projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: flush caches regardless of render condition
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_hw_context_priv.h"
27 #include "r600_pipe.h"
28 #include "r600d.h"
29 #include "util/u_memory.h"
30 #include <errno.h>
31
32 #define GROUP_FORCE_NEW_BLOCK 0
33
34 /* Get backends mask */
35 void r600_get_backend_mask(struct r600_context *ctx)
36 {
37 struct r600_resource *buffer;
38 u32 *results;
39 unsigned num_backends = ctx->screen->info.r600_num_backends;
40 unsigned i, mask = 0;
41
42 /* if backend_map query is supported by the kernel */
43 if (ctx->screen->info.r600_backend_map_valid) {
44 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
45 unsigned backend_map = ctx->screen->info.r600_backend_map;
46 unsigned item_width, item_mask;
47
48 if (ctx->screen->chip_class >= EVERGREEN) {
49 item_width = 4;
50 item_mask = 0x7;
51 } else {
52 item_width = 2;
53 item_mask = 0x3;
54 }
55
56 while(num_tile_pipes--) {
57 i = backend_map & item_mask;
58 mask |= (1<<i);
59 backend_map >>= item_width;
60 }
61 if (mask != 0) {
62 ctx->backend_mask = mask;
63 return;
64 }
65 }
66
67 /* otherwise backup path for older kernels */
68
69 /* create buffer for event data */
70 buffer = (struct r600_resource*)
71 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
72 PIPE_USAGE_STAGING, ctx->max_db*16);
73 if (!buffer)
74 goto err;
75
76 /* initialize buffer with zeroes */
77 results = ctx->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE);
78 if (results) {
79 memset(results, 0, ctx->max_db * 4 * 4);
80 ctx->ws->buffer_unmap(buffer->buf);
81
82 /* emit EVENT_WRITE for ZPASS_DONE */
83 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
84 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
85 ctx->pm4[ctx->pm4_cdwords++] = 0;
86 ctx->pm4[ctx->pm4_cdwords++] = 0;
87
88 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
89 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE);
90
91 /* analyze results */
92 results = ctx->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_READ);
93 if (results) {
94 for(i = 0; i < ctx->max_db; i++) {
95 /* at least highest bit will be set if backend is used */
96 if (results[i*4 + 1])
97 mask |= (1<<i);
98 }
99 ctx->ws->buffer_unmap(buffer->buf);
100 }
101 }
102
103 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
104
105 if (mask != 0) {
106 ctx->backend_mask = mask;
107 return;
108 }
109
110 err:
111 /* fallback to old method - set num_backends lower bits to 1 */
112 ctx->backend_mask = (~((u32)0))>>(32-num_backends);
113 return;
114 }
115
116 static inline void r600_context_ps_partial_flush(struct r600_context *ctx)
117 {
118 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
119 return;
120
121 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
122 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
123
124 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
125 }
126
127 void r600_init_cs(struct r600_context *ctx)
128 {
129 /* R6xx requires this packet at the start of each command buffer */
130 if (ctx->screen->family < CHIP_RV770) {
131 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_START_3D_CMDBUF, 0, 0);
132 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
133 }
134 /* All asics require this one */
135 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_CONTEXT_CONTROL, 1, 0);
136 ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
137 ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
138
139 ctx->init_dwords = ctx->pm4_cdwords;
140 }
141
142 static void r600_init_block(struct r600_context *ctx,
143 struct r600_block *block,
144 const struct r600_reg *reg, int index, int nreg,
145 unsigned opcode, unsigned offset_base)
146 {
147 int i = index;
148 int j, n = nreg;
149
150 /* initialize block */
151 if (opcode == PKT3_SET_RESOURCE) {
152 block->flags = BLOCK_FLAG_RESOURCE;
153 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; /* dirty all blocks at start */
154 } else {
155 block->flags = 0;
156 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
157 }
158 block->start_offset = reg[i].offset;
159 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
160 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
161 block->reg = &block->pm4[block->pm4_ndwords];
162 block->pm4_ndwords += n;
163 block->nreg = n;
164 block->nreg_dirty = n;
165 LIST_INITHEAD(&block->list);
166 LIST_INITHEAD(&block->enable_list);
167
168 for (j = 0; j < n; j++) {
169 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
170 block->flags |= REG_FLAG_DIRTY_ALWAYS;
171 }
172 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
173 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
174 block->status |= R600_BLOCK_STATUS_ENABLED;
175 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
176 LIST_ADDTAIL(&block->list,&ctx->dirty);
177 }
178 }
179 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
180 block->flags |= REG_FLAG_FLUSH_CHANGE;
181 }
182
183 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
184 block->nbo++;
185 assert(block->nbo < R600_BLOCK_MAX_BO);
186 block->pm4_bo_index[j] = block->nbo;
187 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
188 block->pm4[block->pm4_ndwords++] = 0x00000000;
189 if (reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
190 block->reloc[block->nbo].flush_flags = 0;
191 block->reloc[block->nbo].flush_mask = 0;
192 } else {
193 block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags;
194 block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask;
195 }
196 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
197 }
198 if ((ctx->screen->family > CHIP_R600) &&
199 (ctx->screen->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
200 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
201 block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags;
202 }
203 }
204 for (j = 0; j < n; j++) {
205 if (reg[i+j].flush_flags) {
206 block->pm4_flush_ndwords += 7;
207 }
208 }
209 /* check that we stay in limit */
210 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
211 }
212
213 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
214 unsigned opcode, unsigned offset_base)
215 {
216 struct r600_block *block;
217 struct r600_range *range;
218 int offset;
219
220 for (unsigned i = 0, n = 0; i < nreg; i += n) {
221 /* ignore new block balise */
222 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
223 n = 1;
224 continue;
225 }
226
227 /* ignore regs not on R600 on R600 */
228 if ((reg[i].flags & REG_FLAG_NOT_R600) && ctx->screen->family == CHIP_R600) {
229 n = 1;
230 continue;
231 }
232
233 /* register that need relocation are in their own group */
234 /* find number of consecutive registers */
235 n = 0;
236 offset = reg[i].offset;
237 while (reg[i + n].offset == offset) {
238 n++;
239 offset += 4;
240 if ((n + i) >= nreg)
241 break;
242 if (n >= (R600_BLOCK_MAX_REG - 2))
243 break;
244 }
245
246 /* allocate new block */
247 block = calloc(1, sizeof(struct r600_block));
248 if (block == NULL) {
249 return -ENOMEM;
250 }
251 ctx->nblocks++;
252 for (int j = 0; j < n; j++) {
253 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
254 /* create block table if it doesn't exist */
255 if (!range->blocks)
256 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
257 if (!range->blocks)
258 return -1;
259
260 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
261 }
262
263 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
264
265 }
266 return 0;
267 }
268
269 /* R600/R700 configuration */
270 static const struct r600_reg r600_config_reg_list[] = {
271 {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
272 {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
273 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
274 {R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
275 {R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
276 {R_008C10_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
277 {R_008C14_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
278 {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
279 {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
280 {R_009714_VC_ENHANCE, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
281 {R_009830_DB_DEBUG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
282 {R_009838_DB_WATERMARKS, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
283 };
284
285 static const struct r600_reg r600_ctl_const_list[] = {
286 {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
287 {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
288 };
289
290 static const struct r600_reg r600_context_reg_list[] = {
291 {R_028350_SX_MISC, 0, 0, 0},
292 {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
293 {R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
294 {R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
295 {R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
296 {R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
297 {R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
298 {R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
299 {R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0},
300 {R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0},
301 {R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
302 {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
303 {R_028A14_VGT_HOS_CNTL, 0, 0, 0},
304 {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
305 {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
306 {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
307 {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
308 {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
309 {R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
310 {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
311 {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
312 {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
313 {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
314 {R_028A40_VGT_GS_MODE, 0, 0, 0},
315 {R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0},
316 {R_028AB0_VGT_STRMOUT_EN, 0, 0, 0},
317 {R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
318 {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
319 {R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0},
320 {R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
321 {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
322 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
323 {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0},
324 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
325 {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
326 {R_028060_CB_COLOR0_SIZE, 0, 0, 0},
327 {R_028080_CB_COLOR0_VIEW, 0, 0, 0},
328 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
329 {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0},
330 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
331 {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0},
332 {R_028100_CB_COLOR0_MASK, 0, 0, 0},
333 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
334 {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0},
335 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
336 {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
337 {R_028064_CB_COLOR1_SIZE, 0, 0, 0},
338 {R_028084_CB_COLOR1_VIEW, 0, 0, 0},
339 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
340 {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0},
341 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
342 {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0},
343 {R_028104_CB_COLOR1_MASK, 0, 0, 0},
344 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
345 {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0},
346 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
347 {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
348 {R_028068_CB_COLOR2_SIZE, 0, 0, 0},
349 {R_028088_CB_COLOR2_VIEW, 0, 0, 0},
350 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
351 {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0},
352 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
353 {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0},
354 {R_028108_CB_COLOR2_MASK, 0, 0, 0},
355 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
356 {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0},
357 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
358 {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
359 {R_02806C_CB_COLOR3_SIZE, 0, 0, 0},
360 {R_02808C_CB_COLOR3_VIEW, 0, 0, 0},
361 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
362 {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0},
363 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
364 {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0},
365 {R_02810C_CB_COLOR3_MASK, 0, 0, 0},
366 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
367 {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0},
368 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
369 {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
370 {R_028070_CB_COLOR4_SIZE, 0, 0, 0},
371 {R_028090_CB_COLOR4_VIEW, 0, 0, 0},
372 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
373 {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0},
374 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
375 {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0},
376 {R_028110_CB_COLOR4_MASK, 0, 0, 0},
377 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
378 {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0},
379 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
380 {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
381 {R_028074_CB_COLOR5_SIZE, 0, 0, 0},
382 {R_028094_CB_COLOR5_VIEW, 0, 0, 0},
383 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
384 {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0},
385 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
386 {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0},
387 {R_028114_CB_COLOR5_MASK, 0, 0, 0},
388 {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0},
389 {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
390 {R_028078_CB_COLOR6_SIZE, 0, 0, 0},
391 {R_028098_CB_COLOR6_VIEW, 0, 0, 0},
392 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
393 {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0},
394 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
395 {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0},
396 {R_028118_CB_COLOR6_MASK, 0, 0, 0},
397 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
398 {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0},
399 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
400 {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
401 {R_02807C_CB_COLOR7_SIZE, 0, 0, 0},
402 {R_02809C_CB_COLOR7_VIEW, 0, 0, 0},
403 {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0},
404 {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0},
405 {R_02811C_CB_COLOR7_MASK, 0, 0, 0},
406 {R_028120_CB_CLEAR_RED, 0, 0, 0},
407 {R_028124_CB_CLEAR_GREEN, 0, 0, 0},
408 {R_028128_CB_CLEAR_BLUE, 0, 0, 0},
409 {R_02812C_CB_CLEAR_ALPHA, 0, 0, 0},
410 {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
411 {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
412 {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
413 {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
414 {R_02823C_CB_SHADER_MASK, 0, 0, 0},
415 {R_028238_CB_TARGET_MASK, 0, 0, 0},
416 {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
417 {R_028414_CB_BLEND_RED, 0, 0, 0},
418 {R_028418_CB_BLEND_GREEN, 0, 0, 0},
419 {R_02841C_CB_BLEND_BLUE, 0, 0, 0},
420 {R_028420_CB_BLEND_ALPHA, 0, 0, 0},
421 {R_028424_CB_FOG_RED, 0, 0, 0},
422 {R_028428_CB_FOG_GREEN, 0, 0, 0},
423 {R_02842C_CB_FOG_BLUE, 0, 0, 0},
424 {R_028430_DB_STENCILREFMASK, 0, 0, 0},
425 {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
426 {R_028438_SX_ALPHA_REF, 0, 0, 0},
427 {R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
428 {R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0},
429 {R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0},
430 {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0, 0},
431 {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0, 0},
432 {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0, 0},
433 {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0, 0},
434 {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0, 0},
435 {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0, 0},
436 {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0, 0},
437 {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0, 0},
438 {R_0287A0_CB_SHADER_CONTROL, 0, 0, 0},
439 {R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
440 {R_028804_CB_BLEND_CONTROL, 0, 0, 0},
441 {R_028808_CB_COLOR_CONTROL, 0, 0, 0},
442 {R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
443 {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
444 {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
445 {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0},
446 {R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0},
447 {R_028C34_CB_CLRCMP_SRC, 0, 0, 0},
448 {R_028C38_CB_CLRCMP_DST, 0, 0, 0},
449 {R_028C3C_CB_CLRCMP_MSK, 0, 0, 0},
450 {R_028C48_PA_SC_AA_MASK, 0, 0, 0},
451 {R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
452 {R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0},
453 {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0},
454 {R_028000_DB_DEPTH_SIZE, 0, 0, 0},
455 {R_028004_DB_DEPTH_VIEW, 0, 0, 0},
456 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
457 {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0},
458 {R_028D0C_DB_RENDER_CONTROL, 0, 0, 0},
459 {R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0},
460 {R_028D24_DB_HTILE_SURFACE, 0, 0, 0},
461 {R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0},
462 {R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0},
463 {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
464 {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
465 {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
466 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
467 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
468 {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
469 {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
470 {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
471 {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
472 {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
473 {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
474 {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
475 {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
476 {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
477 {R_028230_PA_SC_EDGERULE, 0, 0, 0},
478 {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
479 {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
480 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
481 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
482 {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
483 {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
484 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
485 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
486 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
487 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
488 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
489 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
490 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
491 {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
492 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
493 {R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
494 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
495 {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
496 {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
497 {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
498 {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
499 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0},
500 {R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0},
501 {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
502 {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
503 {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
504 {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
505 {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
506 {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
507 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
508 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
509 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
510 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
511 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
512 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
513 {R_028E20_PA_CL_UCP0_X, 0, 0, 0},
514 {R_028E24_PA_CL_UCP0_Y, 0, 0, 0},
515 {R_028E28_PA_CL_UCP0_Z, 0, 0, 0},
516 {R_028E2C_PA_CL_UCP0_W, 0, 0, 0},
517 {R_028E30_PA_CL_UCP1_X, 0, 0, 0},
518 {R_028E34_PA_CL_UCP1_Y, 0, 0, 0},
519 {R_028E38_PA_CL_UCP1_Z, 0, 0, 0},
520 {R_028E3C_PA_CL_UCP1_W, 0, 0, 0},
521 {R_028E40_PA_CL_UCP2_X, 0, 0, 0},
522 {R_028E44_PA_CL_UCP2_Y, 0, 0, 0},
523 {R_028E48_PA_CL_UCP2_Z, 0, 0, 0},
524 {R_028E4C_PA_CL_UCP2_W, 0, 0, 0},
525 {R_028E50_PA_CL_UCP3_X, 0, 0, 0},
526 {R_028E54_PA_CL_UCP3_Y, 0, 0, 0},
527 {R_028E58_PA_CL_UCP3_Z, 0, 0, 0},
528 {R_028E5C_PA_CL_UCP3_W, 0, 0, 0},
529 {R_028E60_PA_CL_UCP4_X, 0, 0, 0},
530 {R_028E64_PA_CL_UCP4_Y, 0, 0, 0},
531 {R_028E68_PA_CL_UCP4_Z, 0, 0, 0},
532 {R_028E6C_PA_CL_UCP4_W, 0, 0, 0},
533 {R_028E70_PA_CL_UCP5_X, 0, 0, 0},
534 {R_028E74_PA_CL_UCP5_Y, 0, 0, 0},
535 {R_028E78_PA_CL_UCP5_Z, 0, 0, 0},
536 {R_028E7C_PA_CL_UCP5_W, 0, 0, 0},
537 {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
538 {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
539 {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
540 {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
541 {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
542 {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
543 {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
544 {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
545 {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
546 {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
547 {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
548 {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
549 {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
550 {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
551 {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
552 {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
553 {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
554 {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
555 {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
556 {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
557 {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
558 {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
559 {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
560 {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
561 {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
562 {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
563 {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
564 {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
565 {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
566 {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
567 {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
568 {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
569 {R_028614_SPI_VS_OUT_ID_0, 0, 0, 0},
570 {R_028618_SPI_VS_OUT_ID_1, 0, 0, 0},
571 {R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0},
572 {R_028620_SPI_VS_OUT_ID_3, 0, 0, 0},
573 {R_028624_SPI_VS_OUT_ID_4, 0, 0, 0},
574 {R_028628_SPI_VS_OUT_ID_5, 0, 0, 0},
575 {R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0},
576 {R_028630_SPI_VS_OUT_ID_7, 0, 0, 0},
577 {R_028634_SPI_VS_OUT_ID_8, 0, 0, 0},
578 {R_028638_SPI_VS_OUT_ID_9, 0, 0, 0},
579 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
580 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
581 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
582 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
583 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0},
584 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
585 {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
586 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
587 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0},
588 {R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0},
589 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0},
590 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
591 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
592 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
593 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
594 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
595 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
596 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
597 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
598 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
599 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
600 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
601 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
602 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
603 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
604 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
605 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
606 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
607 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
608 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
609 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
610 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
611 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
612 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
613 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
614 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
615 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
616 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
617 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
618 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
619 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
620 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
621 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
622 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
623 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
624 {R_0286D8_SPI_INPUT_Z, 0, 0, 0},
625 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
626 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
627 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
628 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0},
629 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0},
630 {R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0},
631 {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
632 {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
633 {R_028408_VGT_INDX_OFFSET, 0, 0, 0},
634 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
635 {R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0},
636 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0},
637 {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0},
638 {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0},
639 };
640
641 /* SHADER RESOURCE R600/R700 */
642 int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base)
643 {
644 int i;
645 struct r600_block *block;
646 range->blocks = calloc(nblocks, sizeof(struct r600_block *));
647 if (range->blocks == NULL)
648 return -ENOMEM;
649
650 reg[0].offset += offset;
651 for (i = 0; i < nblocks; i++) {
652 block = calloc(1, sizeof(struct r600_block));
653 if (block == NULL) {
654 return -ENOMEM;
655 }
656 ctx->nblocks++;
657 range->blocks[i] = block;
658 r600_init_block(ctx, block, reg, 0, nreg, PKT3_SET_RESOURCE, offset_base);
659
660 reg[0].offset += stride;
661 }
662 return 0;
663 }
664
665
666 static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
667 {
668 struct r600_reg r600_shader_resource[] = {
669 {R_038000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
670 {R_038004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
671 {R_038008_RESOURCE0_WORD2, 0, 0, 0},
672 {R_03800C_RESOURCE0_WORD3, 0, 0, 0},
673 {R_038010_RESOURCE0_WORD4, 0, 0, 0},
674 {R_038014_RESOURCE0_WORD5, 0, 0, 0},
675 {R_038018_RESOURCE0_WORD6, 0, 0, 0},
676 };
677 unsigned nreg = Elements(r600_shader_resource);
678
679 return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, R600_RESOURCE_OFFSET);
680 }
681
682 /* SHADER SAMPLER R600/R700 */
683 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
684 {
685 struct r600_reg r600_shader_sampler[] = {
686 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
687 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
688 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
689 };
690 unsigned nreg = Elements(r600_shader_sampler);
691
692 for (int i = 0; i < nreg; i++) {
693 r600_shader_sampler[i].offset += offset;
694 }
695 return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET);
696 }
697
698 /* SHADER SAMPLER BORDER R600/R700 */
699 static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
700 {
701 struct r600_reg r600_shader_sampler_border[] = {
702 {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
703 {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
704 {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
705 {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
706 };
707 unsigned nreg = Elements(r600_shader_sampler_border);
708
709 for (int i = 0; i < nreg; i++) {
710 r600_shader_sampler_border[i].offset += offset;
711 }
712 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
713 }
714
715 static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
716 {
717 unsigned nreg = 32;
718 struct r600_reg r600_loop_consts[32];
719 int i;
720
721 for (i = 0; i < nreg; i++) {
722 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
723 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
724 r600_loop_consts[i].flush_flags = 0;
725 r600_loop_consts[i].flush_mask = 0;
726 }
727 return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET);
728 }
729
730 static void r600_free_resource_range(struct r600_context *ctx, struct r600_range *range, int nblocks)
731 {
732 struct r600_block *block;
733 int i;
734 for (i = 0; i < nblocks; i++) {
735 block = range->blocks[i];
736 if (block) {
737 for (int k = 1; k <= block->nbo; k++)
738 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
739 free(block);
740 }
741 }
742 free(range->blocks);
743
744 }
745
746 /* initialize */
747 void r600_context_fini(struct r600_context *ctx)
748 {
749 struct r600_block *block;
750 struct r600_range *range;
751
752 for (int i = 0; i < NUM_RANGES; i++) {
753 if (!ctx->range[i].blocks)
754 continue;
755 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
756 block = ctx->range[i].blocks[j];
757 if (block) {
758 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
759 range = &ctx->range[CTX_RANGE_ID(offset)];
760 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
761 }
762 for (int k = 1; k <= block->nbo; k++) {
763 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
764 }
765 free(block);
766 }
767 }
768 free(ctx->range[i].blocks);
769 }
770 r600_free_resource_range(ctx, &ctx->ps_resources, ctx->num_ps_resources);
771 r600_free_resource_range(ctx, &ctx->vs_resources, ctx->num_vs_resources);
772 r600_free_resource_range(ctx, &ctx->fs_resources, ctx->num_fs_resources);
773 free(ctx->range);
774 free(ctx->blocks);
775 free(ctx->bo);
776 ctx->ws->cs_destroy(ctx->cs);
777
778 memset(ctx, 0, sizeof(struct r600_context));
779 }
780
781 static void r600_add_resource_block(struct r600_context *ctx, struct r600_range *range, int num_blocks, int *index)
782 {
783 int c = *index;
784 for (int j = 0; j < num_blocks; j++) {
785 if (!range->blocks[j])
786 continue;
787
788 ctx->blocks[c++] = range->blocks[j];
789 }
790 *index = c;
791 }
792
793 int r600_setup_block_table(struct r600_context *ctx)
794 {
795 /* setup block table */
796 int c = 0;
797 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
798 if (!ctx->blocks)
799 return -ENOMEM;
800 for (int i = 0; i < NUM_RANGES; i++) {
801 if (!ctx->range[i].blocks)
802 continue;
803 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
804 if (!ctx->range[i].blocks[j])
805 continue;
806
807 add = 1;
808 for (int k = 0; k < c; k++) {
809 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
810 add = 0;
811 break;
812 }
813 }
814 if (add) {
815 assert(c < ctx->nblocks);
816 ctx->blocks[c++] = ctx->range[i].blocks[j];
817 j += (ctx->range[i].blocks[j]->nreg) - 1;
818 }
819 }
820 }
821
822 r600_add_resource_block(ctx, &ctx->ps_resources, ctx->num_ps_resources, &c);
823 r600_add_resource_block(ctx, &ctx->vs_resources, ctx->num_vs_resources, &c);
824 r600_add_resource_block(ctx, &ctx->fs_resources, ctx->num_fs_resources, &c);
825 return 0;
826 }
827
828 int r600_context_init(struct r600_context *ctx, struct r600_screen *screen)
829 {
830 int r;
831
832 memset(ctx, 0, sizeof(struct r600_context));
833 ctx->screen = screen;
834 ctx->ws = screen->ws;
835
836 LIST_INITHEAD(&ctx->active_query_list);
837
838 /* init dirty list */
839 LIST_INITHEAD(&ctx->dirty);
840 LIST_INITHEAD(&ctx->resource_dirty);
841 LIST_INITHEAD(&ctx->enable_list);
842
843 ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
844 if (!ctx->range) {
845 r = -ENOMEM;
846 goto out_err;
847 }
848
849 /* add blocks */
850 r = r600_context_add_block(ctx, r600_config_reg_list,
851 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
852 if (r)
853 goto out_err;
854 r = r600_context_add_block(ctx, r600_context_reg_list,
855 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
856 if (r)
857 goto out_err;
858 r = r600_context_add_block(ctx, r600_ctl_const_list,
859 Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
860 if (r)
861 goto out_err;
862
863 /* PS SAMPLER BORDER */
864 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
865 r = r600_state_sampler_border_init(ctx, offset);
866 if (r)
867 goto out_err;
868 }
869
870 /* VS SAMPLER BORDER */
871 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
872 r = r600_state_sampler_border_init(ctx, offset);
873 if (r)
874 goto out_err;
875 }
876 /* PS SAMPLER */
877 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
878 r = r600_state_sampler_init(ctx, offset);
879 if (r)
880 goto out_err;
881 }
882 /* VS SAMPLER */
883 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
884 r = r600_state_sampler_init(ctx, offset);
885 if (r)
886 goto out_err;
887 }
888
889 ctx->num_ps_resources = 160;
890 ctx->num_vs_resources = 160;
891 ctx->num_fs_resources = 16;
892 r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 160, 0x1c);
893 if (r)
894 goto out_err;
895 r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1180, 160, 0x1c);
896 if (r)
897 goto out_err;
898 r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x2300, 16, 0x1c);
899 if (r)
900 goto out_err;
901
902 /* PS loop const */
903 r600_loop_const_init(ctx, 0);
904 /* VS loop const */
905 r600_loop_const_init(ctx, 32);
906
907 r = r600_setup_block_table(ctx);
908 if (r)
909 goto out_err;
910
911 ctx->cs = screen->ws->cs_create(screen->ws);
912
913 /* allocate cs variables */
914 ctx->bo = calloc(RADEON_MAX_CMDBUF_DWORDS, sizeof(void *));
915 if (ctx->bo == NULL) {
916 r = -ENOMEM;
917 goto out_err;
918 }
919 ctx->pm4_ndwords = RADEON_MAX_CMDBUF_DWORDS;
920 ctx->pm4 = ctx->cs->buf;
921
922 r600_init_cs(ctx);
923 /* save 16dwords space for fence mecanism */
924 ctx->pm4_ndwords -= 16;
925 ctx->max_db = 4;
926 return 0;
927 out_err:
928 r600_context_fini(ctx);
929 return r;
930 }
931
932 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
933 boolean count_draw_in)
934 {
935 /* The number of dwords we already used in the CS so far. */
936 num_dw += ctx->pm4_cdwords;
937
938 if (count_draw_in) {
939 /* The number of dwords all the dirty states would take. */
940 num_dw += ctx->pm4_dirty_cdwords;
941
942 /* The upper-bound of how much a draw command would take. */
943 num_dw += R600_MAX_DRAW_CS_DWORDS;
944 }
945
946 /* Count in queries_suspend. */
947 num_dw += ctx->num_cs_dw_queries_suspend;
948
949 /* Count in render_condition(NULL) at the end of CS. */
950 if (ctx->predicate_drawing) {
951 num_dw += 3;
952 }
953
954 /* Flush if there's not enough space. */
955 if (num_dw > ctx->pm4_ndwords) {
956 r600_context_flush(ctx, RADEON_FLUSH_ASYNC);
957 }
958 }
959
960 /* Flushes all surfaces */
961 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags)
962 {
963 r600_need_cs_space(ctx, 5, FALSE);
964
965 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
966 ctx->pm4[ctx->pm4_cdwords++] = flush_flags; /* CP_COHER_CNTL */
967 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
968 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
969 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
970 }
971
972 void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
973 unsigned flush_mask, struct r600_resource *bo)
974 {
975 /* if bo has already been flushed */
976 if (!(~bo->cs_buf->last_flush & flush_flags)) {
977 bo->cs_buf->last_flush &= flush_mask;
978 return;
979 }
980
981 if ((ctx->screen->family < CHIP_RV770) &&
982 (G_0085F0_CB_ACTION_ENA(flush_flags) ||
983 G_0085F0_DB_ACTION_ENA(flush_flags))) {
984 if (ctx->flags & R600_CONTEXT_CHECK_EVENT_FLUSH) {
985 /* the rv670 seems to fail fbo-generatemipmap unless we flush the CB1 dest base ena */
986 if ((bo->cs_buf->binding & BO_BOUND_TEXTURE) &&
987 (flush_flags & S_0085F0_CB_ACTION_ENA(1))) {
988 if ((ctx->screen->family == CHIP_RV670) ||
989 (ctx->screen->family == CHIP_RS780) ||
990 (ctx->screen->family == CHIP_RS880)) {
991 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
992 ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1); /* CP_COHER_CNTL */
993 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
994 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
995 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
996 }
997 }
998
999 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1000 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
1001 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1002 }
1003 } else {
1004 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
1005 ctx->pm4[ctx->pm4_cdwords++] = flush_flags;
1006 ctx->pm4[ctx->pm4_cdwords++] = (bo->buf->size + 255) >> 8;
1007 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
1008 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
1009 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1010 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, bo, RADEON_USAGE_WRITE);
1011 }
1012 bo->cs_buf->last_flush = (bo->cs_buf->last_flush | flush_flags) & flush_mask;
1013 }
1014
1015 void r600_context_reg(struct r600_context *ctx,
1016 unsigned offset, unsigned value,
1017 unsigned mask)
1018 {
1019 struct r600_range *range;
1020 struct r600_block *block;
1021 unsigned id;
1022 unsigned new_val;
1023 int dirty;
1024
1025 range = &ctx->range[CTX_RANGE_ID(offset)];
1026 block = range->blocks[CTX_BLOCK_ID(offset)];
1027 id = (offset - block->start_offset) >> 2;
1028
1029 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1030
1031 new_val = block->reg[id];
1032 new_val &= ~mask;
1033 new_val |= value;
1034 if (new_val != block->reg[id]) {
1035 dirty |= R600_BLOCK_STATUS_DIRTY;
1036 block->reg[id] = new_val;
1037 }
1038 if (dirty)
1039 r600_context_dirty_block(ctx, block, dirty, id);
1040 }
1041
1042 void r600_context_dirty_block(struct r600_context *ctx,
1043 struct r600_block *block,
1044 int dirty, int index)
1045 {
1046 if ((index + 1) > block->nreg_dirty)
1047 block->nreg_dirty = index + 1;
1048
1049 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
1050 block->status |= R600_BLOCK_STATUS_DIRTY;
1051 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
1052 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
1053 block->status |= R600_BLOCK_STATUS_ENABLED;
1054 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
1055 }
1056 LIST_ADDTAIL(&block->list,&ctx->dirty);
1057
1058 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
1059 r600_context_ps_partial_flush(ctx);
1060 }
1061 }
1062 }
1063
1064 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
1065 {
1066 struct r600_block *block;
1067 unsigned new_val;
1068 int dirty;
1069 for (int i = 0; i < state->nregs; i++) {
1070 unsigned id, reloc_id;
1071 struct r600_pipe_reg *reg = &state->regs[i];
1072
1073 block = reg->block;
1074 id = reg->id;
1075
1076 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1077
1078 new_val = block->reg[id];
1079 new_val &= ~reg->mask;
1080 new_val |= reg->value;
1081 if (new_val != block->reg[id]) {
1082 block->reg[id] = new_val;
1083 dirty |= R600_BLOCK_STATUS_DIRTY;
1084 }
1085 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
1086 dirty |= R600_BLOCK_STATUS_DIRTY;
1087 if (block->pm4_bo_index[id]) {
1088 /* find relocation */
1089 reloc_id = block->pm4_bo_index[id];
1090 pipe_resource_reference((struct pipe_resource**)&block->reloc[reloc_id].bo, &reg->bo->b.b.b);
1091 block->reloc[reloc_id].bo_usage = reg->bo_usage;
1092 /* always force dirty for relocs for now */
1093 dirty |= R600_BLOCK_STATUS_DIRTY;
1094 }
1095
1096 if (dirty)
1097 r600_context_dirty_block(ctx, block, dirty, id);
1098 }
1099 }
1100
1101 static void r600_context_dirty_resource_block(struct r600_context *ctx,
1102 struct r600_block *block,
1103 int dirty, int index)
1104 {
1105 block->nreg_dirty = index + 1;
1106
1107 if ((dirty != (block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
1108 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1109 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
1110 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
1111 block->status |= R600_BLOCK_STATUS_ENABLED;
1112 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
1113 }
1114 LIST_ADDTAIL(&block->list,&ctx->resource_dirty);
1115 }
1116 }
1117
1118 void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block)
1119 {
1120 int dirty;
1121 int num_regs = ctx->screen->chip_class >= EVERGREEN ? 8 : 7;
1122 boolean is_vertex;
1123
1124 if (state == NULL) {
1125 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_RESOURCE_DIRTY);
1126 if (block->reloc[1].bo)
1127 block->reloc[1].bo->cs_buf->binding &= ~BO_BOUND_TEXTURE;
1128
1129 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, NULL);
1130 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL);
1131 LIST_DELINIT(&block->list);
1132 LIST_DELINIT(&block->enable_list);
1133 return;
1134 }
1135
1136 is_vertex = ((state->val[num_regs-1] & 0xc0000000) == 0xc0000000);
1137 dirty = block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY;
1138
1139 if (memcmp(block->reg, state->val, num_regs*4)) {
1140 memcpy(block->reg, state->val, num_regs * 4);
1141 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1142 }
1143
1144 /* if no BOs on block, force dirty */
1145 if (!block->reloc[1].bo || !block->reloc[2].bo)
1146 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1147
1148 if (!dirty) {
1149 if (is_vertex) {
1150 if (block->reloc[1].bo->buf != state->bo[0]->buf)
1151 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1152 } else {
1153 if ((block->reloc[1].bo->buf != state->bo[0]->buf) ||
1154 (block->reloc[2].bo->buf != state->bo[1]->buf))
1155 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1156 }
1157 }
1158
1159 if (dirty) {
1160 if (is_vertex) {
1161 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
1162 * we have single case btw VERTEX & TEXTURE resource
1163 */
1164 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b);
1165 block->reloc[1].bo_usage = state->bo_usage[0];
1166 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL);
1167 } else {
1168 /* TEXTURE RESOURCE */
1169 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b);
1170 block->reloc[1].bo_usage = state->bo_usage[0];
1171 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, &state->bo[1]->b.b.b);
1172 block->reloc[2].bo_usage = state->bo_usage[1];
1173 state->bo[0]->cs_buf->binding |= BO_BOUND_TEXTURE;
1174 }
1175
1176 if (is_vertex)
1177 block->status |= R600_BLOCK_STATUS_RESOURCE_VERTEX;
1178 else
1179 block->status &= ~R600_BLOCK_STATUS_RESOURCE_VERTEX;
1180
1181 r600_context_dirty_resource_block(ctx, block, dirty, num_regs - 1);
1182 }
1183 }
1184
1185 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1186 {
1187 struct r600_block *block = ctx->ps_resources.blocks[rid];
1188
1189 r600_context_pipe_state_set_resource(ctx, state, block);
1190 }
1191
1192 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1193 {
1194 struct r600_block *block = ctx->vs_resources.blocks[rid];
1195
1196 r600_context_pipe_state_set_resource(ctx, state, block);
1197 }
1198
1199 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1200 {
1201 struct r600_block *block = ctx->fs_resources.blocks[rid];
1202
1203 r600_context_pipe_state_set_resource(ctx, state, block);
1204 }
1205
1206 static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1207 {
1208 struct r600_range *range;
1209 struct r600_block *block;
1210 int i;
1211 int dirty;
1212
1213 range = &ctx->range[CTX_RANGE_ID(offset)];
1214 block = range->blocks[CTX_BLOCK_ID(offset)];
1215 if (state == NULL) {
1216 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1217 LIST_DELINIT(&block->list);
1218 LIST_DELINIT(&block->enable_list);
1219 return;
1220 }
1221 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1222 for (i = 0; i < 3; i++) {
1223 if (block->reg[i] != state->regs[i].value) {
1224 block->reg[i] = state->regs[i].value;
1225 dirty |= R600_BLOCK_STATUS_DIRTY;
1226 }
1227 }
1228
1229 if (dirty)
1230 r600_context_dirty_block(ctx, block, dirty, 2);
1231 }
1232
1233
1234 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1235 {
1236 struct r600_range *range;
1237 struct r600_block *block;
1238 int i;
1239 int dirty;
1240
1241 range = &ctx->range[CTX_RANGE_ID(offset)];
1242 block = range->blocks[CTX_BLOCK_ID(offset)];
1243 if (state == NULL) {
1244 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1245 LIST_DELINIT(&block->list);
1246 LIST_DELINIT(&block->enable_list);
1247 return;
1248 }
1249 if (state->nregs <= 3) {
1250 return;
1251 }
1252 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1253 for (i = 0; i < 4; i++) {
1254 if (block->reg[i] != state->regs[i + 3].value) {
1255 block->reg[i] = state->regs[i + 3].value;
1256 dirty |= R600_BLOCK_STATUS_DIRTY;
1257 }
1258 }
1259
1260 /* We have to flush the shaders before we change the border color
1261 * registers, or previous draw commands that haven't completed yet
1262 * will end up using the new border color. */
1263 if (dirty & R600_BLOCK_STATUS_DIRTY)
1264 r600_context_ps_partial_flush(ctx);
1265 if (dirty)
1266 r600_context_dirty_block(ctx, block, dirty, 3);
1267 }
1268
1269 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1270 {
1271 unsigned offset;
1272
1273 offset = 0x0003C000 + id * 0xc;
1274 r600_context_pipe_state_set_sampler(ctx, state, offset);
1275 offset = 0x0000A400 + id * 0x10;
1276 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1277 }
1278
1279 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1280 {
1281 unsigned offset;
1282
1283 offset = 0x0003C0D8 + id * 0xc;
1284 r600_context_pipe_state_set_sampler(ctx, state, offset);
1285 offset = 0x0000A600 + id * 0x10;
1286 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1287 }
1288
1289 struct r600_resource *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
1290 {
1291 struct r600_range *range;
1292 struct r600_block *block;
1293 unsigned id;
1294
1295 range = &ctx->range[CTX_RANGE_ID(offset)];
1296 block = range->blocks[CTX_BLOCK_ID(offset)];
1297 offset -= block->start_offset;
1298 id = block->pm4_bo_index[offset >> 2];
1299 if (block->reloc[id].bo) {
1300 return block->reloc[id].bo;
1301 }
1302 return NULL;
1303 }
1304
1305 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1306 {
1307 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
1308 int cp_dwords = block->pm4_ndwords, start_dword = 0;
1309 int new_dwords = 0;
1310 int nbo = block->nbo;
1311
1312 if (block->nreg_dirty == 0 && optional) {
1313 goto out;
1314 }
1315
1316 if (nbo) {
1317 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1318
1319 for (int j = 0; j < block->nreg; j++) {
1320 if (block->pm4_bo_index[j]) {
1321 /* find relocation */
1322 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
1323 block->pm4[reloc->bo_pm4_index] =
1324 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage);
1325 r600_context_bo_flush(ctx,
1326 reloc->flush_flags,
1327 reloc->flush_mask,
1328 reloc->bo);
1329 nbo--;
1330 if (nbo == 0)
1331 break;
1332 }
1333 }
1334 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1335 }
1336
1337 optional &= (block->nreg_dirty != block->nreg);
1338 if (optional) {
1339 new_dwords = block->nreg_dirty;
1340 start_dword = ctx->pm4_cdwords;
1341 cp_dwords = new_dwords + 2;
1342 }
1343 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4);
1344 ctx->pm4_cdwords += cp_dwords;
1345
1346 if (optional) {
1347 uint32_t newword;
1348
1349 newword = ctx->pm4[start_dword];
1350 newword &= PKT_COUNT_C;
1351 newword |= PKT_COUNT_S(new_dwords);
1352 ctx->pm4[start_dword] = newword;
1353 }
1354 out:
1355 block->status ^= R600_BLOCK_STATUS_DIRTY;
1356 block->nreg_dirty = 0;
1357 LIST_DELINIT(&block->list);
1358 }
1359
1360 void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1361 {
1362 int cp_dwords = block->pm4_ndwords;
1363 int nbo = block->nbo;
1364
1365 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1366
1367 if (block->status & R600_BLOCK_STATUS_RESOURCE_VERTEX) {
1368 nbo = 1;
1369 cp_dwords -= 2; /* don't copy the second NOP */
1370 }
1371
1372 for (int j = 0; j < nbo; j++) {
1373 if (block->pm4_bo_index[j]) {
1374 /* find relocation */
1375 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
1376 block->pm4[reloc->bo_pm4_index] =
1377 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage);
1378 r600_context_bo_flush(ctx,
1379 reloc->flush_flags,
1380 reloc->flush_mask,
1381 reloc->bo);
1382 }
1383 }
1384 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1385
1386 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4);
1387 ctx->pm4_cdwords += cp_dwords;
1388
1389 block->status ^= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1390 block->nreg_dirty = 0;
1391 LIST_DELINIT(&block->list);
1392 }
1393
1394 void r600_context_flush_dest_caches(struct r600_context *ctx)
1395 {
1396 struct r600_resource *cb[8];
1397 struct r600_resource *db;
1398 int i;
1399
1400 if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
1401 return;
1402
1403 db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE);
1404 cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE);
1405 cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE);
1406 cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE);
1407 cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE);
1408 cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE);
1409 cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE);
1410 cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE);
1411 cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE);
1412
1413 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1414 /* flush the color buffers */
1415 for (i = 0; i < 8; i++) {
1416 if (!cb[i])
1417 continue;
1418
1419 r600_context_bo_flush(ctx,
1420 (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
1421 S_0085F0_CB_ACTION_ENA(1),
1422 0, cb[i]);
1423 }
1424 if (db) {
1425 r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1), 0, db);
1426 }
1427 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1428 ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
1429 }
1430
1431 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
1432 {
1433 unsigned ndwords = 7;
1434 struct r600_block *dirty_block = NULL;
1435 struct r600_block *next_block;
1436 uint32_t *pm4;
1437
1438 if (draw->indices) {
1439 ndwords = 11;
1440 }
1441 /* when increasing ndwords, bump the max limit too */
1442 assert(ndwords <= R600_MAX_DRAW_CS_DWORDS);
1443
1444 /* queries need some special values
1445 * (this is non-zero if any query is active) */
1446 if (ctx->num_cs_dw_queries_suspend) {
1447 if (ctx->screen->family >= CHIP_RV770) {
1448 r600_context_reg(ctx,
1449 R_028D0C_DB_RENDER_CONTROL,
1450 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
1451 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
1452 }
1453 r600_context_reg(ctx,
1454 R_028D10_DB_RENDER_OVERRIDE,
1455 S_028D10_NOOP_CULL_DISABLE(1),
1456 S_028D10_NOOP_CULL_DISABLE(1));
1457 }
1458
1459 /* update the max dword count to make sure we have enough space
1460 * reserved for flushing the destination caches */
1461 ctx->pm4_ndwords = RADEON_MAX_CMDBUF_DWORDS - ctx->num_dest_buffers * 7 - 16;
1462
1463 r600_need_cs_space(ctx, 0, TRUE);
1464
1465 /* at this point everything is flushed and ctx->pm4_cdwords = 0 */
1466 if (unlikely((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords)) {
1467 R600_ERR("context is too big to be scheduled\n");
1468 return;
1469 }
1470
1471 /* enough room to copy packet */
1472 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty, list) {
1473 r600_context_block_emit_dirty(ctx, dirty_block);
1474 }
1475
1476 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->resource_dirty, list) {
1477 r600_context_block_resource_emit_dirty(ctx, dirty_block);
1478 }
1479
1480 /* draw packet */
1481 pm4 = &ctx->pm4[ctx->pm4_cdwords];
1482
1483 pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
1484 pm4[1] = draw->vgt_index_type;
1485 pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
1486 pm4[3] = draw->vgt_num_instances;
1487 if (draw->indices) {
1488 pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
1489 pm4[5] = draw->indices_bo_offset;
1490 pm4[6] = 0;
1491 pm4[7] = draw->vgt_num_indices;
1492 pm4[8] = draw->vgt_draw_initiator;
1493 pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
1494 pm4[10] = r600_context_bo_reloc(ctx, draw->indices, RADEON_USAGE_READ);
1495 } else {
1496 pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
1497 pm4[5] = draw->vgt_num_indices;
1498 pm4[6] = draw->vgt_draw_initiator;
1499 }
1500 ctx->pm4_cdwords += ndwords;
1501
1502 ctx->flags |= (R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING);
1503
1504 /* all dirty state have been scheduled in current cs */
1505 ctx->pm4_dirty_cdwords = 0;
1506 }
1507
1508 void r600_context_flush(struct r600_context *ctx, unsigned flags)
1509 {
1510 struct r600_block *enable_block = NULL;
1511 bool queries_suspended = false;
1512
1513 if (ctx->pm4_cdwords == ctx->init_dwords)
1514 return;
1515
1516 /* suspend queries */
1517 if (ctx->num_cs_dw_queries_suspend) {
1518 r600_context_queries_suspend(ctx);
1519 queries_suspended = true;
1520 }
1521
1522 if (ctx->screen->chip_class >= EVERGREEN)
1523 evergreen_context_flush_dest_caches(ctx);
1524 else
1525 r600_context_flush_dest_caches(ctx);
1526
1527 /* partial flush is needed to avoid lockups on some chips with user fences */
1528 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1529 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1530
1531 /* Flush the CS. */
1532 ctx->cs->cdw = ctx->pm4_cdwords;
1533 ctx->ws->cs_flush(ctx->cs, flags);
1534
1535 /* We need to get the pointer to the other CS,
1536 * the command streams are double-buffered. */
1537 ctx->pm4 = ctx->cs->buf;
1538
1539 /* restart */
1540 for (int i = 0; i < ctx->creloc; i++) {
1541 ctx->bo[i]->cs_buf->last_flush = 0;
1542 pipe_resource_reference((struct pipe_resource**)&ctx->bo[i], NULL);
1543 }
1544 ctx->creloc = 0;
1545 ctx->pm4_dirty_cdwords = 0;
1546 ctx->pm4_cdwords = 0;
1547 ctx->flags = 0;
1548
1549 r600_init_cs(ctx);
1550
1551 /* resume queries */
1552 if (queries_suspended) {
1553 r600_context_queries_resume(ctx);
1554 }
1555
1556 /* set all valid group as dirty so they get reemited on
1557 * next draw command
1558 */
1559 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
1560 if (!(enable_block->flags & BLOCK_FLAG_RESOURCE)) {
1561 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
1562 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
1563 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
1564 }
1565 } else {
1566 if(!(enable_block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) {
1567 LIST_ADDTAIL(&enable_block->list,&ctx->resource_dirty);
1568 enable_block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1569 }
1570 }
1571 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords +
1572 enable_block->pm4_flush_ndwords;
1573 enable_block->nreg_dirty = enable_block->nreg;
1574 }
1575 }
1576
1577 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
1578 {
1579 r600_need_cs_space(ctx, 10, FALSE);
1580
1581 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1582 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1583 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1584 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1585 ctx->pm4[ctx->pm4_cdwords++] = offset << 2; /* ADDRESS_LO */
1586 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24); /* DATA_SEL | INT_EN | ADDRESS_HI */
1587 ctx->pm4[ctx->pm4_cdwords++] = value; /* DATA_LO */
1588 ctx->pm4[ctx->pm4_cdwords++] = 0; /* DATA_HI */
1589 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1590 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE);
1591 }
1592
1593 static unsigned r600_query_read_result(char *map, unsigned start_index, unsigned end_index,
1594 bool test_status_bit)
1595 {
1596 uint32_t *current_result = (uint32_t*)map;
1597 uint64_t start, end;
1598
1599 start = (uint64_t)current_result[start_index] |
1600 (uint64_t)current_result[start_index+1] << 32;
1601 end = (uint64_t)current_result[end_index] |
1602 (uint64_t)current_result[end_index+1] << 32;
1603
1604 if (!test_status_bit ||
1605 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
1606 return end - start;
1607 }
1608 return 0;
1609 }
1610
1611 static boolean r600_query_result(struct r600_context *ctx, struct r600_query *query, boolean wait)
1612 {
1613 unsigned results_base = query->results_start;
1614 char *map;
1615
1616 map = ctx->ws->buffer_map(query->buffer->buf, ctx->cs,
1617 PIPE_TRANSFER_READ |
1618 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK));
1619 if (!map)
1620 return FALSE;
1621
1622 /* count all results across all data blocks */
1623 switch (query->type) {
1624 case PIPE_QUERY_OCCLUSION_COUNTER:
1625 while (results_base != query->results_end) {
1626 query->result +=
1627 r600_query_read_result(map + results_base, 0, 2, true);
1628 results_base = (results_base + 16) % query->buffer->b.b.b.width0;
1629 }
1630 break;
1631 case PIPE_QUERY_TIME_ELAPSED:
1632 while (results_base != query->results_end) {
1633 query->result +=
1634 r600_query_read_result(map + results_base, 0, 2, false);
1635 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0;
1636 }
1637 break;
1638 default:
1639 assert(0);
1640 }
1641
1642 query->results_start = query->results_end;
1643 ctx->ws->buffer_unmap(query->buffer->buf);
1644 return TRUE;
1645 }
1646
1647 void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
1648 {
1649 unsigned new_results_end;
1650
1651 r600_need_cs_space(ctx, query->num_cs_dw * 2, TRUE);
1652
1653 new_results_end = (query->results_end + query->result_size) % query->buffer->b.b.b.width0;
1654
1655 /* collect current results if query buffer is full */
1656 if (new_results_end == query->results_start) {
1657 r600_query_result(ctx, query, TRUE);
1658 }
1659
1660 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) {
1661 u32 *results;
1662 int i;
1663
1664 results = ctx->ws->buffer_map(query->buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE);
1665 if (results) {
1666 results = (u32*)((char*)results + query->results_end);
1667 memset(results, 0, query->result_size);
1668
1669 /* Set top bits for unused backends */
1670 for (i = 0; i < ctx->max_db; i++) {
1671 if (!(ctx->backend_mask & (1<<i))) {
1672 results[(i * 4)+1] = 0x80000000;
1673 results[(i * 4)+3] = 0x80000000;
1674 }
1675 }
1676 ctx->ws->buffer_unmap(query->buffer->buf);
1677 }
1678 }
1679
1680 /* emit begin query */
1681 switch (query->type) {
1682 case PIPE_QUERY_OCCLUSION_COUNTER:
1683 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1684 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1685 ctx->pm4[ctx->pm4_cdwords++] = query->results_end;
1686 ctx->pm4[ctx->pm4_cdwords++] = 0;
1687 break;
1688 case PIPE_QUERY_TIME_ELAPSED:
1689 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1690 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1691 ctx->pm4[ctx->pm4_cdwords++] = query->results_end;
1692 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1693 ctx->pm4[ctx->pm4_cdwords++] = 0;
1694 ctx->pm4[ctx->pm4_cdwords++] = 0;
1695 break;
1696 default:
1697 assert(0);
1698 }
1699 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1700 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE);
1701
1702 ctx->num_cs_dw_queries_suspend += query->num_cs_dw;
1703 }
1704
1705 void r600_query_end(struct r600_context *ctx, struct r600_query *query)
1706 {
1707 /* emit end query */
1708 switch (query->type) {
1709 case PIPE_QUERY_OCCLUSION_COUNTER:
1710 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1711 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1712 ctx->pm4[ctx->pm4_cdwords++] = query->results_end + 8;
1713 ctx->pm4[ctx->pm4_cdwords++] = 0;
1714 break;
1715 case PIPE_QUERY_TIME_ELAPSED:
1716 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1717 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1718 ctx->pm4[ctx->pm4_cdwords++] = query->results_end + query->result_size/2;
1719 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1720 ctx->pm4[ctx->pm4_cdwords++] = 0;
1721 ctx->pm4[ctx->pm4_cdwords++] = 0;
1722 break;
1723 default:
1724 assert(0);
1725 }
1726 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1727 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE);
1728
1729 query->results_end = (query->results_end + query->result_size) % query->buffer->b.b.b.width0;
1730 ctx->num_cs_dw_queries_suspend -= query->num_cs_dw;
1731 }
1732
1733 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
1734 int flag_wait)
1735 {
1736 if (operation == PREDICATION_OP_CLEAR) {
1737 r600_need_cs_space(ctx, 3, FALSE);
1738
1739 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
1740 ctx->pm4[ctx->pm4_cdwords++] = 0;
1741 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(PREDICATION_OP_CLEAR);
1742 } else {
1743 unsigned results_base = query->results_start;
1744 unsigned count;
1745 u32 op;
1746
1747 /* find count of the query data blocks */
1748 count = (query->buffer->b.b.b.width0 + query->results_end - query->results_start) % query->buffer->b.b.b.width0;
1749 count /= query->result_size;
1750
1751 r600_need_cs_space(ctx, 5 * count, TRUE);
1752
1753 op = PRED_OP(operation) | PREDICATION_DRAW_VISIBLE |
1754 (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW);
1755
1756 /* emit predicate packets for all data blocks */
1757 while (results_base != query->results_end) {
1758 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
1759 ctx->pm4[ctx->pm4_cdwords++] = results_base;
1760 ctx->pm4[ctx->pm4_cdwords++] = op;
1761 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1762 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, query->buffer,
1763 RADEON_USAGE_READ);
1764 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0;
1765
1766 /* set CONTINUE bit for all packets except the first */
1767 op |= PREDICATION_CONTINUE;
1768 }
1769 }
1770 }
1771
1772 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type)
1773 {
1774 struct r600_query *query;
1775 unsigned buffer_size = 4096;
1776
1777 query = CALLOC_STRUCT(r600_query);
1778 if (query == NULL)
1779 return NULL;
1780
1781 query->type = query_type;
1782
1783 switch (query_type) {
1784 case PIPE_QUERY_OCCLUSION_COUNTER:
1785 query->result_size = 16 * ctx->max_db;
1786 query->num_cs_dw = 6;
1787 break;
1788 case PIPE_QUERY_TIME_ELAPSED:
1789 query->result_size = 16;
1790 query->num_cs_dw = 8;
1791 break;
1792 default:
1793 assert(0);
1794 FREE(query);
1795 return NULL;
1796 }
1797
1798 /* adjust buffer size to simplify offsets wrapping math */
1799 buffer_size -= buffer_size % query->result_size;
1800
1801 /* Queries are normally read by the CPU after
1802 * being written by the gpu, hence staging is probably a good
1803 * usage pattern.
1804 */
1805 query->buffer = (struct r600_resource*)
1806 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING, buffer_size);
1807 if (!query->buffer) {
1808 FREE(query);
1809 return NULL;
1810 }
1811 return query;
1812 }
1813
1814 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
1815 {
1816 pipe_resource_reference((struct pipe_resource**)&query->buffer, NULL);
1817 free(query);
1818 }
1819
1820 boolean r600_context_query_result(struct r600_context *ctx,
1821 struct r600_query *query,
1822 boolean wait, void *vresult)
1823 {
1824 uint64_t *result = (uint64_t*)vresult;
1825
1826 if (!r600_query_result(ctx, query, wait))
1827 return FALSE;
1828
1829 switch (query->type) {
1830 case PIPE_QUERY_OCCLUSION_COUNTER:
1831 *result = query->result;
1832 break;
1833 case PIPE_QUERY_TIME_ELAPSED:
1834 *result = (1000000 * query->result) / ctx->screen->info.r600_clock_crystal_freq;
1835 break;
1836 default:
1837 assert(0);
1838 }
1839
1840 query->result = 0;
1841 return TRUE;
1842 }
1843
1844 void r600_context_queries_suspend(struct r600_context *ctx)
1845 {
1846 struct r600_query *query;
1847
1848 LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) {
1849 r600_query_end(ctx, query);
1850 }
1851 assert(ctx->num_cs_dw_queries_suspend == 0);
1852 }
1853
1854 void r600_context_queries_resume(struct r600_context *ctx)
1855 {
1856 struct r600_query *query;
1857
1858 assert(ctx->num_cs_dw_queries_suspend == 0);
1859
1860 LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) {
1861 r600_query_begin(ctx, query);
1862 }
1863 }