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r600g: merge r600_flush with r600_context_flush
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_pipe.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30 #include <unistd.h>
31
32
33 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
34 boolean count_draw_in)
35 {
36
37 if (!ctx->b.ws->cs_memory_below_limit(ctx->b.rings.gfx.cs, ctx->b.vram, ctx->b.gtt)) {
38 ctx->b.gtt = 0;
39 ctx->b.vram = 0;
40 ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
41 return;
42 }
43 /* all will be accounted once relocation are emited */
44 ctx->b.gtt = 0;
45 ctx->b.vram = 0;
46
47 /* The number of dwords we already used in the CS so far. */
48 num_dw += ctx->b.rings.gfx.cs->cdw;
49
50 if (count_draw_in) {
51 unsigned i;
52
53 /* The number of dwords all the dirty states would take. */
54 for (i = 0; i < R600_NUM_ATOMS; i++) {
55 if (ctx->atoms[i] && ctx->atoms[i]->dirty) {
56 num_dw += ctx->atoms[i]->num_dw;
57 if (ctx->screen->b.trace_bo) {
58 num_dw += R600_TRACE_CS_DWORDS;
59 }
60 }
61 }
62
63 /* The upper-bound of how much space a draw command would take. */
64 num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
65 if (ctx->screen->b.trace_bo) {
66 num_dw += R600_TRACE_CS_DWORDS;
67 }
68 }
69
70 /* Count in queries_suspend. */
71 num_dw += ctx->b.num_cs_dw_nontimer_queries_suspend;
72
73 /* Count in streamout_end at the end of CS. */
74 if (ctx->b.streamout.begin_emitted) {
75 num_dw += ctx->b.streamout.num_dw_for_end;
76 }
77
78 /* Count in render_condition(NULL) at the end of CS. */
79 if (ctx->b.predicate_drawing) {
80 num_dw += 3;
81 }
82
83 /* SX_MISC */
84 if (ctx->b.chip_class <= R700) {
85 num_dw += 3;
86 }
87
88 /* Count in framebuffer cache flushes at the end of CS. */
89 num_dw += R600_MAX_FLUSH_CS_DWORDS;
90
91 /* The fence at the end of CS. */
92 num_dw += 10;
93
94 /* Flush if there's not enough space. */
95 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
96 ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
97 }
98 }
99
100 void r600_flush_emit(struct r600_context *rctx)
101 {
102 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
103 unsigned cp_coher_cntl = 0;
104 unsigned wait_until = 0;
105
106 if (!rctx->b.flags) {
107 return;
108 }
109
110 if (rctx->b.flags & R600_CONTEXT_WAIT_3D_IDLE) {
111 wait_until |= S_008040_WAIT_3D_IDLE(1);
112 }
113 if (rctx->b.flags & R600_CONTEXT_WAIT_CP_DMA_IDLE) {
114 wait_until |= S_008040_WAIT_CP_DMA_IDLE(1);
115 }
116
117 if (wait_until) {
118 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
119 if (rctx->b.family >= CHIP_CAYMAN) {
120 /* emit a PS partial flush on Cayman/TN */
121 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
122 }
123 }
124
125 if (rctx->b.flags & R600_CONTEXT_PS_PARTIAL_FLUSH) {
126 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
127 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
128 }
129
130 if (rctx->b.chip_class >= R700 &&
131 (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
132 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
133 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0);
134 }
135
136 if (rctx->b.chip_class >= R700 &&
137 (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_DB_META)) {
138 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
139 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0);
140
141 /* Set FULL_CACHE_ENA for DB META flushes on r7xx and later.
142 *
143 * This hack predates use of FLUSH_AND_INV_DB_META, so it's
144 * unclear whether it's still needed or even whether it has
145 * any effect.
146 */
147 cp_coher_cntl |= S_0085F0_FULL_CACHE_ENA(1);
148 }
149
150 if (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV) {
151 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
152 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
153 }
154
155 if (rctx->b.flags & R600_CONTEXT_INV_CONST_CACHE) {
156 /* Direct constant addressing uses the shader cache.
157 * Indirect contant addressing uses the vertex cache. */
158 cp_coher_cntl |= S_0085F0_SH_ACTION_ENA(1) |
159 (rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1)
160 : S_0085F0_TC_ACTION_ENA(1));
161 }
162 if (rctx->b.flags & R600_CONTEXT_INV_VERTEX_CACHE) {
163 cp_coher_cntl |= rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1)
164 : S_0085F0_TC_ACTION_ENA(1);
165 }
166 if (rctx->b.flags & R600_CONTEXT_INV_TEX_CACHE) {
167 /* Textures use the texture cache.
168 * Texture buffer objects use the vertex cache. */
169 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
170 (rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1) : 0);
171 }
172
173 /* Don't use the DB CP COHER logic on r6xx.
174 * There are hw bugs.
175 */
176 if (rctx->b.chip_class >= R700 &&
177 (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_DB)) {
178 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
179 S_0085F0_DB_DEST_BASE_ENA(1) |
180 S_0085F0_SMX_ACTION_ENA(1);
181 }
182
183 /* Don't use the CB CP COHER logic on r6xx.
184 * There are hw bugs.
185 */
186 if (rctx->b.chip_class >= R700 &&
187 (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_CB)) {
188 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
189 S_0085F0_CB0_DEST_BASE_ENA(1) |
190 S_0085F0_CB1_DEST_BASE_ENA(1) |
191 S_0085F0_CB2_DEST_BASE_ENA(1) |
192 S_0085F0_CB3_DEST_BASE_ENA(1) |
193 S_0085F0_CB4_DEST_BASE_ENA(1) |
194 S_0085F0_CB5_DEST_BASE_ENA(1) |
195 S_0085F0_CB6_DEST_BASE_ENA(1) |
196 S_0085F0_CB7_DEST_BASE_ENA(1) |
197 S_0085F0_SMX_ACTION_ENA(1);
198 if (rctx->b.chip_class >= EVERGREEN)
199 cp_coher_cntl |= S_0085F0_CB8_DEST_BASE_ENA(1) |
200 S_0085F0_CB9_DEST_BASE_ENA(1) |
201 S_0085F0_CB10_DEST_BASE_ENA(1) |
202 S_0085F0_CB11_DEST_BASE_ENA(1);
203 }
204
205 if (rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH) {
206 cp_coher_cntl |= S_0085F0_SO0_DEST_BASE_ENA(1) |
207 S_0085F0_SO1_DEST_BASE_ENA(1) |
208 S_0085F0_SO2_DEST_BASE_ENA(1) |
209 S_0085F0_SO3_DEST_BASE_ENA(1) |
210 S_0085F0_SMX_ACTION_ENA(1);
211 }
212
213 if (cp_coher_cntl) {
214 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
215 cs->buf[cs->cdw++] = cp_coher_cntl; /* CP_COHER_CNTL */
216 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
217 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
218 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
219 }
220
221 if (wait_until) {
222 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
223 if (rctx->b.family < CHIP_CAYMAN) {
224 /* wait for things to settle */
225 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, wait_until);
226 }
227 }
228
229 /* everything is properly flushed */
230 rctx->b.flags = 0;
231 }
232
233 void r600_context_gfx_flush(void *context, unsigned flags,
234 struct pipe_fence_handle **fence)
235 {
236 struct r600_context *ctx = context;
237 struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
238
239 if (ctx->b.rings.gfx.cs->cdw == ctx->b.initial_gfx_cs_size)
240 return;
241
242 ctx->b.rings.gfx.flushing = true;
243
244 /* Disable render condition. */
245 ctx->b.saved_render_cond = NULL;
246 ctx->b.saved_render_cond_cond = FALSE;
247 ctx->b.saved_render_cond_mode = 0;
248 if (ctx->b.current_render_cond) {
249 ctx->b.saved_render_cond = ctx->b.current_render_cond;
250 ctx->b.saved_render_cond_cond = ctx->b.current_render_cond_cond;
251 ctx->b.saved_render_cond_mode = ctx->b.current_render_cond_mode;
252 ctx->b.b.render_condition(&ctx->b.b, NULL, FALSE, 0);
253 }
254
255 ctx->b.nontimer_queries_suspended = false;
256 ctx->b.streamout.suspended = false;
257
258 /* suspend queries */
259 if (ctx->b.num_cs_dw_nontimer_queries_suspend) {
260 r600_suspend_nontimer_queries(&ctx->b);
261 ctx->b.nontimer_queries_suspended = true;
262 }
263
264 if (ctx->b.streamout.begin_emitted) {
265 r600_emit_streamout_end(&ctx->b);
266 ctx->b.streamout.suspended = true;
267 }
268
269 /* flush the framebuffer cache */
270 ctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV |
271 R600_CONTEXT_FLUSH_AND_INV_CB |
272 R600_CONTEXT_FLUSH_AND_INV_DB |
273 R600_CONTEXT_FLUSH_AND_INV_CB_META |
274 R600_CONTEXT_FLUSH_AND_INV_DB_META |
275 R600_CONTEXT_WAIT_3D_IDLE |
276 R600_CONTEXT_WAIT_CP_DMA_IDLE;
277
278 r600_flush_emit(ctx);
279
280 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
281 if (ctx->b.chip_class <= R700) {
282 r600_write_context_reg(cs, R_028350_SX_MISC, 0);
283 }
284
285 /* force to keep tiling flags */
286 if (ctx->keep_tiling_flags) {
287 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
288 }
289
290 /* Flush the CS. */
291 ctx->b.ws->cs_flush(cs, flags, fence, ctx->screen->b.cs_count++);
292 ctx->b.rings.gfx.flushing = false;
293
294 r600_begin_new_cs(ctx);
295 }
296
297 void r600_begin_new_cs(struct r600_context *ctx)
298 {
299 unsigned shader;
300 int i;
301 ctx->b.flags = 0;
302 ctx->b.gtt = 0;
303 ctx->b.vram = 0;
304
305 /* Begin a new CS. */
306 r600_emit_command_buffer(ctx->b.rings.gfx.cs, &ctx->start_cs_cmd);
307
308 /* Re-emit states. */
309 ctx->alphatest_state.atom.dirty = true;
310 ctx->blend_color.atom.dirty = true;
311 ctx->cb_misc_state.atom.dirty = true;
312 ctx->clip_misc_state.atom.dirty = true;
313 ctx->clip_state.atom.dirty = true;
314 ctx->db_misc_state.atom.dirty = true;
315 ctx->db_state.atom.dirty = true;
316 ctx->framebuffer.atom.dirty = true;
317 ctx->pixel_shader.atom.dirty = true;
318 ctx->poly_offset_state.atom.dirty = true;
319 ctx->vgt_state.atom.dirty = true;
320 ctx->sample_mask.atom.dirty = true;
321 for (i = 0; i < 16; i++) {
322 ctx->scissor[i].atom.dirty = true;
323 ctx->viewport[i].atom.dirty = true;
324 }
325 ctx->config_state.atom.dirty = true;
326 ctx->stencil_ref.atom.dirty = true;
327 ctx->vertex_fetch_shader.atom.dirty = true;
328 ctx->export_shader.atom.dirty = true;
329 if (ctx->gs_shader) {
330 ctx->geometry_shader.atom.dirty = true;
331 ctx->shader_stages.atom.dirty = true;
332 ctx->gs_rings.atom.dirty = true;
333 }
334 ctx->vertex_shader.atom.dirty = true;
335 ctx->b.streamout.enable_atom.dirty = true;
336
337 if (ctx->blend_state.cso)
338 ctx->blend_state.atom.dirty = true;
339 if (ctx->dsa_state.cso)
340 ctx->dsa_state.atom.dirty = true;
341 if (ctx->rasterizer_state.cso)
342 ctx->rasterizer_state.atom.dirty = true;
343
344 if (ctx->b.chip_class <= R700) {
345 ctx->seamless_cube_map.atom.dirty = true;
346 }
347
348 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
349 r600_vertex_buffers_dirty(ctx);
350
351 /* Re-emit shader resources. */
352 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
353 struct r600_constbuf_state *constbuf = &ctx->constbuf_state[shader];
354 struct r600_textures_info *samplers = &ctx->samplers[shader];
355
356 constbuf->dirty_mask = constbuf->enabled_mask;
357 samplers->views.dirty_mask = samplers->views.enabled_mask;
358 samplers->states.dirty_mask = samplers->states.enabled_mask;
359
360 r600_constant_buffers_dirty(ctx, constbuf);
361 r600_sampler_views_dirty(ctx, &samplers->views);
362 r600_sampler_states_dirty(ctx, &samplers->states);
363 }
364
365 if (ctx->b.streamout.suspended) {
366 ctx->b.streamout.append_bitmask = ctx->b.streamout.enabled_mask;
367 r600_streamout_buffers_dirty(&ctx->b);
368 }
369
370 /* resume queries */
371 if (ctx->b.nontimer_queries_suspended) {
372 r600_resume_nontimer_queries(&ctx->b);
373 }
374
375 /* Re-enable render condition. */
376 if (ctx->b.saved_render_cond) {
377 ctx->b.b.render_condition(&ctx->b.b, ctx->b.saved_render_cond,
378 ctx->b.saved_render_cond_cond,
379 ctx->b.saved_render_cond_mode);
380 }
381
382 /* Re-emit the draw state. */
383 ctx->last_primitive_type = -1;
384 ctx->last_start_instance = -1;
385
386 ctx->b.initial_gfx_cs_size = ctx->b.rings.gfx.cs->cdw;
387 }
388
389 /* The max number of bytes to copy per packet. */
390 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
391
392 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
393 struct pipe_resource *dst, uint64_t dst_offset,
394 struct pipe_resource *src, uint64_t src_offset,
395 unsigned size)
396 {
397 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
398
399 assert(size);
400 assert(rctx->screen->b.has_cp_dma);
401
402 /* Mark the buffer range of destination as valid (initialized),
403 * so that transfer_map knows it should wait for the GPU when mapping
404 * that range. */
405 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
406 dst_offset + size);
407
408 dst_offset += r600_resource_va(&rctx->screen->b.b, dst);
409 src_offset += r600_resource_va(&rctx->screen->b.b, src);
410
411 /* Flush the caches where the resources are bound. */
412 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE |
413 R600_CONTEXT_INV_VERTEX_CACHE |
414 R600_CONTEXT_INV_TEX_CACHE |
415 R600_CONTEXT_FLUSH_AND_INV |
416 R600_CONTEXT_FLUSH_AND_INV_CB |
417 R600_CONTEXT_FLUSH_AND_INV_DB |
418 R600_CONTEXT_FLUSH_AND_INV_CB_META |
419 R600_CONTEXT_FLUSH_AND_INV_DB_META |
420 R600_CONTEXT_STREAMOUT_FLUSH |
421 R600_CONTEXT_WAIT_3D_IDLE;
422
423 /* There are differences between R700 and EG in CP DMA,
424 * but we only use the common bits here. */
425 while (size) {
426 unsigned sync = 0;
427 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
428 unsigned src_reloc, dst_reloc;
429
430 r600_need_cs_space(rctx, 10 + (rctx->b.flags ? R600_MAX_FLUSH_CS_DWORDS : 0), FALSE);
431
432 /* Flush the caches for the first copy only. */
433 if (rctx->b.flags) {
434 r600_flush_emit(rctx);
435 }
436
437 /* Do the synchronization after the last copy, so that all data is written to memory. */
438 if (size == byte_count) {
439 sync = PKT3_CP_DMA_CP_SYNC;
440 }
441
442 /* This must be done after r600_need_cs_space. */
443 src_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)src,
444 RADEON_USAGE_READ, RADEON_PRIO_MIN);
445 dst_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)dst,
446 RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
447
448 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
449 radeon_emit(cs, src_offset); /* SRC_ADDR_LO [31:0] */
450 radeon_emit(cs, sync | ((src_offset >> 32) & 0xff)); /* CP_SYNC [31] | SRC_ADDR_HI [7:0] */
451 radeon_emit(cs, dst_offset); /* DST_ADDR_LO [31:0] */
452 radeon_emit(cs, (dst_offset >> 32) & 0xff); /* DST_ADDR_HI [7:0] */
453 radeon_emit(cs, byte_count); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
454
455 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
456 radeon_emit(cs, src_reloc);
457 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
458 radeon_emit(cs, dst_reloc);
459
460 size -= byte_count;
461 src_offset += byte_count;
462 dst_offset += byte_count;
463 }
464
465 /* Invalidate the read caches. */
466 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE |
467 R600_CONTEXT_INV_VERTEX_CACHE |
468 R600_CONTEXT_INV_TEX_CACHE;
469 }
470
471 void r600_dma_copy_buffer(struct r600_context *rctx,
472 struct pipe_resource *dst,
473 struct pipe_resource *src,
474 uint64_t dst_offset,
475 uint64_t src_offset,
476 uint64_t size)
477 {
478 struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
479 unsigned i, ncopy, csize;
480 struct r600_resource *rdst = (struct r600_resource*)dst;
481 struct r600_resource *rsrc = (struct r600_resource*)src;
482
483 /* Mark the buffer range of destination as valid (initialized),
484 * so that transfer_map knows it should wait for the GPU when mapping
485 * that range. */
486 util_range_add(&rdst->valid_buffer_range, dst_offset,
487 dst_offset + size);
488
489 size >>= 2; /* convert to dwords */
490 ncopy = (size / R600_DMA_COPY_MAX_SIZE_DW) + !!(size % R600_DMA_COPY_MAX_SIZE_DW);
491
492 r600_need_dma_space(&rctx->b, ncopy * 5);
493 for (i = 0; i < ncopy; i++) {
494 csize = size < R600_DMA_COPY_MAX_SIZE_DW ? size : R600_DMA_COPY_MAX_SIZE_DW;
495 /* emit reloc before writting cs so that cs is always in consistent state */
496 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
497 RADEON_PRIO_MIN);
498 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
499 RADEON_PRIO_MIN);
500 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 0, 0, csize);
501 cs->buf[cs->cdw++] = dst_offset & 0xfffffffc;
502 cs->buf[cs->cdw++] = src_offset & 0xfffffffc;
503 cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xff;
504 cs->buf[cs->cdw++] = (src_offset >> 32UL) & 0xff;
505 dst_offset += csize << 2;
506 src_offset += csize << 2;
507 size -= csize;
508 }
509 }