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r600g: add cs memory usage accounting and limit it v3
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_hw_context_priv.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30 #include <unistd.h>
31
32 /* Get backends mask */
33 void r600_get_backend_mask(struct r600_context *ctx)
34 {
35 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
36 struct r600_resource *buffer;
37 uint32_t *results;
38 unsigned num_backends = ctx->screen->info.r600_num_backends;
39 unsigned i, mask = 0;
40 uint64_t va;
41
42 /* if backend_map query is supported by the kernel */
43 if (ctx->screen->info.r600_backend_map_valid) {
44 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
45 unsigned backend_map = ctx->screen->info.r600_backend_map;
46 unsigned item_width, item_mask;
47
48 if (ctx->chip_class >= EVERGREEN) {
49 item_width = 4;
50 item_mask = 0x7;
51 } else {
52 item_width = 2;
53 item_mask = 0x3;
54 }
55
56 while(num_tile_pipes--) {
57 i = backend_map & item_mask;
58 mask |= (1<<i);
59 backend_map >>= item_width;
60 }
61 if (mask != 0) {
62 ctx->backend_mask = mask;
63 return;
64 }
65 }
66
67 /* otherwise backup path for older kernels */
68
69 /* create buffer for event data */
70 buffer = (struct r600_resource*)
71 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
72 PIPE_USAGE_STAGING, ctx->max_db*16);
73 if (!buffer)
74 goto err;
75 va = r600_resource_va(&ctx->screen->screen, (void*)buffer);
76
77 /* initialize buffer with zeroes */
78 results = r600_buffer_mmap_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
79 if (results) {
80 memset(results, 0, ctx->max_db * 4 * 4);
81 ctx->ws->buffer_unmap(buffer->cs_buf);
82
83 /* emit EVENT_WRITE for ZPASS_DONE */
84 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
85 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
86 cs->buf[cs->cdw++] = va;
87 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
88
89 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
90 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, &ctx->rings.gfx, buffer, RADEON_USAGE_WRITE);
91
92 /* analyze results */
93 results = r600_buffer_mmap_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
94 if (results) {
95 for(i = 0; i < ctx->max_db; i++) {
96 /* at least highest bit will be set if backend is used */
97 if (results[i*4 + 1])
98 mask |= (1<<i);
99 }
100 ctx->ws->buffer_unmap(buffer->cs_buf);
101 }
102 }
103
104 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
105
106 if (mask != 0) {
107 ctx->backend_mask = mask;
108 return;
109 }
110
111 err:
112 /* fallback to old method - set num_backends lower bits to 1 */
113 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
114 return;
115 }
116
117 static void r600_init_block(struct r600_context *ctx,
118 struct r600_block *block,
119 const struct r600_reg *reg, int index, int nreg,
120 unsigned opcode, unsigned offset_base)
121 {
122 int i = index;
123 int j, n = nreg;
124
125 /* initialize block */
126 block->flags = 0;
127 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
128 block->start_offset = reg[i].offset;
129 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
130 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
131 block->reg = &block->pm4[block->pm4_ndwords];
132 block->pm4_ndwords += n;
133 block->nreg = n;
134 block->nreg_dirty = n;
135 LIST_INITHEAD(&block->list);
136 LIST_INITHEAD(&block->enable_list);
137
138 for (j = 0; j < n; j++) {
139 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
140 block->flags |= REG_FLAG_DIRTY_ALWAYS;
141 }
142 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
143 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
144 block->status |= R600_BLOCK_STATUS_ENABLED;
145 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
146 LIST_ADDTAIL(&block->list,&ctx->dirty);
147 }
148 }
149 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
150 block->flags |= REG_FLAG_FLUSH_CHANGE;
151 }
152
153 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
154 block->nbo++;
155 assert(block->nbo < R600_BLOCK_MAX_BO);
156 block->pm4_bo_index[j] = block->nbo;
157 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
158 block->pm4[block->pm4_ndwords++] = 0x00000000;
159 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
160 }
161 }
162 /* check that we stay in limit */
163 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
164 }
165
166 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
167 unsigned opcode, unsigned offset_base)
168 {
169 struct r600_block *block;
170 struct r600_range *range;
171 int offset;
172
173 for (unsigned i = 0, n = 0; i < nreg; i += n) {
174 /* ignore new block balise */
175 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
176 n = 1;
177 continue;
178 }
179
180 /* register that need relocation are in their own group */
181 /* find number of consecutive registers */
182 n = 0;
183 offset = reg[i].offset;
184 while (reg[i + n].offset == offset) {
185 n++;
186 offset += 4;
187 if ((n + i) >= nreg)
188 break;
189 if (n >= (R600_BLOCK_MAX_REG - 2))
190 break;
191 }
192
193 /* allocate new block */
194 block = calloc(1, sizeof(struct r600_block));
195 if (block == NULL) {
196 return -ENOMEM;
197 }
198 ctx->nblocks++;
199 for (int j = 0; j < n; j++) {
200 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
201 /* create block table if it doesn't exist */
202 if (!range->blocks)
203 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
204 if (!range->blocks)
205 return -1;
206
207 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
208 }
209
210 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
211
212 }
213 return 0;
214 }
215
216 static const struct r600_reg r600_context_reg_list[] = {
217 {R_028D24_DB_HTILE_SURFACE, 0, 0},
218 {R_028614_SPI_VS_OUT_ID_0, 0, 0},
219 {R_028618_SPI_VS_OUT_ID_1, 0, 0},
220 {R_02861C_SPI_VS_OUT_ID_2, 0, 0},
221 {R_028620_SPI_VS_OUT_ID_3, 0, 0},
222 {R_028624_SPI_VS_OUT_ID_4, 0, 0},
223 {R_028628_SPI_VS_OUT_ID_5, 0, 0},
224 {R_02862C_SPI_VS_OUT_ID_6, 0, 0},
225 {R_028630_SPI_VS_OUT_ID_7, 0, 0},
226 {R_028634_SPI_VS_OUT_ID_8, 0, 0},
227 {R_028638_SPI_VS_OUT_ID_9, 0, 0},
228 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
229 {GROUP_FORCE_NEW_BLOCK, 0, 0},
230 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
231 {GROUP_FORCE_NEW_BLOCK, 0, 0},
232 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0},
233 {GROUP_FORCE_NEW_BLOCK, 0, 0},
234 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0},
235 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0},
236 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
237 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
238 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
239 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
240 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
241 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
242 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
243 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
244 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
245 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
246 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
247 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
248 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
249 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
250 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
251 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
252 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
253 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
254 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
255 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
256 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
257 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
258 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
259 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
260 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
261 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
262 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
263 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
264 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
265 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
266 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
267 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
268 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
269 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
270 {R_0286D8_SPI_INPUT_Z, 0, 0},
271 {GROUP_FORCE_NEW_BLOCK, 0, 0},
272 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
273 {GROUP_FORCE_NEW_BLOCK, 0, 0},
274 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
275 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
276 };
277
278 /* initialize */
279 void r600_context_fini(struct r600_context *ctx)
280 {
281 struct r600_block *block;
282 struct r600_range *range;
283
284 if (ctx->range) {
285 for (int i = 0; i < NUM_RANGES; i++) {
286 if (!ctx->range[i].blocks)
287 continue;
288 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
289 block = ctx->range[i].blocks[j];
290 if (block) {
291 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
292 range = &ctx->range[CTX_RANGE_ID(offset)];
293 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
294 }
295 for (int k = 1; k <= block->nbo; k++) {
296 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
297 }
298 free(block);
299 }
300 }
301 free(ctx->range[i].blocks);
302 }
303 }
304 free(ctx->blocks);
305 }
306
307 int r600_setup_block_table(struct r600_context *ctx)
308 {
309 /* setup block table */
310 int c = 0;
311 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
312 if (!ctx->blocks)
313 return -ENOMEM;
314 for (int i = 0; i < NUM_RANGES; i++) {
315 if (!ctx->range[i].blocks)
316 continue;
317 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
318 if (!ctx->range[i].blocks[j])
319 continue;
320
321 add = 1;
322 for (int k = 0; k < c; k++) {
323 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
324 add = 0;
325 break;
326 }
327 }
328 if (add) {
329 assert(c < ctx->nblocks);
330 ctx->blocks[c++] = ctx->range[i].blocks[j];
331 j += (ctx->range[i].blocks[j]->nreg) - 1;
332 }
333 }
334 }
335 return 0;
336 }
337
338 int r600_context_init(struct r600_context *ctx)
339 {
340 int r;
341
342 /* add blocks */
343 r = r600_context_add_block(ctx, r600_context_reg_list,
344 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
345 if (r)
346 goto out_err;
347
348 r = r600_setup_block_table(ctx);
349 if (r)
350 goto out_err;
351
352 ctx->max_db = 4;
353 return 0;
354 out_err:
355 r600_context_fini(ctx);
356 return r;
357 }
358
359 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
360 boolean count_draw_in)
361 {
362 if (!ctx->ws->cs_memory_below_limit(ctx->rings.gfx.cs, ctx->vram, ctx->gtt)) {
363 ctx->gtt = 0;
364 ctx->vram = 0;
365 ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
366 return;
367 }
368 /* all will be accounted once relocation are emited */
369 ctx->gtt = 0;
370 ctx->vram = 0;
371
372 /* The number of dwords we already used in the CS so far. */
373 num_dw += ctx->rings.gfx.cs->cdw;
374
375 if (count_draw_in) {
376 unsigned i;
377
378 /* The number of dwords all the dirty states would take. */
379 for (i = 0; i < R600_NUM_ATOMS; i++) {
380 if (ctx->atoms[i] && ctx->atoms[i]->dirty) {
381 num_dw += ctx->atoms[i]->num_dw;
382 #if R600_TRACE_CS
383 if (ctx->screen->trace_bo) {
384 num_dw += R600_TRACE_CS_DWORDS;
385 }
386 #endif
387 }
388 }
389
390 num_dw += ctx->pm4_dirty_cdwords;
391
392 /* The upper-bound of how much space a draw command would take. */
393 num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
394 #if R600_TRACE_CS
395 if (ctx->screen->trace_bo) {
396 num_dw += R600_TRACE_CS_DWORDS;
397 }
398 #endif
399 }
400
401 /* Count in queries_suspend. */
402 num_dw += ctx->num_cs_dw_nontimer_queries_suspend;
403
404 /* Count in streamout_end at the end of CS. */
405 num_dw += ctx->num_cs_dw_streamout_end;
406
407 /* Count in render_condition(NULL) at the end of CS. */
408 if (ctx->predicate_drawing) {
409 num_dw += 3;
410 }
411
412 /* SX_MISC */
413 if (ctx->chip_class <= R700) {
414 num_dw += 3;
415 }
416
417 /* Count in framebuffer cache flushes at the end of CS. */
418 num_dw += R600_MAX_FLUSH_CS_DWORDS;
419
420 /* The fence at the end of CS. */
421 num_dw += 10;
422
423 /* Flush if there's not enough space. */
424 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
425 ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
426 }
427 }
428
429 void r600_context_dirty_block(struct r600_context *ctx,
430 struct r600_block *block,
431 int dirty, int index)
432 {
433 if ((index + 1) > block->nreg_dirty)
434 block->nreg_dirty = index + 1;
435
436 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
437 block->status |= R600_BLOCK_STATUS_DIRTY;
438 ctx->pm4_dirty_cdwords += block->pm4_ndwords;
439 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
440 block->status |= R600_BLOCK_STATUS_ENABLED;
441 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
442 }
443 LIST_ADDTAIL(&block->list,&ctx->dirty);
444
445 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
446 ctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
447 }
448 }
449 }
450
451 /**
452 * If reg needs a reloc, this function will add it to its block's reloc list.
453 * @return true if reg needs a reloc, false otherwise
454 */
455 static bool r600_reg_set_block_reloc(struct r600_pipe_reg *reg)
456 {
457 unsigned reloc_id;
458
459 if (!reg->block->pm4_bo_index[reg->id]) {
460 return false;
461 }
462 /* find relocation */
463 reloc_id = reg->block->pm4_bo_index[reg->id];
464 pipe_resource_reference(
465 (struct pipe_resource**)&reg->block->reloc[reloc_id].bo,
466 &reg->bo->b.b);
467 reg->block->reloc[reloc_id].bo_usage = reg->bo_usage;
468 return true;
469 }
470
471 /**
472 * This function will emit all the registers in state directly to the command
473 * stream allowing you to bypass the r600_context dirty list.
474 *
475 * This is used for dispatching compute shaders to avoid mixing compute and
476 * 3D states in the context's dirty list.
477 *
478 * @param pkt_flags Should be either 0 or RADEON_CP_PACKET3_COMPUTE_MODE. This
479 * value will be passed on to r600_context_block_emit_dirty an or'd against
480 * the PKT3 headers.
481 */
482 void r600_context_pipe_state_emit(struct r600_context *ctx,
483 struct r600_pipe_state *state,
484 unsigned pkt_flags)
485 {
486 unsigned i;
487
488 /* Mark all blocks as dirty:
489 * Since two registers can be in the same block, we need to make sure
490 * we mark all the blocks dirty before we emit any of them. If we were
491 * to mark blocks dirty and emit them in the same loop, like this:
492 *
493 * foreach (reg in state->regs) {
494 * mark_dirty(reg->block)
495 * emit_block(reg->block)
496 * }
497 *
498 * Then if we have two registers in this state that are in the same
499 * block, we would end up emitting that block twice.
500 */
501 for (i = 0; i < state->nregs; i++) {
502 struct r600_pipe_reg *reg = &state->regs[i];
503 /* Mark all the registers in the block as dirty */
504 reg->block->nreg_dirty = reg->block->nreg;
505 reg->block->status |= R600_BLOCK_STATUS_DIRTY;
506 /* Update the reloc for this register if necessary. */
507 r600_reg_set_block_reloc(reg);
508 }
509
510 /* Emit the registers writes */
511 for (i = 0; i < state->nregs; i++) {
512 struct r600_pipe_reg *reg = &state->regs[i];
513 if (reg->block->status & R600_BLOCK_STATUS_DIRTY) {
514 r600_context_block_emit_dirty(ctx, reg->block, pkt_flags);
515 }
516 }
517 }
518
519 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
520 {
521 struct r600_block *block;
522 int dirty;
523 for (int i = 0; i < state->nregs; i++) {
524 unsigned id;
525 struct r600_pipe_reg *reg = &state->regs[i];
526
527 block = reg->block;
528 id = reg->id;
529
530 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
531
532 if (reg->value != block->reg[id]) {
533 block->reg[id] = reg->value;
534 dirty |= R600_BLOCK_STATUS_DIRTY;
535 }
536 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
537 dirty |= R600_BLOCK_STATUS_DIRTY;
538 if (r600_reg_set_block_reloc(reg)) {
539 /* always force dirty for relocs for now */
540 dirty |= R600_BLOCK_STATUS_DIRTY;
541 }
542
543 if (dirty)
544 r600_context_dirty_block(ctx, block, dirty, id);
545 }
546 }
547
548 /**
549 * @param pkt_flags should be set to RADEON_CP_PACKET3_COMPUTE_MODE if this
550 * block will be used for compute shaders.
551 */
552 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block,
553 unsigned pkt_flags)
554 {
555 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
556 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
557 int cp_dwords = block->pm4_ndwords, start_dword = 0;
558 int new_dwords = 0;
559 int nbo = block->nbo;
560
561 if (block->nreg_dirty == 0 && optional) {
562 goto out;
563 }
564
565 if (nbo) {
566 for (int j = 0; j < block->nreg; j++) {
567 if (block->pm4_bo_index[j]) {
568 /* find relocation */
569 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
570 if (reloc->bo) {
571 block->pm4[reloc->bo_pm4_index] =
572 r600_context_bo_reloc(ctx, &ctx->rings.gfx, reloc->bo, reloc->bo_usage);
573 } else {
574 block->pm4[reloc->bo_pm4_index] = 0;
575 }
576 nbo--;
577 if (nbo == 0)
578 break;
579
580 }
581 }
582 }
583
584 optional &= (block->nreg_dirty != block->nreg);
585 if (optional) {
586 new_dwords = block->nreg_dirty;
587 start_dword = cs->cdw;
588 cp_dwords = new_dwords + 2;
589 }
590 memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4);
591
592 /* We are applying the pkt_flags after copying the register block to
593 * the the command stream, because it is possible this block will be
594 * emitted with a different pkt_flags, and we don't want to store the
595 * pkt_flags in the block.
596 */
597 cs->buf[cs->cdw] |= pkt_flags;
598 cs->cdw += cp_dwords;
599
600 if (optional) {
601 uint32_t newword;
602
603 newword = cs->buf[start_dword];
604 newword &= PKT_COUNT_C;
605 newword |= PKT_COUNT_S(new_dwords);
606 cs->buf[start_dword] = newword;
607 }
608 out:
609 block->status ^= R600_BLOCK_STATUS_DIRTY;
610 block->nreg_dirty = 0;
611 LIST_DELINIT(&block->list);
612 }
613
614 void r600_flush_emit(struct r600_context *rctx)
615 {
616 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
617 unsigned cp_coher_cntl = 0;
618 unsigned wait_until = 0;
619 unsigned emit_flush = 0;
620
621 if (!rctx->flags) {
622 return;
623 }
624
625 if (rctx->flags & R600_CONTEXT_WAIT_3D_IDLE) {
626 wait_until |= S_008040_WAIT_3D_IDLE(1);
627 }
628 if (rctx->flags & R600_CONTEXT_WAIT_CP_DMA_IDLE) {
629 wait_until |= S_008040_WAIT_CP_DMA_IDLE(1);
630 }
631
632 if (wait_until) {
633 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
634 if (rctx->family >= CHIP_CAYMAN) {
635 /* emit a PS partial flush on Cayman/TN */
636 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
637 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
638 }
639 }
640
641 if (rctx->chip_class >= R700 &&
642 (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
643 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
644 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0);
645 }
646
647 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) {
648 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
649 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
650 if (rctx->chip_class >= EVERGREEN) {
651 cp_coher_cntl = S_0085F0_CB0_DEST_BASE_ENA(1) |
652 S_0085F0_CB1_DEST_BASE_ENA(1) |
653 S_0085F0_CB2_DEST_BASE_ENA(1) |
654 S_0085F0_CB3_DEST_BASE_ENA(1) |
655 S_0085F0_CB4_DEST_BASE_ENA(1) |
656 S_0085F0_CB5_DEST_BASE_ENA(1) |
657 S_0085F0_CB6_DEST_BASE_ENA(1) |
658 S_0085F0_CB7_DEST_BASE_ENA(1) |
659 S_0085F0_CB8_DEST_BASE_ENA(1) |
660 S_0085F0_CB9_DEST_BASE_ENA(1) |
661 S_0085F0_CB10_DEST_BASE_ENA(1) |
662 S_0085F0_CB11_DEST_BASE_ENA(1) |
663 S_0085F0_DB_DEST_BASE_ENA(1) |
664 S_0085F0_TC_ACTION_ENA(1) |
665 S_0085F0_CB_ACTION_ENA(1) |
666 S_0085F0_DB_ACTION_ENA(1) |
667 S_0085F0_SH_ACTION_ENA(1) |
668 S_0085F0_SMX_ACTION_ENA(1) |
669 S_0085F0_FULL_CACHE_ENA(1);
670 } else {
671 cp_coher_cntl = S_0085F0_SMX_ACTION_ENA(1) |
672 S_0085F0_SH_ACTION_ENA(1) |
673 S_0085F0_VC_ACTION_ENA(1) |
674 S_0085F0_TC_ACTION_ENA(1) |
675 S_0085F0_FULL_CACHE_ENA(1);
676 }
677 }
678
679 if (rctx->flags & R600_CONTEXT_INVAL_READ_CACHES) {
680 cp_coher_cntl |= S_0085F0_VC_ACTION_ENA(1) |
681 S_0085F0_TC_ACTION_ENA(1) |
682 S_0085F0_FULL_CACHE_ENA(1);
683 emit_flush = 1;
684 }
685
686 if (rctx->family >= CHIP_RV770 && rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
687 cp_coher_cntl |= S_0085F0_SO0_DEST_BASE_ENA(1) |
688 S_0085F0_SO1_DEST_BASE_ENA(1) |
689 S_0085F0_SO2_DEST_BASE_ENA(1) |
690 S_0085F0_SO3_DEST_BASE_ENA(1) |
691 S_0085F0_SMX_ACTION_ENA(1);
692 emit_flush = 1;
693 }
694
695 if (emit_flush) {
696 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
697 cs->buf[cs->cdw++] = cp_coher_cntl; /* CP_COHER_CNTL */
698 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
699 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
700 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
701 }
702
703 if (wait_until) {
704 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
705 if (rctx->family < CHIP_CAYMAN) {
706 /* wait for things to settle */
707 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, wait_until);
708 }
709 }
710
711 /* everything is properly flushed */
712 rctx->flags = 0;
713 }
714
715 void r600_context_flush(struct r600_context *ctx, unsigned flags)
716 {
717 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
718
719 if (cs->cdw == ctx->start_cs_cmd.num_dw)
720 return;
721
722 ctx->nontimer_queries_suspended = false;
723 ctx->streamout_suspended = false;
724
725 /* suspend queries */
726 if (ctx->num_cs_dw_nontimer_queries_suspend) {
727 r600_suspend_nontimer_queries(ctx);
728 ctx->nontimer_queries_suspended = true;
729 }
730
731 if (ctx->num_cs_dw_streamout_end) {
732 r600_context_streamout_end(ctx);
733 ctx->streamout_suspended = true;
734 }
735
736 /* flush is needed to avoid lockups on some chips with user fences
737 * this will also flush the framebuffer cache
738 */
739 ctx->flags |= R600_CONTEXT_FLUSH_AND_INV |
740 R600_CONTEXT_FLUSH_AND_INV_CB_META |
741 R600_CONTEXT_WAIT_3D_IDLE |
742 R600_CONTEXT_WAIT_CP_DMA_IDLE;
743
744 r600_flush_emit(ctx);
745
746 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
747 if (ctx->chip_class <= R700) {
748 r600_write_context_reg(cs, R_028350_SX_MISC, 0);
749 }
750
751 /* force to keep tiling flags */
752 if (ctx->keep_tiling_flags) {
753 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
754 }
755
756 /* Flush the CS. */
757 #if R600_TRACE_CS
758 if (ctx->screen->trace_bo) {
759 struct r600_screen *rscreen = ctx->screen;
760 unsigned i;
761
762 for (i = 0; i < cs->cdw; i++) {
763 fprintf(stderr, "[%4d] [%5d] 0x%08x\n", rscreen->cs_count, i, cs->buf[i]);
764 }
765 rscreen->cs_count++;
766 }
767 #endif
768 ctx->ws->cs_flush(ctx->rings.gfx.cs, flags);
769 #if R600_TRACE_CS
770 if (ctx->screen->trace_bo) {
771 struct r600_screen *rscreen = ctx->screen;
772 unsigned i;
773
774 for (i = 0; i < 10; i++) {
775 usleep(5);
776 if (!ctx->ws->buffer_is_busy(rscreen->trace_bo->buf, RADEON_USAGE_READWRITE)) {
777 break;
778 }
779 }
780 if (i == 10) {
781 fprintf(stderr, "timeout on cs lockup likely happen at cs %d dw %d\n",
782 rscreen->trace_ptr[1], rscreen->trace_ptr[0]);
783 } else {
784 fprintf(stderr, "cs %d executed in %dms\n", rscreen->trace_ptr[1], i * 5);
785 }
786 }
787 #endif
788 }
789
790 void r600_begin_new_cs(struct r600_context *ctx)
791 {
792 struct r600_block *enable_block = NULL;
793 unsigned shader;
794
795 ctx->pm4_dirty_cdwords = 0;
796 ctx->flags = 0;
797 ctx->gtt = 0;
798 ctx->vram = 0;
799
800 /* Begin a new CS. */
801 r600_emit_command_buffer(ctx->rings.gfx.cs, &ctx->start_cs_cmd);
802
803 /* Re-emit states. */
804 ctx->alphatest_state.atom.dirty = true;
805 ctx->blend_color.atom.dirty = true;
806 ctx->cb_misc_state.atom.dirty = true;
807 ctx->clip_misc_state.atom.dirty = true;
808 ctx->clip_state.atom.dirty = true;
809 ctx->db_misc_state.atom.dirty = true;
810 ctx->db_state.atom.dirty = true;
811 ctx->framebuffer.atom.dirty = true;
812 ctx->poly_offset_state.atom.dirty = true;
813 ctx->vgt_state.atom.dirty = true;
814 ctx->vgt2_state.atom.dirty = true;
815 ctx->sample_mask.atom.dirty = true;
816 ctx->scissor.atom.dirty = true;
817 ctx->config_state.atom.dirty = true;
818 ctx->stencil_ref.atom.dirty = true;
819 ctx->vertex_fetch_shader.atom.dirty = true;
820 ctx->viewport.atom.dirty = true;
821
822 if (ctx->blend_state.cso)
823 ctx->blend_state.atom.dirty = true;
824 if (ctx->dsa_state.cso)
825 ctx->dsa_state.atom.dirty = true;
826 if (ctx->rasterizer_state.cso)
827 ctx->rasterizer_state.atom.dirty = true;
828
829 if (ctx->chip_class <= R700) {
830 ctx->seamless_cube_map.atom.dirty = true;
831 }
832
833 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
834 r600_vertex_buffers_dirty(ctx);
835
836 /* Re-emit shader resources. */
837 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
838 struct r600_constbuf_state *constbuf = &ctx->constbuf_state[shader];
839 struct r600_textures_info *samplers = &ctx->samplers[shader];
840
841 constbuf->dirty_mask = constbuf->enabled_mask;
842 samplers->views.dirty_mask = samplers->views.enabled_mask;
843 samplers->states.dirty_mask = samplers->states.enabled_mask;
844
845 r600_constant_buffers_dirty(ctx, constbuf);
846 r600_sampler_views_dirty(ctx, &samplers->views);
847 r600_sampler_states_dirty(ctx, &samplers->states);
848 }
849
850 if (ctx->streamout_suspended) {
851 ctx->streamout_start = TRUE;
852 ctx->streamout_append_bitmask = ~0;
853 }
854
855 /* resume queries */
856 if (ctx->nontimer_queries_suspended) {
857 r600_resume_nontimer_queries(ctx);
858 }
859
860 /* set all valid group as dirty so they get reemited on
861 * next draw command
862 */
863 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
864 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
865 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
866 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
867 }
868 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
869 enable_block->nreg_dirty = enable_block->nreg;
870 }
871
872 /* Re-emit the draw state. */
873 ctx->last_primitive_type = -1;
874 ctx->last_start_instance = -1;
875 }
876
877 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
878 {
879 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
880 uint64_t va;
881
882 r600_need_cs_space(ctx, 10, FALSE);
883
884 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
885 va = va + (offset << 2);
886
887 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
888 if (ctx->family >= CHIP_CAYMAN) {
889 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
890 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
891 } else {
892 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
893 }
894
895 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
896 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
897 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */
898 /* DATA_SEL | INT_EN | ADDRESS_HI */
899 cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF);
900 cs->buf[cs->cdw++] = value; /* DATA_LO */
901 cs->buf[cs->cdw++] = 0; /* DATA_HI */
902 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
903 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, &ctx->rings.gfx, fence_bo, RADEON_USAGE_WRITE);
904 }
905
906 static void r600_flush_vgt_streamout(struct r600_context *ctx)
907 {
908 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
909
910 r600_write_config_reg(cs, R_008490_CP_STRMOUT_CNTL, 0);
911
912 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
913 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
914
915 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
916 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
917 cs->buf[cs->cdw++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */
918 cs->buf[cs->cdw++] = 0;
919 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */
920 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */
921 cs->buf[cs->cdw++] = 4; /* poll interval */
922 }
923
924 static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
925 {
926 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
927
928 if (buffer_enable_bit) {
929 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(1));
930 r600_write_context_reg(cs, R_028B20_VGT_STRMOUT_BUFFER_EN, buffer_enable_bit);
931 } else {
932 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(0));
933 }
934 }
935
936 void r600_context_streamout_begin(struct r600_context *ctx)
937 {
938 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
939 struct r600_so_target **t = ctx->so_targets;
940 unsigned *stride_in_dw = ctx->vs_shader->so.stride;
941 unsigned buffer_en, i, update_flags = 0;
942 uint64_t va;
943 unsigned num_cs_dw_streamout_end;
944
945 buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) |
946 (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) |
947 (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) |
948 (ctx->num_so_targets >= 4 && t[3] ? 8 : 0);
949
950 num_cs_dw_streamout_end =
951 12 + /* flush_vgt_streamout */
952 util_bitcount(buffer_en) * 8 + /* STRMOUT_BUFFER_UPDATE */
953 3 /* set_streamout_enable(0) */;
954
955 r600_need_cs_space(ctx,
956 12 + /* flush_vgt_streamout */
957 6 + /* set_streamout_enable */
958 util_bitcount(buffer_en) * 7 + /* SET_CONTEXT_REG */
959 (ctx->family >= CHIP_RS780 &&
960 ctx->family <= CHIP_RV740 ? util_bitcount(buffer_en) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
961 util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 + /* STRMOUT_BUFFER_UPDATE */
962 util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 + /* STRMOUT_BUFFER_UPDATE */
963 (ctx->family > CHIP_R600 && ctx->family < CHIP_RS780 ? 2 : 0) + /* SURFACE_BASE_UPDATE */
964 num_cs_dw_streamout_end, TRUE);
965
966 /* This must be set after r600_need_cs_space. */
967 ctx->num_cs_dw_streamout_end = num_cs_dw_streamout_end;
968
969 if (ctx->chip_class >= EVERGREEN) {
970 evergreen_flush_vgt_streamout(ctx);
971 evergreen_set_streamout_enable(ctx, buffer_en);
972 } else {
973 r600_flush_vgt_streamout(ctx);
974 r600_set_streamout_enable(ctx, buffer_en);
975 }
976
977 for (i = 0; i < ctx->num_so_targets; i++) {
978 if (t[i]) {
979 t[i]->stride_in_dw = stride_in_dw[i];
980 t[i]->so_index = i;
981 va = r600_resource_va(&ctx->screen->screen,
982 (void*)t[i]->b.buffer);
983
984 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
985
986 r600_write_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
987 r600_write_value(cs, (t[i]->b.buffer_offset +
988 t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
989 r600_write_value(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
990 r600_write_value(cs, va >> 8); /* BUFFER_BASE */
991
992 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
993 cs->buf[cs->cdw++] =
994 r600_context_bo_reloc(ctx, &ctx->rings.gfx, r600_resource(t[i]->b.buffer),
995 RADEON_USAGE_WRITE);
996
997 /* R7xx requires this packet after updating BUFFER_BASE.
998 * Without this, R7xx locks up. */
999 if (ctx->family >= CHIP_RS780 && ctx->family <= CHIP_RV740) {
1000 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0);
1001 cs->buf[cs->cdw++] = i;
1002 cs->buf[cs->cdw++] = va >> 8;
1003
1004 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1005 cs->buf[cs->cdw++] =
1006 r600_context_bo_reloc(ctx, &ctx->rings.gfx, r600_resource(t[i]->b.buffer),
1007 RADEON_USAGE_WRITE);
1008 }
1009
1010 if (ctx->streamout_append_bitmask & (1 << i)) {
1011 va = r600_resource_va(&ctx->screen->screen,
1012 (void*)t[i]->buf_filled_size) + t[i]->buf_filled_size_offset;
1013 /* Append. */
1014 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1015 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1016 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
1017 cs->buf[cs->cdw++] = 0; /* unused */
1018 cs->buf[cs->cdw++] = 0; /* unused */
1019 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1020 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1021
1022 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1023 cs->buf[cs->cdw++] =
1024 r600_context_bo_reloc(ctx, &ctx->rings.gfx, t[i]->buf_filled_size,
1025 RADEON_USAGE_READ);
1026 } else {
1027 /* Start from the beginning. */
1028 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1029 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1030 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
1031 cs->buf[cs->cdw++] = 0; /* unused */
1032 cs->buf[cs->cdw++] = 0; /* unused */
1033 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
1034 cs->buf[cs->cdw++] = 0; /* unused */
1035 }
1036 }
1037 }
1038
1039 if (ctx->family > CHIP_R600 && ctx->family < CHIP_RS780) {
1040 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
1041 cs->buf[cs->cdw++] = update_flags;
1042 }
1043 }
1044
1045 void r600_context_streamout_end(struct r600_context *ctx)
1046 {
1047 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
1048 struct r600_so_target **t = ctx->so_targets;
1049 unsigned i;
1050 uint64_t va;
1051
1052 if (ctx->chip_class >= EVERGREEN) {
1053 evergreen_flush_vgt_streamout(ctx);
1054 } else {
1055 r600_flush_vgt_streamout(ctx);
1056 }
1057
1058 for (i = 0; i < ctx->num_so_targets; i++) {
1059 if (t[i]) {
1060 va = r600_resource_va(&ctx->screen->screen,
1061 (void*)t[i]->buf_filled_size) + t[i]->buf_filled_size_offset;
1062 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1063 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1064 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
1065 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
1066 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* dst address lo */
1067 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* dst address hi */
1068 cs->buf[cs->cdw++] = 0; /* unused */
1069 cs->buf[cs->cdw++] = 0; /* unused */
1070
1071 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1072 cs->buf[cs->cdw++] =
1073 r600_context_bo_reloc(ctx, &ctx->rings.gfx, t[i]->buf_filled_size,
1074 RADEON_USAGE_WRITE);
1075
1076 }
1077 }
1078
1079 if (ctx->chip_class >= EVERGREEN) {
1080 ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
1081 evergreen_set_streamout_enable(ctx, 0);
1082 } else {
1083 if (ctx->chip_class >= R700) {
1084 ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
1085 }
1086 r600_set_streamout_enable(ctx, 0);
1087 }
1088 ctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1089 ctx->num_cs_dw_streamout_end = 0;
1090 }
1091
1092 /* The max number of bytes to copy per packet. */
1093 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
1094
1095 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
1096 struct pipe_resource *dst, uint64_t dst_offset,
1097 struct pipe_resource *src, uint64_t src_offset,
1098 unsigned size)
1099 {
1100 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1101
1102 assert(size);
1103 assert(rctx->chip_class != R600);
1104
1105 /* CP DMA doesn't work on R600 (flushing seems to be unreliable). */
1106 if (rctx->chip_class == R600) {
1107 return;
1108 }
1109
1110 dst_offset += r600_resource_va(&rctx->screen->screen, dst);
1111 src_offset += r600_resource_va(&rctx->screen->screen, src);
1112
1113 /* We flush the caches, because we might read from or write
1114 * to resources which are bound right now. */
1115 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES |
1116 R600_CONTEXT_FLUSH_AND_INV |
1117 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1118 R600_CONTEXT_STREAMOUT_FLUSH |
1119 R600_CONTEXT_WAIT_3D_IDLE;
1120
1121 /* There are differences between R700 and EG in CP DMA,
1122 * but we only use the common bits here. */
1123 while (size) {
1124 unsigned sync = 0;
1125 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
1126 unsigned src_reloc, dst_reloc;
1127
1128 r600_need_cs_space(rctx, 10 + (rctx->flags ? R600_MAX_FLUSH_CS_DWORDS : 0), FALSE);
1129
1130 /* Flush the caches for the first copy only. */
1131 if (rctx->flags) {
1132 r600_flush_emit(rctx);
1133 }
1134
1135 /* Do the synchronization after the last copy, so that all data is written to memory. */
1136 if (size == byte_count) {
1137 sync = PKT3_CP_DMA_CP_SYNC;
1138 }
1139
1140 /* This must be done after r600_need_cs_space. */
1141 src_reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)src, RADEON_USAGE_READ);
1142 dst_reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)dst, RADEON_USAGE_WRITE);
1143
1144 r600_write_value(cs, PKT3(PKT3_CP_DMA, 4, 0));
1145 r600_write_value(cs, src_offset); /* SRC_ADDR_LO [31:0] */
1146 r600_write_value(cs, sync | ((src_offset >> 32) & 0xff)); /* CP_SYNC [31] | SRC_ADDR_HI [7:0] */
1147 r600_write_value(cs, dst_offset); /* DST_ADDR_LO [31:0] */
1148 r600_write_value(cs, (dst_offset >> 32) & 0xff); /* DST_ADDR_HI [7:0] */
1149 r600_write_value(cs, byte_count); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
1150
1151 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1152 r600_write_value(cs, src_reloc);
1153 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1154 r600_write_value(cs, dst_reloc);
1155
1156 size -= byte_count;
1157 src_offset += byte_count;
1158 dst_offset += byte_count;
1159 }
1160 }
1161
1162 void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw)
1163 {
1164 /* The number of dwords we already used in the DMA so far. */
1165 num_dw += ctx->rings.dma.cs->cdw;
1166 /* Flush if there's not enough space. */
1167 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
1168 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
1169 }
1170 }
1171
1172 void r600_dma_copy(struct r600_context *rctx,
1173 struct pipe_resource *dst,
1174 struct pipe_resource *src,
1175 uint64_t dst_offset,
1176 uint64_t src_offset,
1177 uint64_t size)
1178 {
1179 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
1180 unsigned i, ncopy, csize, shift;
1181 struct r600_resource *rdst = (struct r600_resource*)dst;
1182 struct r600_resource *rsrc = (struct r600_resource*)src;
1183
1184 /* make sure that the dma ring is only one active */
1185 rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
1186
1187 size >>= 2;
1188 shift = 2;
1189 ncopy = (size / 0xffff) + !!(size % 0xffff);
1190
1191 r600_need_dma_space(rctx, ncopy * 5);
1192 for (i = 0; i < ncopy; i++) {
1193 csize = size < 0xffff ? size : 0xffff;
1194 /* emit reloc before writting cs so that cs is always in consistent state */
1195 r600_context_bo_reloc(rctx, &rctx->rings.dma, rsrc, RADEON_USAGE_READ);
1196 r600_context_bo_reloc(rctx, &rctx->rings.dma, rdst, RADEON_USAGE_WRITE);
1197 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 0, 0, csize);
1198 cs->buf[cs->cdw++] = dst_offset & 0xfffffffc;
1199 cs->buf[cs->cdw++] = src_offset & 0xfffffffc;
1200 cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xff;
1201 cs->buf[cs->cdw++] = (src_offset >> 32UL) & 0xff;
1202 dst_offset += csize << shift;
1203 src_offset += csize << shift;
1204 size -= csize;
1205 }
1206 }