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r600g: add PS_PARTIAL_FLUSH flag
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_hw_context_priv.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30 #include <unistd.h>
31
32 /* Get backends mask */
33 void r600_get_backend_mask(struct r600_context *ctx)
34 {
35 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
36 struct r600_resource *buffer;
37 uint32_t *results;
38 unsigned num_backends = ctx->screen->info.r600_num_backends;
39 unsigned i, mask = 0;
40 uint64_t va;
41
42 /* if backend_map query is supported by the kernel */
43 if (ctx->screen->info.r600_backend_map_valid) {
44 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
45 unsigned backend_map = ctx->screen->info.r600_backend_map;
46 unsigned item_width, item_mask;
47
48 if (ctx->chip_class >= EVERGREEN) {
49 item_width = 4;
50 item_mask = 0x7;
51 } else {
52 item_width = 2;
53 item_mask = 0x3;
54 }
55
56 while(num_tile_pipes--) {
57 i = backend_map & item_mask;
58 mask |= (1<<i);
59 backend_map >>= item_width;
60 }
61 if (mask != 0) {
62 ctx->backend_mask = mask;
63 return;
64 }
65 }
66
67 /* otherwise backup path for older kernels */
68
69 /* create buffer for event data */
70 buffer = (struct r600_resource*)
71 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
72 PIPE_USAGE_STAGING, ctx->max_db*16);
73 if (!buffer)
74 goto err;
75 va = r600_resource_va(&ctx->screen->screen, (void*)buffer);
76
77 /* initialize buffer with zeroes */
78 results = r600_buffer_mmap_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
79 if (results) {
80 memset(results, 0, ctx->max_db * 4 * 4);
81 ctx->ws->buffer_unmap(buffer->cs_buf);
82
83 /* emit EVENT_WRITE for ZPASS_DONE */
84 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
85 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
86 cs->buf[cs->cdw++] = va;
87 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
88
89 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
90 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, &ctx->rings.gfx, buffer, RADEON_USAGE_WRITE);
91
92 /* analyze results */
93 results = r600_buffer_mmap_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
94 if (results) {
95 for(i = 0; i < ctx->max_db; i++) {
96 /* at least highest bit will be set if backend is used */
97 if (results[i*4 + 1])
98 mask |= (1<<i);
99 }
100 ctx->ws->buffer_unmap(buffer->cs_buf);
101 }
102 }
103
104 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
105
106 if (mask != 0) {
107 ctx->backend_mask = mask;
108 return;
109 }
110
111 err:
112 /* fallback to old method - set num_backends lower bits to 1 */
113 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
114 return;
115 }
116
117 static void r600_init_block(struct r600_context *ctx,
118 struct r600_block *block,
119 const struct r600_reg *reg, int index, int nreg,
120 unsigned opcode, unsigned offset_base)
121 {
122 int i = index;
123 int j, n = nreg;
124
125 /* initialize block */
126 block->flags = 0;
127 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
128 block->start_offset = reg[i].offset;
129 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
130 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
131 block->reg = &block->pm4[block->pm4_ndwords];
132 block->pm4_ndwords += n;
133 block->nreg = n;
134 block->nreg_dirty = n;
135 LIST_INITHEAD(&block->list);
136 LIST_INITHEAD(&block->enable_list);
137
138 for (j = 0; j < n; j++) {
139 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
140 block->flags |= REG_FLAG_DIRTY_ALWAYS;
141 }
142 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
143 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
144 block->status |= R600_BLOCK_STATUS_ENABLED;
145 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
146 LIST_ADDTAIL(&block->list,&ctx->dirty);
147 }
148 }
149 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
150 block->flags |= REG_FLAG_FLUSH_CHANGE;
151 }
152
153 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
154 block->nbo++;
155 assert(block->nbo < R600_BLOCK_MAX_BO);
156 block->pm4_bo_index[j] = block->nbo;
157 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
158 block->pm4[block->pm4_ndwords++] = 0x00000000;
159 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
160 }
161 }
162 /* check that we stay in limit */
163 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
164 }
165
166 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
167 unsigned opcode, unsigned offset_base)
168 {
169 struct r600_block *block;
170 struct r600_range *range;
171 int offset;
172
173 for (unsigned i = 0, n = 0; i < nreg; i += n) {
174 /* ignore new block balise */
175 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
176 n = 1;
177 continue;
178 }
179
180 /* register that need relocation are in their own group */
181 /* find number of consecutive registers */
182 n = 0;
183 offset = reg[i].offset;
184 while (reg[i + n].offset == offset) {
185 n++;
186 offset += 4;
187 if ((n + i) >= nreg)
188 break;
189 if (n >= (R600_BLOCK_MAX_REG - 2))
190 break;
191 }
192
193 /* allocate new block */
194 block = calloc(1, sizeof(struct r600_block));
195 if (block == NULL) {
196 return -ENOMEM;
197 }
198 ctx->nblocks++;
199 for (int j = 0; j < n; j++) {
200 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
201 /* create block table if it doesn't exist */
202 if (!range->blocks)
203 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
204 if (!range->blocks) {
205 free(block);
206 return -1;
207 }
208
209 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
210 }
211
212 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
213
214 }
215 return 0;
216 }
217
218 static const struct r600_reg r600_context_reg_list[] = {
219 {R_028D24_DB_HTILE_SURFACE, 0, 0},
220 {R_028614_SPI_VS_OUT_ID_0, 0, 0},
221 {R_028618_SPI_VS_OUT_ID_1, 0, 0},
222 {R_02861C_SPI_VS_OUT_ID_2, 0, 0},
223 {R_028620_SPI_VS_OUT_ID_3, 0, 0},
224 {R_028624_SPI_VS_OUT_ID_4, 0, 0},
225 {R_028628_SPI_VS_OUT_ID_5, 0, 0},
226 {R_02862C_SPI_VS_OUT_ID_6, 0, 0},
227 {R_028630_SPI_VS_OUT_ID_7, 0, 0},
228 {R_028634_SPI_VS_OUT_ID_8, 0, 0},
229 {R_028638_SPI_VS_OUT_ID_9, 0, 0},
230 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
231 {GROUP_FORCE_NEW_BLOCK, 0, 0},
232 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
233 {GROUP_FORCE_NEW_BLOCK, 0, 0},
234 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0},
235 {GROUP_FORCE_NEW_BLOCK, 0, 0},
236 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0},
237 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0},
238 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
239 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
240 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
241 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
242 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
243 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
244 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
245 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
246 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
247 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
248 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
249 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
250 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
251 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
252 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
253 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
254 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
255 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
256 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
257 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
258 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
259 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
260 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
261 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
262 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
263 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
264 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
265 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
266 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
267 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
268 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
269 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
270 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
271 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
272 {R_0286D8_SPI_INPUT_Z, 0, 0},
273 {GROUP_FORCE_NEW_BLOCK, 0, 0},
274 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
275 {GROUP_FORCE_NEW_BLOCK, 0, 0},
276 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
277 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
278 };
279
280 /* initialize */
281 void r600_context_fini(struct r600_context *ctx)
282 {
283 struct r600_block *block;
284 struct r600_range *range;
285
286 if (ctx->range) {
287 for (int i = 0; i < NUM_RANGES; i++) {
288 if (!ctx->range[i].blocks)
289 continue;
290 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
291 block = ctx->range[i].blocks[j];
292 if (block) {
293 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
294 range = &ctx->range[CTX_RANGE_ID(offset)];
295 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
296 }
297 for (int k = 1; k <= block->nbo; k++) {
298 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
299 }
300 free(block);
301 }
302 }
303 free(ctx->range[i].blocks);
304 }
305 }
306 free(ctx->blocks);
307 }
308
309 int r600_setup_block_table(struct r600_context *ctx)
310 {
311 /* setup block table */
312 int c = 0;
313 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
314 if (!ctx->blocks)
315 return -ENOMEM;
316 for (int i = 0; i < NUM_RANGES; i++) {
317 if (!ctx->range[i].blocks)
318 continue;
319 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
320 if (!ctx->range[i].blocks[j])
321 continue;
322
323 add = 1;
324 for (int k = 0; k < c; k++) {
325 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
326 add = 0;
327 break;
328 }
329 }
330 if (add) {
331 assert(c < ctx->nblocks);
332 ctx->blocks[c++] = ctx->range[i].blocks[j];
333 j += (ctx->range[i].blocks[j]->nreg) - 1;
334 }
335 }
336 }
337 return 0;
338 }
339
340 int r600_context_init(struct r600_context *ctx)
341 {
342 int r;
343
344 /* add blocks */
345 r = r600_context_add_block(ctx, r600_context_reg_list,
346 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
347 if (r)
348 goto out_err;
349
350 r = r600_setup_block_table(ctx);
351 if (r)
352 goto out_err;
353
354 ctx->max_db = 4;
355 return 0;
356 out_err:
357 r600_context_fini(ctx);
358 return r;
359 }
360
361 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
362 boolean count_draw_in)
363 {
364 if (!ctx->ws->cs_memory_below_limit(ctx->rings.gfx.cs, ctx->vram, ctx->gtt)) {
365 ctx->gtt = 0;
366 ctx->vram = 0;
367 ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
368 return;
369 }
370 /* all will be accounted once relocation are emited */
371 ctx->gtt = 0;
372 ctx->vram = 0;
373
374 /* The number of dwords we already used in the CS so far. */
375 num_dw += ctx->rings.gfx.cs->cdw;
376
377 if (count_draw_in) {
378 unsigned i;
379
380 /* The number of dwords all the dirty states would take. */
381 for (i = 0; i < R600_NUM_ATOMS; i++) {
382 if (ctx->atoms[i] && ctx->atoms[i]->dirty) {
383 num_dw += ctx->atoms[i]->num_dw;
384 #if R600_TRACE_CS
385 if (ctx->screen->trace_bo) {
386 num_dw += R600_TRACE_CS_DWORDS;
387 }
388 #endif
389 }
390 }
391
392 num_dw += ctx->pm4_dirty_cdwords;
393
394 /* The upper-bound of how much space a draw command would take. */
395 num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
396 #if R600_TRACE_CS
397 if (ctx->screen->trace_bo) {
398 num_dw += R600_TRACE_CS_DWORDS;
399 }
400 #endif
401 }
402
403 /* Count in queries_suspend. */
404 num_dw += ctx->num_cs_dw_nontimer_queries_suspend;
405
406 /* Count in streamout_end at the end of CS. */
407 num_dw += ctx->num_cs_dw_streamout_end;
408
409 /* Count in render_condition(NULL) at the end of CS. */
410 if (ctx->predicate_drawing) {
411 num_dw += 3;
412 }
413
414 /* SX_MISC */
415 if (ctx->chip_class <= R700) {
416 num_dw += 3;
417 }
418
419 /* Count in framebuffer cache flushes at the end of CS. */
420 num_dw += R600_MAX_FLUSH_CS_DWORDS;
421
422 /* The fence at the end of CS. */
423 num_dw += 10;
424
425 /* Flush if there's not enough space. */
426 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
427 ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
428 }
429 }
430
431 void r600_context_dirty_block(struct r600_context *ctx,
432 struct r600_block *block,
433 int dirty, int index)
434 {
435 if ((index + 1) > block->nreg_dirty)
436 block->nreg_dirty = index + 1;
437
438 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
439 block->status |= R600_BLOCK_STATUS_DIRTY;
440 ctx->pm4_dirty_cdwords += block->pm4_ndwords;
441 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
442 block->status |= R600_BLOCK_STATUS_ENABLED;
443 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
444 }
445 LIST_ADDTAIL(&block->list,&ctx->dirty);
446
447 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
448 ctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
449 }
450 }
451 }
452
453 /**
454 * If reg needs a reloc, this function will add it to its block's reloc list.
455 * @return true if reg needs a reloc, false otherwise
456 */
457 static bool r600_reg_set_block_reloc(struct r600_pipe_reg *reg)
458 {
459 unsigned reloc_id;
460
461 if (!reg->block->pm4_bo_index[reg->id]) {
462 return false;
463 }
464 /* find relocation */
465 reloc_id = reg->block->pm4_bo_index[reg->id];
466 pipe_resource_reference(
467 (struct pipe_resource**)&reg->block->reloc[reloc_id].bo,
468 &reg->bo->b.b);
469 reg->block->reloc[reloc_id].bo_usage = reg->bo_usage;
470 return true;
471 }
472
473 /**
474 * This function will emit all the registers in state directly to the command
475 * stream allowing you to bypass the r600_context dirty list.
476 *
477 * This is used for dispatching compute shaders to avoid mixing compute and
478 * 3D states in the context's dirty list.
479 *
480 * @param pkt_flags Should be either 0 or RADEON_CP_PACKET3_COMPUTE_MODE. This
481 * value will be passed on to r600_context_block_emit_dirty an or'd against
482 * the PKT3 headers.
483 */
484 void r600_context_pipe_state_emit(struct r600_context *ctx,
485 struct r600_pipe_state *state,
486 unsigned pkt_flags)
487 {
488 unsigned i;
489
490 /* Mark all blocks as dirty:
491 * Since two registers can be in the same block, we need to make sure
492 * we mark all the blocks dirty before we emit any of them. If we were
493 * to mark blocks dirty and emit them in the same loop, like this:
494 *
495 * foreach (reg in state->regs) {
496 * mark_dirty(reg->block)
497 * emit_block(reg->block)
498 * }
499 *
500 * Then if we have two registers in this state that are in the same
501 * block, we would end up emitting that block twice.
502 */
503 for (i = 0; i < state->nregs; i++) {
504 struct r600_pipe_reg *reg = &state->regs[i];
505 /* Mark all the registers in the block as dirty */
506 reg->block->nreg_dirty = reg->block->nreg;
507 reg->block->status |= R600_BLOCK_STATUS_DIRTY;
508 /* Update the reloc for this register if necessary. */
509 r600_reg_set_block_reloc(reg);
510 }
511
512 /* Emit the registers writes */
513 for (i = 0; i < state->nregs; i++) {
514 struct r600_pipe_reg *reg = &state->regs[i];
515 if (reg->block->status & R600_BLOCK_STATUS_DIRTY) {
516 r600_context_block_emit_dirty(ctx, reg->block, pkt_flags);
517 }
518 }
519 }
520
521 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
522 {
523 struct r600_block *block;
524 int dirty;
525 for (int i = 0; i < state->nregs; i++) {
526 unsigned id;
527 struct r600_pipe_reg *reg = &state->regs[i];
528
529 block = reg->block;
530 id = reg->id;
531
532 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
533
534 if (reg->value != block->reg[id]) {
535 block->reg[id] = reg->value;
536 dirty |= R600_BLOCK_STATUS_DIRTY;
537 }
538 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
539 dirty |= R600_BLOCK_STATUS_DIRTY;
540 if (r600_reg_set_block_reloc(reg)) {
541 /* always force dirty for relocs for now */
542 dirty |= R600_BLOCK_STATUS_DIRTY;
543 }
544
545 if (dirty)
546 r600_context_dirty_block(ctx, block, dirty, id);
547 }
548 }
549
550 /**
551 * @param pkt_flags should be set to RADEON_CP_PACKET3_COMPUTE_MODE if this
552 * block will be used for compute shaders.
553 */
554 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block,
555 unsigned pkt_flags)
556 {
557 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
558 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
559 int cp_dwords = block->pm4_ndwords, start_dword = 0;
560 int new_dwords = 0;
561 int nbo = block->nbo;
562
563 if (block->nreg_dirty == 0 && optional) {
564 goto out;
565 }
566
567 if (nbo) {
568 for (int j = 0; j < block->nreg; j++) {
569 if (block->pm4_bo_index[j]) {
570 /* find relocation */
571 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
572 if (reloc->bo) {
573 block->pm4[reloc->bo_pm4_index] =
574 r600_context_bo_reloc(ctx, &ctx->rings.gfx, reloc->bo, reloc->bo_usage);
575 } else {
576 block->pm4[reloc->bo_pm4_index] = 0;
577 }
578 nbo--;
579 if (nbo == 0)
580 break;
581
582 }
583 }
584 }
585
586 optional &= (block->nreg_dirty != block->nreg);
587 if (optional) {
588 new_dwords = block->nreg_dirty;
589 start_dword = cs->cdw;
590 cp_dwords = new_dwords + 2;
591 }
592 memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4);
593
594 /* We are applying the pkt_flags after copying the register block to
595 * the the command stream, because it is possible this block will be
596 * emitted with a different pkt_flags, and we don't want to store the
597 * pkt_flags in the block.
598 */
599 cs->buf[cs->cdw] |= pkt_flags;
600 cs->cdw += cp_dwords;
601
602 if (optional) {
603 uint32_t newword;
604
605 newword = cs->buf[start_dword];
606 newword &= PKT_COUNT_C;
607 newword |= PKT_COUNT_S(new_dwords);
608 cs->buf[start_dword] = newword;
609 }
610 out:
611 block->status ^= R600_BLOCK_STATUS_DIRTY;
612 block->nreg_dirty = 0;
613 LIST_DELINIT(&block->list);
614 }
615
616 void r600_flush_emit(struct r600_context *rctx)
617 {
618 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
619 unsigned cp_coher_cntl = 0;
620 unsigned wait_until = 0;
621 unsigned emit_flush = 0;
622
623 if (!rctx->flags) {
624 return;
625 }
626
627 if (rctx->flags & R600_CONTEXT_PS_PARTIAL_FLUSH) {
628 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
629 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
630 }
631
632 if (rctx->flags & R600_CONTEXT_WAIT_3D_IDLE) {
633 wait_until |= S_008040_WAIT_3D_IDLE(1);
634 }
635 if (rctx->flags & R600_CONTEXT_WAIT_CP_DMA_IDLE) {
636 wait_until |= S_008040_WAIT_CP_DMA_IDLE(1);
637 }
638
639 if (wait_until) {
640 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
641 if (rctx->family >= CHIP_CAYMAN) {
642 /* emit a PS partial flush on Cayman/TN */
643 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
644 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
645 }
646 }
647
648 if (rctx->chip_class >= R700 &&
649 (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
650 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
651 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0);
652 }
653
654 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) {
655 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
656 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
657 if (rctx->chip_class >= EVERGREEN) {
658 cp_coher_cntl = S_0085F0_CB0_DEST_BASE_ENA(1) |
659 S_0085F0_CB1_DEST_BASE_ENA(1) |
660 S_0085F0_CB2_DEST_BASE_ENA(1) |
661 S_0085F0_CB3_DEST_BASE_ENA(1) |
662 S_0085F0_CB4_DEST_BASE_ENA(1) |
663 S_0085F0_CB5_DEST_BASE_ENA(1) |
664 S_0085F0_CB6_DEST_BASE_ENA(1) |
665 S_0085F0_CB7_DEST_BASE_ENA(1) |
666 S_0085F0_CB8_DEST_BASE_ENA(1) |
667 S_0085F0_CB9_DEST_BASE_ENA(1) |
668 S_0085F0_CB10_DEST_BASE_ENA(1) |
669 S_0085F0_CB11_DEST_BASE_ENA(1) |
670 S_0085F0_DB_DEST_BASE_ENA(1) |
671 S_0085F0_TC_ACTION_ENA(1) |
672 S_0085F0_CB_ACTION_ENA(1) |
673 S_0085F0_DB_ACTION_ENA(1) |
674 S_0085F0_SH_ACTION_ENA(1) |
675 S_0085F0_SMX_ACTION_ENA(1) |
676 S_0085F0_FULL_CACHE_ENA(1);
677 } else {
678 cp_coher_cntl = S_0085F0_SMX_ACTION_ENA(1) |
679 S_0085F0_SH_ACTION_ENA(1) |
680 S_0085F0_VC_ACTION_ENA(1) |
681 S_0085F0_TC_ACTION_ENA(1) |
682 S_0085F0_FULL_CACHE_ENA(1);
683 }
684 }
685
686 if (rctx->flags & R600_CONTEXT_INVAL_READ_CACHES) {
687 cp_coher_cntl |= S_0085F0_VC_ACTION_ENA(1) |
688 S_0085F0_TC_ACTION_ENA(1) |
689 S_0085F0_FULL_CACHE_ENA(1);
690 emit_flush = 1;
691 }
692
693 if (rctx->family >= CHIP_RV770 && rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
694 cp_coher_cntl |= S_0085F0_SO0_DEST_BASE_ENA(1) |
695 S_0085F0_SO1_DEST_BASE_ENA(1) |
696 S_0085F0_SO2_DEST_BASE_ENA(1) |
697 S_0085F0_SO3_DEST_BASE_ENA(1) |
698 S_0085F0_SMX_ACTION_ENA(1);
699 emit_flush = 1;
700 }
701
702 if (emit_flush) {
703 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
704 cs->buf[cs->cdw++] = cp_coher_cntl; /* CP_COHER_CNTL */
705 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
706 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
707 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
708 }
709
710 if (wait_until) {
711 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
712 if (rctx->family < CHIP_CAYMAN) {
713 /* wait for things to settle */
714 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, wait_until);
715 }
716 }
717
718 /* everything is properly flushed */
719 rctx->flags = 0;
720 }
721
722 void r600_context_flush(struct r600_context *ctx, unsigned flags)
723 {
724 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
725
726 if (cs->cdw == ctx->start_cs_cmd.num_dw)
727 return;
728
729 ctx->nontimer_queries_suspended = false;
730 ctx->streamout_suspended = false;
731
732 /* suspend queries */
733 if (ctx->num_cs_dw_nontimer_queries_suspend) {
734 r600_suspend_nontimer_queries(ctx);
735 ctx->nontimer_queries_suspended = true;
736 }
737
738 if (ctx->num_cs_dw_streamout_end) {
739 r600_context_streamout_end(ctx);
740 ctx->streamout_suspended = true;
741 }
742
743 /* flush is needed to avoid lockups on some chips with user fences
744 * this will also flush the framebuffer cache
745 */
746 ctx->flags |= R600_CONTEXT_FLUSH_AND_INV |
747 R600_CONTEXT_FLUSH_AND_INV_CB_META |
748 R600_CONTEXT_WAIT_3D_IDLE |
749 R600_CONTEXT_WAIT_CP_DMA_IDLE;
750
751 r600_flush_emit(ctx);
752
753 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
754 if (ctx->chip_class <= R700) {
755 r600_write_context_reg(cs, R_028350_SX_MISC, 0);
756 }
757
758 /* force to keep tiling flags */
759 if (ctx->keep_tiling_flags) {
760 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
761 }
762
763 /* Flush the CS. */
764 #if R600_TRACE_CS
765 if (ctx->screen->trace_bo) {
766 struct r600_screen *rscreen = ctx->screen;
767 unsigned i;
768
769 for (i = 0; i < cs->cdw; i++) {
770 fprintf(stderr, "[%4d] [%5d] 0x%08x\n", rscreen->cs_count, i, cs->buf[i]);
771 }
772 rscreen->cs_count++;
773 }
774 #endif
775 ctx->ws->cs_flush(ctx->rings.gfx.cs, flags);
776 #if R600_TRACE_CS
777 if (ctx->screen->trace_bo) {
778 struct r600_screen *rscreen = ctx->screen;
779 unsigned i;
780
781 for (i = 0; i < 10; i++) {
782 usleep(5);
783 if (!ctx->ws->buffer_is_busy(rscreen->trace_bo->buf, RADEON_USAGE_READWRITE)) {
784 break;
785 }
786 }
787 if (i == 10) {
788 fprintf(stderr, "timeout on cs lockup likely happen at cs %d dw %d\n",
789 rscreen->trace_ptr[1], rscreen->trace_ptr[0]);
790 } else {
791 fprintf(stderr, "cs %d executed in %dms\n", rscreen->trace_ptr[1], i * 5);
792 }
793 }
794 #endif
795 }
796
797 void r600_begin_new_cs(struct r600_context *ctx)
798 {
799 struct r600_block *enable_block = NULL;
800 unsigned shader;
801
802 ctx->pm4_dirty_cdwords = 0;
803 ctx->flags = 0;
804 ctx->gtt = 0;
805 ctx->vram = 0;
806
807 /* Begin a new CS. */
808 r600_emit_command_buffer(ctx->rings.gfx.cs, &ctx->start_cs_cmd);
809
810 /* Re-emit states. */
811 ctx->alphatest_state.atom.dirty = true;
812 ctx->blend_color.atom.dirty = true;
813 ctx->cb_misc_state.atom.dirty = true;
814 ctx->clip_misc_state.atom.dirty = true;
815 ctx->clip_state.atom.dirty = true;
816 ctx->db_misc_state.atom.dirty = true;
817 ctx->db_state.atom.dirty = true;
818 ctx->framebuffer.atom.dirty = true;
819 ctx->poly_offset_state.atom.dirty = true;
820 ctx->vgt_state.atom.dirty = true;
821 ctx->vgt2_state.atom.dirty = true;
822 ctx->sample_mask.atom.dirty = true;
823 ctx->scissor.atom.dirty = true;
824 ctx->config_state.atom.dirty = true;
825 ctx->stencil_ref.atom.dirty = true;
826 ctx->vertex_fetch_shader.atom.dirty = true;
827 ctx->viewport.atom.dirty = true;
828
829 if (ctx->blend_state.cso)
830 ctx->blend_state.atom.dirty = true;
831 if (ctx->dsa_state.cso)
832 ctx->dsa_state.atom.dirty = true;
833 if (ctx->rasterizer_state.cso)
834 ctx->rasterizer_state.atom.dirty = true;
835
836 if (ctx->chip_class <= R700) {
837 ctx->seamless_cube_map.atom.dirty = true;
838 }
839
840 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
841 r600_vertex_buffers_dirty(ctx);
842
843 /* Re-emit shader resources. */
844 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
845 struct r600_constbuf_state *constbuf = &ctx->constbuf_state[shader];
846 struct r600_textures_info *samplers = &ctx->samplers[shader];
847
848 constbuf->dirty_mask = constbuf->enabled_mask;
849 samplers->views.dirty_mask = samplers->views.enabled_mask;
850 samplers->states.dirty_mask = samplers->states.enabled_mask;
851
852 r600_constant_buffers_dirty(ctx, constbuf);
853 r600_sampler_views_dirty(ctx, &samplers->views);
854 r600_sampler_states_dirty(ctx, &samplers->states);
855 }
856
857 if (ctx->streamout_suspended) {
858 ctx->streamout_start = TRUE;
859 ctx->streamout_append_bitmask = ~0;
860 }
861
862 /* resume queries */
863 if (ctx->nontimer_queries_suspended) {
864 r600_resume_nontimer_queries(ctx);
865 }
866
867 /* set all valid group as dirty so they get reemited on
868 * next draw command
869 */
870 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
871 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
872 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
873 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
874 }
875 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
876 enable_block->nreg_dirty = enable_block->nreg;
877 }
878
879 /* Re-emit the draw state. */
880 ctx->last_primitive_type = -1;
881 ctx->last_start_instance = -1;
882 }
883
884 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
885 {
886 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
887 uint64_t va;
888
889 r600_need_cs_space(ctx, 10, FALSE);
890
891 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
892 va = va + (offset << 2);
893
894 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
895 if (ctx->family >= CHIP_CAYMAN) {
896 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
897 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
898 } else {
899 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
900 }
901
902 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
903 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
904 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */
905 /* DATA_SEL | INT_EN | ADDRESS_HI */
906 cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF);
907 cs->buf[cs->cdw++] = value; /* DATA_LO */
908 cs->buf[cs->cdw++] = 0; /* DATA_HI */
909 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
910 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, &ctx->rings.gfx, fence_bo, RADEON_USAGE_WRITE);
911 }
912
913 static void r600_flush_vgt_streamout(struct r600_context *ctx)
914 {
915 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
916
917 r600_write_config_reg(cs, R_008490_CP_STRMOUT_CNTL, 0);
918
919 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
920 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
921
922 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
923 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
924 cs->buf[cs->cdw++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */
925 cs->buf[cs->cdw++] = 0;
926 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */
927 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */
928 cs->buf[cs->cdw++] = 4; /* poll interval */
929 }
930
931 static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
932 {
933 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
934
935 if (buffer_enable_bit) {
936 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(1));
937 r600_write_context_reg(cs, R_028B20_VGT_STRMOUT_BUFFER_EN, buffer_enable_bit);
938 } else {
939 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(0));
940 }
941 }
942
943 void r600_context_streamout_begin(struct r600_context *ctx)
944 {
945 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
946 struct r600_so_target **t = ctx->so_targets;
947 unsigned *stride_in_dw = ctx->vs_shader->so.stride;
948 unsigned buffer_en, i, update_flags = 0;
949 uint64_t va;
950 unsigned num_cs_dw_streamout_end;
951
952 buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) |
953 (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) |
954 (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) |
955 (ctx->num_so_targets >= 4 && t[3] ? 8 : 0);
956
957 num_cs_dw_streamout_end =
958 12 + /* flush_vgt_streamout */
959 util_bitcount(buffer_en) * 8 + /* STRMOUT_BUFFER_UPDATE */
960 3 /* set_streamout_enable(0) */;
961
962 r600_need_cs_space(ctx,
963 12 + /* flush_vgt_streamout */
964 6 + /* set_streamout_enable */
965 util_bitcount(buffer_en) * 7 + /* SET_CONTEXT_REG */
966 (ctx->family >= CHIP_RS780 &&
967 ctx->family <= CHIP_RV740 ? util_bitcount(buffer_en) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
968 util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 + /* STRMOUT_BUFFER_UPDATE */
969 util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 + /* STRMOUT_BUFFER_UPDATE */
970 (ctx->family > CHIP_R600 && ctx->family < CHIP_RS780 ? 2 : 0) + /* SURFACE_BASE_UPDATE */
971 num_cs_dw_streamout_end, TRUE);
972
973 /* This must be set after r600_need_cs_space. */
974 ctx->num_cs_dw_streamout_end = num_cs_dw_streamout_end;
975
976 if (ctx->chip_class >= EVERGREEN) {
977 evergreen_flush_vgt_streamout(ctx);
978 evergreen_set_streamout_enable(ctx, buffer_en);
979 } else {
980 r600_flush_vgt_streamout(ctx);
981 r600_set_streamout_enable(ctx, buffer_en);
982 }
983
984 for (i = 0; i < ctx->num_so_targets; i++) {
985 if (t[i]) {
986 t[i]->stride_in_dw = stride_in_dw[i];
987 t[i]->so_index = i;
988 va = r600_resource_va(&ctx->screen->screen,
989 (void*)t[i]->b.buffer);
990
991 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
992
993 r600_write_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
994 r600_write_value(cs, (t[i]->b.buffer_offset +
995 t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
996 r600_write_value(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
997 r600_write_value(cs, va >> 8); /* BUFFER_BASE */
998
999 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1000 cs->buf[cs->cdw++] =
1001 r600_context_bo_reloc(ctx, &ctx->rings.gfx, r600_resource(t[i]->b.buffer),
1002 RADEON_USAGE_WRITE);
1003
1004 /* R7xx requires this packet after updating BUFFER_BASE.
1005 * Without this, R7xx locks up. */
1006 if (ctx->family >= CHIP_RS780 && ctx->family <= CHIP_RV740) {
1007 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0);
1008 cs->buf[cs->cdw++] = i;
1009 cs->buf[cs->cdw++] = va >> 8;
1010
1011 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1012 cs->buf[cs->cdw++] =
1013 r600_context_bo_reloc(ctx, &ctx->rings.gfx, r600_resource(t[i]->b.buffer),
1014 RADEON_USAGE_WRITE);
1015 }
1016
1017 if (ctx->streamout_append_bitmask & (1 << i)) {
1018 va = r600_resource_va(&ctx->screen->screen,
1019 (void*)t[i]->buf_filled_size) + t[i]->buf_filled_size_offset;
1020 /* Append. */
1021 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1022 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1023 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
1024 cs->buf[cs->cdw++] = 0; /* unused */
1025 cs->buf[cs->cdw++] = 0; /* unused */
1026 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1027 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1028
1029 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1030 cs->buf[cs->cdw++] =
1031 r600_context_bo_reloc(ctx, &ctx->rings.gfx, t[i]->buf_filled_size,
1032 RADEON_USAGE_READ);
1033 } else {
1034 /* Start from the beginning. */
1035 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1036 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1037 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
1038 cs->buf[cs->cdw++] = 0; /* unused */
1039 cs->buf[cs->cdw++] = 0; /* unused */
1040 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
1041 cs->buf[cs->cdw++] = 0; /* unused */
1042 }
1043 }
1044 }
1045
1046 if (ctx->family > CHIP_R600 && ctx->family < CHIP_RS780) {
1047 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
1048 cs->buf[cs->cdw++] = update_flags;
1049 }
1050 }
1051
1052 void r600_context_streamout_end(struct r600_context *ctx)
1053 {
1054 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
1055 struct r600_so_target **t = ctx->so_targets;
1056 unsigned i;
1057 uint64_t va;
1058
1059 if (ctx->chip_class >= EVERGREEN) {
1060 evergreen_flush_vgt_streamout(ctx);
1061 } else {
1062 r600_flush_vgt_streamout(ctx);
1063 }
1064
1065 for (i = 0; i < ctx->num_so_targets; i++) {
1066 if (t[i]) {
1067 va = r600_resource_va(&ctx->screen->screen,
1068 (void*)t[i]->buf_filled_size) + t[i]->buf_filled_size_offset;
1069 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1070 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1071 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
1072 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
1073 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* dst address lo */
1074 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* dst address hi */
1075 cs->buf[cs->cdw++] = 0; /* unused */
1076 cs->buf[cs->cdw++] = 0; /* unused */
1077
1078 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1079 cs->buf[cs->cdw++] =
1080 r600_context_bo_reloc(ctx, &ctx->rings.gfx, t[i]->buf_filled_size,
1081 RADEON_USAGE_WRITE);
1082
1083 }
1084 }
1085
1086 if (ctx->chip_class >= EVERGREEN) {
1087 ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
1088 evergreen_set_streamout_enable(ctx, 0);
1089 } else {
1090 if (ctx->chip_class >= R700) {
1091 ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
1092 }
1093 r600_set_streamout_enable(ctx, 0);
1094 }
1095 ctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1096 ctx->num_cs_dw_streamout_end = 0;
1097 }
1098
1099 /* The max number of bytes to copy per packet. */
1100 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
1101
1102 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
1103 struct pipe_resource *dst, uint64_t dst_offset,
1104 struct pipe_resource *src, uint64_t src_offset,
1105 unsigned size)
1106 {
1107 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1108
1109 assert(size);
1110 assert(rctx->chip_class != R600);
1111
1112 /* CP DMA doesn't work on R600 (flushing seems to be unreliable). */
1113 if (rctx->chip_class == R600) {
1114 return;
1115 }
1116
1117 dst_offset += r600_resource_va(&rctx->screen->screen, dst);
1118 src_offset += r600_resource_va(&rctx->screen->screen, src);
1119
1120 /* We flush the caches, because we might read from or write
1121 * to resources which are bound right now. */
1122 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES |
1123 R600_CONTEXT_FLUSH_AND_INV |
1124 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1125 R600_CONTEXT_STREAMOUT_FLUSH |
1126 R600_CONTEXT_WAIT_3D_IDLE;
1127
1128 /* There are differences between R700 and EG in CP DMA,
1129 * but we only use the common bits here. */
1130 while (size) {
1131 unsigned sync = 0;
1132 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
1133 unsigned src_reloc, dst_reloc;
1134
1135 r600_need_cs_space(rctx, 10 + (rctx->flags ? R600_MAX_FLUSH_CS_DWORDS : 0), FALSE);
1136
1137 /* Flush the caches for the first copy only. */
1138 if (rctx->flags) {
1139 r600_flush_emit(rctx);
1140 }
1141
1142 /* Do the synchronization after the last copy, so that all data is written to memory. */
1143 if (size == byte_count) {
1144 sync = PKT3_CP_DMA_CP_SYNC;
1145 }
1146
1147 /* This must be done after r600_need_cs_space. */
1148 src_reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)src, RADEON_USAGE_READ);
1149 dst_reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)dst, RADEON_USAGE_WRITE);
1150
1151 r600_write_value(cs, PKT3(PKT3_CP_DMA, 4, 0));
1152 r600_write_value(cs, src_offset); /* SRC_ADDR_LO [31:0] */
1153 r600_write_value(cs, sync | ((src_offset >> 32) & 0xff)); /* CP_SYNC [31] | SRC_ADDR_HI [7:0] */
1154 r600_write_value(cs, dst_offset); /* DST_ADDR_LO [31:0] */
1155 r600_write_value(cs, (dst_offset >> 32) & 0xff); /* DST_ADDR_HI [7:0] */
1156 r600_write_value(cs, byte_count); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
1157
1158 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1159 r600_write_value(cs, src_reloc);
1160 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1161 r600_write_value(cs, dst_reloc);
1162
1163 size -= byte_count;
1164 src_offset += byte_count;
1165 dst_offset += byte_count;
1166 }
1167
1168 /* Invalidate the read caches. */
1169 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
1170 }
1171
1172 void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw)
1173 {
1174 /* The number of dwords we already used in the DMA so far. */
1175 num_dw += ctx->rings.dma.cs->cdw;
1176 /* Flush if there's not enough space. */
1177 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
1178 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
1179 }
1180 }
1181
1182 void r600_dma_copy(struct r600_context *rctx,
1183 struct pipe_resource *dst,
1184 struct pipe_resource *src,
1185 uint64_t dst_offset,
1186 uint64_t src_offset,
1187 uint64_t size)
1188 {
1189 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
1190 unsigned i, ncopy, csize, shift;
1191 struct r600_resource *rdst = (struct r600_resource*)dst;
1192 struct r600_resource *rsrc = (struct r600_resource*)src;
1193
1194 /* make sure that the dma ring is only one active */
1195 rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
1196
1197 size >>= 2;
1198 shift = 2;
1199 ncopy = (size / 0xffff) + !!(size % 0xffff);
1200
1201 r600_need_dma_space(rctx, ncopy * 5);
1202 for (i = 0; i < ncopy; i++) {
1203 csize = size < 0xffff ? size : 0xffff;
1204 /* emit reloc before writting cs so that cs is always in consistent state */
1205 r600_context_bo_reloc(rctx, &rctx->rings.dma, rsrc, RADEON_USAGE_READ);
1206 r600_context_bo_reloc(rctx, &rctx->rings.dma, rdst, RADEON_USAGE_WRITE);
1207 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 0, 0, csize);
1208 cs->buf[cs->cdw++] = dst_offset & 0xfffffffc;
1209 cs->buf[cs->cdw++] = src_offset & 0xfffffffc;
1210 cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xff;
1211 cs->buf[cs->cdw++] = (src_offset >> 32UL) & 0xff;
1212 dst_offset += csize << shift;
1213 src_offset += csize << shift;
1214 size -= csize;
1215 }
1216 }