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r600g: atomize fetch shader
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_hw_context_priv.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30
31 /* Get backends mask */
32 void r600_get_backend_mask(struct r600_context *ctx)
33 {
34 struct radeon_winsys_cs *cs = ctx->cs;
35 struct r600_resource *buffer;
36 uint32_t *results;
37 unsigned num_backends = ctx->screen->info.r600_num_backends;
38 unsigned i, mask = 0;
39 uint64_t va;
40
41 /* if backend_map query is supported by the kernel */
42 if (ctx->screen->info.r600_backend_map_valid) {
43 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
44 unsigned backend_map = ctx->screen->info.r600_backend_map;
45 unsigned item_width, item_mask;
46
47 if (ctx->chip_class >= EVERGREEN) {
48 item_width = 4;
49 item_mask = 0x7;
50 } else {
51 item_width = 2;
52 item_mask = 0x3;
53 }
54
55 while(num_tile_pipes--) {
56 i = backend_map & item_mask;
57 mask |= (1<<i);
58 backend_map >>= item_width;
59 }
60 if (mask != 0) {
61 ctx->backend_mask = mask;
62 return;
63 }
64 }
65
66 /* otherwise backup path for older kernels */
67
68 /* create buffer for event data */
69 buffer = (struct r600_resource*)
70 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
71 PIPE_USAGE_STAGING, ctx->max_db*16);
72 if (!buffer)
73 goto err;
74
75 va = r600_resource_va(&ctx->screen->screen, (void*)buffer);
76
77 /* initialize buffer with zeroes */
78 results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE);
79 if (results) {
80 memset(results, 0, ctx->max_db * 4 * 4);
81 ctx->ws->buffer_unmap(buffer->cs_buf);
82
83 /* emit EVENT_WRITE for ZPASS_DONE */
84 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
85 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
86 cs->buf[cs->cdw++] = va;
87 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
88
89 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
90 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE);
91
92 /* analyze results */
93 results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_READ);
94 if (results) {
95 for(i = 0; i < ctx->max_db; i++) {
96 /* at least highest bit will be set if backend is used */
97 if (results[i*4 + 1])
98 mask |= (1<<i);
99 }
100 ctx->ws->buffer_unmap(buffer->cs_buf);
101 }
102 }
103
104 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
105
106 if (mask != 0) {
107 ctx->backend_mask = mask;
108 return;
109 }
110
111 err:
112 /* fallback to old method - set num_backends lower bits to 1 */
113 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
114 return;
115 }
116
117 static void r600_init_block(struct r600_context *ctx,
118 struct r600_block *block,
119 const struct r600_reg *reg, int index, int nreg,
120 unsigned opcode, unsigned offset_base)
121 {
122 int i = index;
123 int j, n = nreg;
124
125 /* initialize block */
126 block->flags = 0;
127 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
128 block->start_offset = reg[i].offset;
129 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
130 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
131 block->reg = &block->pm4[block->pm4_ndwords];
132 block->pm4_ndwords += n;
133 block->nreg = n;
134 block->nreg_dirty = n;
135 LIST_INITHEAD(&block->list);
136 LIST_INITHEAD(&block->enable_list);
137
138 for (j = 0; j < n; j++) {
139 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
140 block->flags |= REG_FLAG_DIRTY_ALWAYS;
141 }
142 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
143 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
144 block->status |= R600_BLOCK_STATUS_ENABLED;
145 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
146 LIST_ADDTAIL(&block->list,&ctx->dirty);
147 }
148 }
149 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
150 block->flags |= REG_FLAG_FLUSH_CHANGE;
151 }
152
153 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
154 block->nbo++;
155 assert(block->nbo < R600_BLOCK_MAX_BO);
156 block->pm4_bo_index[j] = block->nbo;
157 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
158 block->pm4[block->pm4_ndwords++] = 0x00000000;
159 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
160 }
161 }
162 /* check that we stay in limit */
163 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
164 }
165
166 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
167 unsigned opcode, unsigned offset_base)
168 {
169 struct r600_block *block;
170 struct r600_range *range;
171 int offset;
172
173 for (unsigned i = 0, n = 0; i < nreg; i += n) {
174 /* ignore new block balise */
175 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
176 n = 1;
177 continue;
178 }
179
180 /* register that need relocation are in their own group */
181 /* find number of consecutive registers */
182 n = 0;
183 offset = reg[i].offset;
184 while (reg[i + n].offset == offset) {
185 n++;
186 offset += 4;
187 if ((n + i) >= nreg)
188 break;
189 if (n >= (R600_BLOCK_MAX_REG - 2))
190 break;
191 }
192
193 /* allocate new block */
194 block = calloc(1, sizeof(struct r600_block));
195 if (block == NULL) {
196 return -ENOMEM;
197 }
198 ctx->nblocks++;
199 for (int j = 0; j < n; j++) {
200 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
201 /* create block table if it doesn't exist */
202 if (!range->blocks)
203 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
204 if (!range->blocks)
205 return -1;
206
207 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
208 }
209
210 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
211
212 }
213 return 0;
214 }
215
216 /* R600/R700 configuration */
217 static const struct r600_reg r600_config_reg_list[] = {
218 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
219 };
220
221 static const struct r600_reg r600_context_reg_list[] = {
222 {R_028A4C_PA_SC_MODE_CNTL, 0, 0},
223 {GROUP_FORCE_NEW_BLOCK, 0, 0},
224 {R_028800_DB_DEPTH_CONTROL, 0, 0},
225 {R_02880C_DB_SHADER_CONTROL, 0, 0},
226 {GROUP_FORCE_NEW_BLOCK, 0, 0},
227 {R_028D24_DB_HTILE_SURFACE, 0, 0},
228 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
229 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
230 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
231 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
232 {R_028A00_PA_SU_POINT_SIZE, 0, 0},
233 {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
234 {R_028A08_PA_SU_LINE_CNTL, 0, 0},
235 {R_028C08_PA_SU_VTX_CNTL, 0, 0},
236 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
237 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
238 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
239 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
240 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
241 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
242 {R_028350_SX_MISC, 0, 0},
243 {R_028380_SQ_VTX_SEMANTIC_0, 0, 0},
244 {R_028384_SQ_VTX_SEMANTIC_1, 0, 0},
245 {R_028388_SQ_VTX_SEMANTIC_2, 0, 0},
246 {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0},
247 {R_028390_SQ_VTX_SEMANTIC_4, 0, 0},
248 {R_028394_SQ_VTX_SEMANTIC_5, 0, 0},
249 {R_028398_SQ_VTX_SEMANTIC_6, 0, 0},
250 {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0},
251 {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0},
252 {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0},
253 {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0},
254 {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0},
255 {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0},
256 {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0},
257 {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0},
258 {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0},
259 {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0},
260 {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0},
261 {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0},
262 {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0},
263 {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0},
264 {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0},
265 {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0},
266 {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0},
267 {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0},
268 {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0},
269 {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0},
270 {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0},
271 {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0},
272 {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0},
273 {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0},
274 {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0},
275 {R_028614_SPI_VS_OUT_ID_0, 0, 0},
276 {R_028618_SPI_VS_OUT_ID_1, 0, 0},
277 {R_02861C_SPI_VS_OUT_ID_2, 0, 0},
278 {R_028620_SPI_VS_OUT_ID_3, 0, 0},
279 {R_028624_SPI_VS_OUT_ID_4, 0, 0},
280 {R_028628_SPI_VS_OUT_ID_5, 0, 0},
281 {R_02862C_SPI_VS_OUT_ID_6, 0, 0},
282 {R_028630_SPI_VS_OUT_ID_7, 0, 0},
283 {R_028634_SPI_VS_OUT_ID_8, 0, 0},
284 {R_028638_SPI_VS_OUT_ID_9, 0, 0},
285 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
286 {GROUP_FORCE_NEW_BLOCK, 0, 0},
287 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
288 {GROUP_FORCE_NEW_BLOCK, 0, 0},
289 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0},
290 {GROUP_FORCE_NEW_BLOCK, 0, 0},
291 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0},
292 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0},
293 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
294 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
295 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
296 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
297 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
298 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
299 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
300 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
301 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
302 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
303 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
304 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
305 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
306 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
307 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
308 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
309 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
310 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
311 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
312 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
313 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
314 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
315 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
316 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
317 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
318 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
319 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
320 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
321 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
322 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
323 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
324 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
325 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
326 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
327 {R_0286D8_SPI_INPUT_Z, 0, 0},
328 {GROUP_FORCE_NEW_BLOCK, 0, 0},
329 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
330 {GROUP_FORCE_NEW_BLOCK, 0, 0},
331 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
332 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
333 };
334
335 /* initialize */
336 void r600_context_fini(struct r600_context *ctx)
337 {
338 struct r600_block *block;
339 struct r600_range *range;
340
341 if (ctx->range) {
342 for (int i = 0; i < NUM_RANGES; i++) {
343 if (!ctx->range[i].blocks)
344 continue;
345 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
346 block = ctx->range[i].blocks[j];
347 if (block) {
348 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
349 range = &ctx->range[CTX_RANGE_ID(offset)];
350 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
351 }
352 for (int k = 1; k <= block->nbo; k++) {
353 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
354 }
355 free(block);
356 }
357 }
358 free(ctx->range[i].blocks);
359 }
360 }
361 free(ctx->blocks);
362 }
363
364 int r600_setup_block_table(struct r600_context *ctx)
365 {
366 /* setup block table */
367 int c = 0;
368 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
369 if (!ctx->blocks)
370 return -ENOMEM;
371 for (int i = 0; i < NUM_RANGES; i++) {
372 if (!ctx->range[i].blocks)
373 continue;
374 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
375 if (!ctx->range[i].blocks[j])
376 continue;
377
378 add = 1;
379 for (int k = 0; k < c; k++) {
380 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
381 add = 0;
382 break;
383 }
384 }
385 if (add) {
386 assert(c < ctx->nblocks);
387 ctx->blocks[c++] = ctx->range[i].blocks[j];
388 j += (ctx->range[i].blocks[j]->nreg) - 1;
389 }
390 }
391 }
392 return 0;
393 }
394
395 int r600_context_init(struct r600_context *ctx)
396 {
397 int r;
398
399 /* add blocks */
400 r = r600_context_add_block(ctx, r600_config_reg_list,
401 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
402 if (r)
403 goto out_err;
404 r = r600_context_add_block(ctx, r600_context_reg_list,
405 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
406 if (r)
407 goto out_err;
408
409 r = r600_setup_block_table(ctx);
410 if (r)
411 goto out_err;
412
413 ctx->max_db = 4;
414 return 0;
415 out_err:
416 r600_context_fini(ctx);
417 return r;
418 }
419
420 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
421 boolean count_draw_in)
422 {
423 /* The number of dwords we already used in the CS so far. */
424 num_dw += ctx->cs->cdw;
425
426 if (count_draw_in) {
427 unsigned i;
428
429 /* The number of dwords all the dirty states would take. */
430 for (i = 0; i < R600_NUM_ATOMS; i++) {
431 if (ctx->atoms[i] && ctx->atoms[i]->dirty) {
432 num_dw += ctx->atoms[i]->num_dw;
433 }
434 }
435
436 num_dw += ctx->pm4_dirty_cdwords;
437
438 /* The upper-bound of how much space a draw command would take. */
439 num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
440 }
441
442 /* Count in queries_suspend. */
443 num_dw += ctx->num_cs_dw_nontimer_queries_suspend;
444 num_dw += ctx->num_cs_dw_timer_queries_suspend;
445
446 /* Count in streamout_end at the end of CS. */
447 num_dw += ctx->num_cs_dw_streamout_end;
448
449 /* Count in render_condition(NULL) at the end of CS. */
450 if (ctx->predicate_drawing) {
451 num_dw += 3;
452 }
453
454 /* SX_MISC */
455 if (ctx->chip_class <= R700) {
456 num_dw += 3;
457 }
458
459 /* Count in framebuffer cache flushes at the end of CS. */
460 num_dw += R600_MAX_FLUSH_CS_DWORDS;
461
462 /* The fence at the end of CS. */
463 num_dw += 10;
464
465 /* Flush if there's not enough space. */
466 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
467 r600_flush(&ctx->context, NULL, RADEON_FLUSH_ASYNC);
468 }
469 }
470
471 void r600_context_dirty_block(struct r600_context *ctx,
472 struct r600_block *block,
473 int dirty, int index)
474 {
475 if ((index + 1) > block->nreg_dirty)
476 block->nreg_dirty = index + 1;
477
478 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
479 block->status |= R600_BLOCK_STATUS_DIRTY;
480 ctx->pm4_dirty_cdwords += block->pm4_ndwords;
481 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
482 block->status |= R600_BLOCK_STATUS_ENABLED;
483 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
484 }
485 LIST_ADDTAIL(&block->list,&ctx->dirty);
486
487 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
488 ctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
489 }
490 }
491 }
492
493 /**
494 * If reg needs a reloc, this function will add it to its block's reloc list.
495 * @return true if reg needs a reloc, false otherwise
496 */
497 static bool r600_reg_set_block_reloc(struct r600_pipe_reg *reg)
498 {
499 unsigned reloc_id;
500
501 if (!reg->block->pm4_bo_index[reg->id]) {
502 return false;
503 }
504 /* find relocation */
505 reloc_id = reg->block->pm4_bo_index[reg->id];
506 pipe_resource_reference(
507 (struct pipe_resource**)&reg->block->reloc[reloc_id].bo,
508 &reg->bo->b.b);
509 reg->block->reloc[reloc_id].bo_usage = reg->bo_usage;
510 return true;
511 }
512
513 /**
514 * This function will emit all the registers in state directly to the command
515 * stream allowing you to bypass the r600_context dirty list.
516 *
517 * This is used for dispatching compute shaders to avoid mixing compute and
518 * 3D states in the context's dirty list.
519 *
520 * @param pkt_flags Should be either 0 or RADEON_CP_PACKET3_COMPUTE_MODE. This
521 * value will be passed on to r600_context_block_emit_dirty an or'd against
522 * the PKT3 headers.
523 */
524 void r600_context_pipe_state_emit(struct r600_context *ctx,
525 struct r600_pipe_state *state,
526 unsigned pkt_flags)
527 {
528 unsigned i;
529
530 /* Mark all blocks as dirty:
531 * Since two registers can be in the same block, we need to make sure
532 * we mark all the blocks dirty before we emit any of them. If we were
533 * to mark blocks dirty and emit them in the same loop, like this:
534 *
535 * foreach (reg in state->regs) {
536 * mark_dirty(reg->block)
537 * emit_block(reg->block)
538 * }
539 *
540 * Then if we have two registers in this state that are in the same
541 * block, we would end up emitting that block twice.
542 */
543 for (i = 0; i < state->nregs; i++) {
544 struct r600_pipe_reg *reg = &state->regs[i];
545 /* Mark all the registers in the block as dirty */
546 reg->block->nreg_dirty = reg->block->nreg;
547 reg->block->status |= R600_BLOCK_STATUS_DIRTY;
548 /* Update the reloc for this register if necessary. */
549 r600_reg_set_block_reloc(reg);
550 }
551
552 /* Emit the registers writes */
553 for (i = 0; i < state->nregs; i++) {
554 struct r600_pipe_reg *reg = &state->regs[i];
555 if (reg->block->status & R600_BLOCK_STATUS_DIRTY) {
556 r600_context_block_emit_dirty(ctx, reg->block, pkt_flags);
557 }
558 }
559 }
560
561 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
562 {
563 struct r600_block *block;
564 int dirty;
565 for (int i = 0; i < state->nregs; i++) {
566 unsigned id;
567 struct r600_pipe_reg *reg = &state->regs[i];
568
569 block = reg->block;
570 id = reg->id;
571
572 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
573
574 if (reg->value != block->reg[id]) {
575 block->reg[id] = reg->value;
576 dirty |= R600_BLOCK_STATUS_DIRTY;
577 }
578 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
579 dirty |= R600_BLOCK_STATUS_DIRTY;
580 if (r600_reg_set_block_reloc(reg)) {
581 /* always force dirty for relocs for now */
582 dirty |= R600_BLOCK_STATUS_DIRTY;
583 }
584
585 if (dirty)
586 r600_context_dirty_block(ctx, block, dirty, id);
587 }
588 }
589
590 /**
591 * @param pkt_flags should be set to RADEON_CP_PACKET3_COMPUTE_MODE if this
592 * block will be used for compute shaders.
593 */
594 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block,
595 unsigned pkt_flags)
596 {
597 struct radeon_winsys_cs *cs = ctx->cs;
598 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
599 int cp_dwords = block->pm4_ndwords, start_dword = 0;
600 int new_dwords = 0;
601 int nbo = block->nbo;
602
603 if (block->nreg_dirty == 0 && optional) {
604 goto out;
605 }
606
607 if (nbo) {
608 for (int j = 0; j < block->nreg; j++) {
609 if (block->pm4_bo_index[j]) {
610 /* find relocation */
611 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
612 if (reloc->bo) {
613 block->pm4[reloc->bo_pm4_index] =
614 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage);
615 } else {
616 block->pm4[reloc->bo_pm4_index] = 0;
617 }
618 nbo--;
619 if (nbo == 0)
620 break;
621
622 }
623 }
624 }
625
626 optional &= (block->nreg_dirty != block->nreg);
627 if (optional) {
628 new_dwords = block->nreg_dirty;
629 start_dword = cs->cdw;
630 cp_dwords = new_dwords + 2;
631 }
632 memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4);
633
634 /* We are applying the pkt_flags after copying the register block to
635 * the the command stream, because it is possible this block will be
636 * emitted with a different pkt_flags, and we don't want to store the
637 * pkt_flags in the block.
638 */
639 cs->buf[cs->cdw] |= pkt_flags;
640 cs->cdw += cp_dwords;
641
642 if (optional) {
643 uint32_t newword;
644
645 newword = cs->buf[start_dword];
646 newword &= PKT_COUNT_C;
647 newword |= PKT_COUNT_S(new_dwords);
648 cs->buf[start_dword] = newword;
649 }
650 out:
651 block->status ^= R600_BLOCK_STATUS_DIRTY;
652 block->nreg_dirty = 0;
653 LIST_DELINIT(&block->list);
654 }
655
656 void r600_flush_emit(struct r600_context *rctx)
657 {
658 struct radeon_winsys_cs *cs = rctx->cs;
659
660 if (!rctx->flags) {
661 return;
662 }
663
664 if (rctx->flags & R600_CONTEXT_PS_PARTIAL_FLUSH) {
665 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
666 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
667 }
668
669 if (rctx->chip_class >= R700 &&
670 (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
671 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
672 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0);
673 }
674
675 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) {
676 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
677 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
678
679 /* DB flushes are special due to errata with hyperz, we need to
680 * insert a no-op, so that the cache has time to really flush.
681 */
682 if (rctx->chip_class <= R700 &&
683 rctx->flags & R600_CONTEXT_HTILE_ERRATA) {
684 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 31, 0);
685 cs->buf[cs->cdw++] = 0xdeadcafe;
686 cs->buf[cs->cdw++] = 0xdeadcafe;
687 cs->buf[cs->cdw++] = 0xdeadcafe;
688 cs->buf[cs->cdw++] = 0xdeadcafe;
689 cs->buf[cs->cdw++] = 0xdeadcafe;
690 cs->buf[cs->cdw++] = 0xdeadcafe;
691 cs->buf[cs->cdw++] = 0xdeadcafe;
692 cs->buf[cs->cdw++] = 0xdeadcafe;
693 cs->buf[cs->cdw++] = 0xdeadcafe;
694 cs->buf[cs->cdw++] = 0xdeadcafe;
695 cs->buf[cs->cdw++] = 0xdeadcafe;
696 cs->buf[cs->cdw++] = 0xdeadcafe;
697 cs->buf[cs->cdw++] = 0xdeadcafe;
698 cs->buf[cs->cdw++] = 0xdeadcafe;
699 cs->buf[cs->cdw++] = 0xdeadcafe;
700 cs->buf[cs->cdw++] = 0xdeadcafe;
701 cs->buf[cs->cdw++] = 0xdeadcafe;
702 cs->buf[cs->cdw++] = 0xdeadcafe;
703 cs->buf[cs->cdw++] = 0xdeadcafe;
704 cs->buf[cs->cdw++] = 0xdeadcafe;
705 cs->buf[cs->cdw++] = 0xdeadcafe;
706 cs->buf[cs->cdw++] = 0xdeadcafe;
707 cs->buf[cs->cdw++] = 0xdeadcafe;
708 cs->buf[cs->cdw++] = 0xdeadcafe;
709 cs->buf[cs->cdw++] = 0xdeadcafe;
710 cs->buf[cs->cdw++] = 0xdeadcafe;
711 cs->buf[cs->cdw++] = 0xdeadcafe;
712 cs->buf[cs->cdw++] = 0xdeadcafe;
713 cs->buf[cs->cdw++] = 0xdeadcafe;
714 cs->buf[cs->cdw++] = 0xdeadcafe;
715 cs->buf[cs->cdw++] = 0xdeadcafe;
716 cs->buf[cs->cdw++] = 0xdeadcafe;
717 }
718 }
719
720 if (rctx->flags & (R600_CONTEXT_CB_FLUSH |
721 R600_CONTEXT_DB_FLUSH |
722 R600_CONTEXT_SHADERCONST_FLUSH |
723 R600_CONTEXT_TEX_FLUSH |
724 R600_CONTEXT_VTX_FLUSH |
725 R600_CONTEXT_STREAMOUT_FLUSH)) {
726 /* anything left (cb, vtx, shader, streamout) can be flushed
727 * using the surface sync packet
728 */
729 unsigned flags = 0;
730
731 if (rctx->flags & R600_CONTEXT_CB_FLUSH) {
732 flags |= S_0085F0_CB_ACTION_ENA(1) |
733 S_0085F0_CB0_DEST_BASE_ENA(1) |
734 S_0085F0_CB1_DEST_BASE_ENA(1) |
735 S_0085F0_CB2_DEST_BASE_ENA(1) |
736 S_0085F0_CB3_DEST_BASE_ENA(1) |
737 S_0085F0_CB4_DEST_BASE_ENA(1) |
738 S_0085F0_CB5_DEST_BASE_ENA(1) |
739 S_0085F0_CB6_DEST_BASE_ENA(1) |
740 S_0085F0_CB7_DEST_BASE_ENA(1);
741
742 if (rctx->chip_class >= EVERGREEN) {
743 flags |= S_0085F0_CB8_DEST_BASE_ENA(1) |
744 S_0085F0_CB9_DEST_BASE_ENA(1) |
745 S_0085F0_CB10_DEST_BASE_ENA(1) |
746 S_0085F0_CB11_DEST_BASE_ENA(1);
747 }
748
749 /* RV670 errata
750 * (CB1_DEST_BASE_ENA is also required, which is
751 * included unconditionally above). */
752 if (rctx->family == CHIP_RV670 ||
753 rctx->family == CHIP_RS780 ||
754 rctx->family == CHIP_RS880) {
755 flags |= S_0085F0_DEST_BASE_0_ENA(1);
756 }
757 }
758
759 if (rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
760 flags |= S_0085F0_SO0_DEST_BASE_ENA(1) |
761 S_0085F0_SO1_DEST_BASE_ENA(1) |
762 S_0085F0_SO2_DEST_BASE_ENA(1) |
763 S_0085F0_SO3_DEST_BASE_ENA(1) |
764 S_0085F0_SMX_ACTION_ENA(1);
765
766 /* RV670 errata */
767 if (rctx->family == CHIP_RV670 ||
768 rctx->family == CHIP_RS780 ||
769 rctx->family == CHIP_RS880) {
770 flags |= S_0085F0_DEST_BASE_0_ENA(1);
771 }
772 }
773
774 flags |= (rctx->flags & R600_CONTEXT_DB_FLUSH) ? S_0085F0_DB_ACTION_ENA(1) |
775 S_0085F0_DB_DEST_BASE_ENA(1): 0;
776 flags |= (rctx->flags & R600_CONTEXT_SHADERCONST_FLUSH) ? S_0085F0_SH_ACTION_ENA(1) : 0;
777 flags |= (rctx->flags & R600_CONTEXT_TEX_FLUSH) ? S_0085F0_TC_ACTION_ENA(1) : 0;
778 flags |= (rctx->flags & R600_CONTEXT_VTX_FLUSH) ? S_0085F0_VC_ACTION_ENA(1) : 0;
779
780 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
781 cs->buf[cs->cdw++] = flags; /* CP_COHER_CNTL */
782 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
783 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
784 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
785 }
786
787 if (rctx->flags & R600_CONTEXT_WAIT_IDLE) {
788 /* wait for things to settle */
789 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
790 }
791
792 /* everything is properly flushed */
793 rctx->flags = 0;
794 }
795
796 void r600_context_flush(struct r600_context *ctx, unsigned flags)
797 {
798 struct radeon_winsys_cs *cs = ctx->cs;
799
800 if (cs->cdw == ctx->start_cs_cmd.num_dw)
801 return;
802
803 ctx->timer_queries_suspended = false;
804 ctx->nontimer_queries_suspended = false;
805 ctx->streamout_suspended = false;
806
807 /* suspend queries */
808 if (ctx->num_cs_dw_timer_queries_suspend) {
809 r600_suspend_timer_queries(ctx);
810 ctx->timer_queries_suspended = true;
811 }
812 if (ctx->num_cs_dw_nontimer_queries_suspend) {
813 r600_suspend_nontimer_queries(ctx);
814 ctx->nontimer_queries_suspended = true;
815 }
816
817 if (ctx->num_cs_dw_streamout_end) {
818 r600_context_streamout_end(ctx);
819 ctx->streamout_suspended = true;
820 }
821
822 /* partial flush is needed to avoid lockups on some chips with user fences */
823 ctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
824
825 /* flush the framebuffer */
826 ctx->flags |= R600_CONTEXT_CB_FLUSH | R600_CONTEXT_DB_FLUSH;
827
828 /* R6xx errata */
829 if (ctx->chip_class == R600) {
830 ctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
831 }
832
833 r600_flush_emit(ctx);
834
835 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
836 if (ctx->chip_class <= R700) {
837 r600_write_context_reg(cs, R_028350_SX_MISC, 0);
838 }
839
840 /* force to keep tiling flags */
841 if (ctx->keep_tiling_flags) {
842 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
843 }
844
845 /* Flush the CS. */
846 ctx->ws->cs_flush(ctx->cs, flags);
847
848 r600_begin_new_cs(ctx);
849 }
850
851 void r600_begin_new_cs(struct r600_context *ctx)
852 {
853 struct r600_block *enable_block = NULL;
854 unsigned shader;
855
856 ctx->pm4_dirty_cdwords = 0;
857 ctx->flags = 0;
858
859 /* Begin a new CS. */
860 r600_emit_command_buffer(ctx->cs, &ctx->start_cs_cmd);
861
862 /* Re-emit states. */
863 ctx->alphatest_state.atom.dirty = true;
864 ctx->blend_color.atom.dirty = true;
865 ctx->cb_misc_state.atom.dirty = true;
866 ctx->clip_misc_state.atom.dirty = true;
867 ctx->clip_state.atom.dirty = true;
868 ctx->db_misc_state.atom.dirty = true;
869 ctx->framebuffer.atom.dirty = true;
870 ctx->vgt_state.atom.dirty = true;
871 ctx->vgt2_state.atom.dirty = true;
872 ctx->sample_mask.atom.dirty = true;
873 ctx->stencil_ref.atom.dirty = true;
874 ctx->vertex_fetch_shader.atom.dirty = true;
875 ctx->viewport.atom.dirty = true;
876
877 if (ctx->blend_state.cso)
878 ctx->blend_state.atom.dirty = true;
879
880 if (ctx->chip_class <= R700) {
881 ctx->seamless_cube_map.atom.dirty = true;
882 }
883
884 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
885 r600_vertex_buffers_dirty(ctx);
886
887 /* Re-emit shader resources. */
888 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
889 struct r600_constbuf_state *constbuf = &ctx->constbuf_state[shader];
890 struct r600_textures_info *samplers = &ctx->samplers[shader];
891
892 constbuf->dirty_mask = constbuf->enabled_mask;
893 samplers->views.dirty_mask = samplers->views.enabled_mask;
894 samplers->states.dirty_mask = samplers->states.enabled_mask;
895
896 r600_constant_buffers_dirty(ctx, constbuf);
897 r600_sampler_views_dirty(ctx, &samplers->views);
898 r600_sampler_states_dirty(ctx, &samplers->states);
899 }
900
901 if (ctx->streamout_suspended) {
902 ctx->streamout_start = TRUE;
903 ctx->streamout_append_bitmask = ~0;
904 }
905
906 /* resume queries */
907 if (ctx->timer_queries_suspended) {
908 r600_resume_timer_queries(ctx);
909 }
910 if (ctx->nontimer_queries_suspended) {
911 r600_resume_nontimer_queries(ctx);
912 }
913
914 /* set all valid group as dirty so they get reemited on
915 * next draw command
916 */
917 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
918 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
919 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
920 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
921 }
922 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
923 enable_block->nreg_dirty = enable_block->nreg;
924 }
925
926 /* Re-emit the draw state. */
927 ctx->last_primitive_type = -1;
928 ctx->last_start_instance = -1;
929 }
930
931 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
932 {
933 struct radeon_winsys_cs *cs = ctx->cs;
934 uint64_t va;
935
936 r600_need_cs_space(ctx, 10, FALSE);
937
938 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
939 va = va + (offset << 2);
940
941 ctx->flags &= ~R600_CONTEXT_PS_PARTIAL_FLUSH;
942 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
943 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
944
945 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
946 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
947 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */
948 /* DATA_SEL | INT_EN | ADDRESS_HI */
949 cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF);
950 cs->buf[cs->cdw++] = value; /* DATA_LO */
951 cs->buf[cs->cdw++] = 0; /* DATA_HI */
952 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
953 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE);
954 }
955
956 static void r600_flush_vgt_streamout(struct r600_context *ctx)
957 {
958 struct radeon_winsys_cs *cs = ctx->cs;
959
960 r600_write_config_reg(cs, R_008490_CP_STRMOUT_CNTL, 0);
961
962 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
963 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
964
965 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
966 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
967 cs->buf[cs->cdw++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */
968 cs->buf[cs->cdw++] = 0;
969 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */
970 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */
971 cs->buf[cs->cdw++] = 4; /* poll interval */
972 }
973
974 static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
975 {
976 struct radeon_winsys_cs *cs = ctx->cs;
977
978 if (buffer_enable_bit) {
979 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(1));
980 r600_write_context_reg(cs, R_028B20_VGT_STRMOUT_BUFFER_EN, buffer_enable_bit);
981 } else {
982 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(0));
983 }
984 }
985
986 void r600_context_streamout_begin(struct r600_context *ctx)
987 {
988 struct radeon_winsys_cs *cs = ctx->cs;
989 struct r600_so_target **t = ctx->so_targets;
990 unsigned *stride_in_dw = ctx->vs_shader->so.stride;
991 unsigned buffer_en, i, update_flags = 0;
992 uint64_t va;
993
994 buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) |
995 (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) |
996 (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) |
997 (ctx->num_so_targets >= 4 && t[3] ? 8 : 0);
998
999 ctx->num_cs_dw_streamout_end =
1000 12 + /* flush_vgt_streamout */
1001 util_bitcount(buffer_en) * 8 + /* STRMOUT_BUFFER_UPDATE */
1002 3 /* set_streamout_enable(0) */;
1003
1004 r600_need_cs_space(ctx,
1005 12 + /* flush_vgt_streamout */
1006 6 + /* set_streamout_enable */
1007 util_bitcount(buffer_en) * 7 + /* SET_CONTEXT_REG */
1008 (ctx->family >= CHIP_RS780 &&
1009 ctx->family <= CHIP_RV740 ? util_bitcount(buffer_en) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
1010 util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 + /* STRMOUT_BUFFER_UPDATE */
1011 util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 + /* STRMOUT_BUFFER_UPDATE */
1012 (ctx->family > CHIP_R600 && ctx->family < CHIP_RS780 ? 2 : 0) + /* SURFACE_BASE_UPDATE */
1013 ctx->num_cs_dw_streamout_end, TRUE);
1014
1015 if (ctx->chip_class >= EVERGREEN) {
1016 evergreen_flush_vgt_streamout(ctx);
1017 evergreen_set_streamout_enable(ctx, buffer_en);
1018 } else {
1019 r600_flush_vgt_streamout(ctx);
1020 r600_set_streamout_enable(ctx, buffer_en);
1021 }
1022
1023 for (i = 0; i < ctx->num_so_targets; i++) {
1024 if (t[i]) {
1025 t[i]->stride_in_dw = stride_in_dw[i];
1026 t[i]->so_index = i;
1027 va = r600_resource_va(&ctx->screen->screen,
1028 (void*)t[i]->b.buffer);
1029
1030 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
1031
1032 r600_write_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
1033 r600_write_value(cs, (t[i]->b.buffer_offset +
1034 t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
1035 r600_write_value(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
1036 r600_write_value(cs, va >> 8); /* BUFFER_BASE */
1037
1038 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1039 cs->buf[cs->cdw++] =
1040 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
1041 RADEON_USAGE_WRITE);
1042
1043 /* R7xx requires this packet after updating BUFFER_BASE.
1044 * Without this, R7xx locks up. */
1045 if (ctx->family >= CHIP_RS780 && ctx->family <= CHIP_RV740) {
1046 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0);
1047 cs->buf[cs->cdw++] = i;
1048 cs->buf[cs->cdw++] = va >> 8;
1049
1050 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1051 cs->buf[cs->cdw++] =
1052 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
1053 RADEON_USAGE_WRITE);
1054 }
1055
1056 if (ctx->streamout_append_bitmask & (1 << i)) {
1057 va = r600_resource_va(&ctx->screen->screen,
1058 (void*)t[i]->filled_size);
1059 /* Append. */
1060 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1061 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1062 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
1063 cs->buf[cs->cdw++] = 0; /* unused */
1064 cs->buf[cs->cdw++] = 0; /* unused */
1065 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1066 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1067
1068 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1069 cs->buf[cs->cdw++] =
1070 r600_context_bo_reloc(ctx, t[i]->filled_size,
1071 RADEON_USAGE_READ);
1072 } else {
1073 /* Start from the beginning. */
1074 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1075 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1076 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
1077 cs->buf[cs->cdw++] = 0; /* unused */
1078 cs->buf[cs->cdw++] = 0; /* unused */
1079 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
1080 cs->buf[cs->cdw++] = 0; /* unused */
1081 }
1082 }
1083 }
1084
1085 if (ctx->family > CHIP_R600 && ctx->family < CHIP_RS780) {
1086 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
1087 cs->buf[cs->cdw++] = update_flags;
1088 }
1089 }
1090
1091 void r600_context_streamout_end(struct r600_context *ctx)
1092 {
1093 struct radeon_winsys_cs *cs = ctx->cs;
1094 struct r600_so_target **t = ctx->so_targets;
1095 unsigned i;
1096 uint64_t va;
1097
1098 if (ctx->chip_class >= EVERGREEN) {
1099 evergreen_flush_vgt_streamout(ctx);
1100 } else {
1101 r600_flush_vgt_streamout(ctx);
1102 }
1103
1104 for (i = 0; i < ctx->num_so_targets; i++) {
1105 if (t[i]) {
1106 va = r600_resource_va(&ctx->screen->screen,
1107 (void*)t[i]->filled_size);
1108 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1109 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1110 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
1111 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
1112 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* dst address lo */
1113 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* dst address hi */
1114 cs->buf[cs->cdw++] = 0; /* unused */
1115 cs->buf[cs->cdw++] = 0; /* unused */
1116
1117 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1118 cs->buf[cs->cdw++] =
1119 r600_context_bo_reloc(ctx, t[i]->filled_size,
1120 RADEON_USAGE_WRITE);
1121
1122 }
1123 }
1124
1125 if (ctx->chip_class >= EVERGREEN) {
1126 evergreen_set_streamout_enable(ctx, 0);
1127 } else {
1128 r600_set_streamout_enable(ctx, 0);
1129 }
1130 ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
1131
1132 /* R6xx errata */
1133 if (ctx->chip_class == R600) {
1134 ctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
1135 }
1136 ctx->num_cs_dw_streamout_end = 0;
1137 }