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winsys/radeon: consolidate tracing into winsys v2
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_pipe.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30 #include <unistd.h>
31
32 /* Get backends mask */
33 void r600_get_backend_mask(struct r600_context *ctx)
34 {
35 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
36 struct r600_resource *buffer;
37 uint32_t *results;
38 unsigned num_backends = ctx->screen->info.r600_num_backends;
39 unsigned i, mask = 0;
40 uint64_t va;
41
42 /* if backend_map query is supported by the kernel */
43 if (ctx->screen->info.r600_backend_map_valid) {
44 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
45 unsigned backend_map = ctx->screen->info.r600_backend_map;
46 unsigned item_width, item_mask;
47
48 if (ctx->chip_class >= EVERGREEN) {
49 item_width = 4;
50 item_mask = 0x7;
51 } else {
52 item_width = 2;
53 item_mask = 0x3;
54 }
55
56 while(num_tile_pipes--) {
57 i = backend_map & item_mask;
58 mask |= (1<<i);
59 backend_map >>= item_width;
60 }
61 if (mask != 0) {
62 ctx->backend_mask = mask;
63 return;
64 }
65 }
66
67 /* otherwise backup path for older kernels */
68
69 /* create buffer for event data */
70 buffer = (struct r600_resource*)
71 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
72 PIPE_USAGE_STAGING, ctx->max_db*16);
73 if (!buffer)
74 goto err;
75 va = r600_resource_va(&ctx->screen->screen, (void*)buffer);
76
77 /* initialize buffer with zeroes */
78 results = r600_buffer_mmap_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
79 if (results) {
80 memset(results, 0, ctx->max_db * 4 * 4);
81 ctx->ws->buffer_unmap(buffer->cs_buf);
82
83 /* emit EVENT_WRITE for ZPASS_DONE */
84 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
85 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
86 cs->buf[cs->cdw++] = va;
87 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
88
89 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
90 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, &ctx->rings.gfx, buffer, RADEON_USAGE_WRITE);
91
92 /* analyze results */
93 results = r600_buffer_mmap_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
94 if (results) {
95 for(i = 0; i < ctx->max_db; i++) {
96 /* at least highest bit will be set if backend is used */
97 if (results[i*4 + 1])
98 mask |= (1<<i);
99 }
100 ctx->ws->buffer_unmap(buffer->cs_buf);
101 }
102 }
103
104 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
105
106 if (mask != 0) {
107 ctx->backend_mask = mask;
108 return;
109 }
110
111 err:
112 /* fallback to old method - set num_backends lower bits to 1 */
113 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
114 return;
115 }
116
117 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
118 boolean count_draw_in)
119 {
120 if (!ctx->ws->cs_memory_below_limit(ctx->rings.gfx.cs, ctx->vram, ctx->gtt)) {
121 ctx->gtt = 0;
122 ctx->vram = 0;
123 ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
124 return;
125 }
126 /* all will be accounted once relocation are emited */
127 ctx->gtt = 0;
128 ctx->vram = 0;
129
130 /* The number of dwords we already used in the CS so far. */
131 num_dw += ctx->rings.gfx.cs->cdw;
132
133 if (count_draw_in) {
134 unsigned i;
135
136 /* The number of dwords all the dirty states would take. */
137 for (i = 0; i < R600_NUM_ATOMS; i++) {
138 if (ctx->atoms[i] && ctx->atoms[i]->dirty) {
139 num_dw += ctx->atoms[i]->num_dw;
140 if (ctx->screen->trace_bo) {
141 num_dw += R600_TRACE_CS_DWORDS;
142 }
143 }
144 }
145
146 /* The upper-bound of how much space a draw command would take. */
147 num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
148 if (ctx->screen->trace_bo) {
149 num_dw += R600_TRACE_CS_DWORDS;
150 }
151 }
152
153 /* Count in queries_suspend. */
154 num_dw += ctx->num_cs_dw_nontimer_queries_suspend;
155
156 /* Count in streamout_end at the end of CS. */
157 if (ctx->streamout.begin_emitted) {
158 num_dw += ctx->streamout.num_dw_for_end;
159 }
160
161 /* Count in render_condition(NULL) at the end of CS. */
162 if (ctx->predicate_drawing) {
163 num_dw += 3;
164 }
165
166 /* SX_MISC */
167 if (ctx->chip_class <= R700) {
168 num_dw += 3;
169 }
170
171 /* Count in framebuffer cache flushes at the end of CS. */
172 num_dw += R600_MAX_FLUSH_CS_DWORDS;
173
174 /* The fence at the end of CS. */
175 num_dw += 10;
176
177 /* Flush if there's not enough space. */
178 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
179 ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
180 }
181 }
182
183 void r600_flush_emit(struct r600_context *rctx)
184 {
185 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
186 unsigned cp_coher_cntl = 0;
187 unsigned wait_until = 0;
188 unsigned emit_flush = 0;
189
190 if (!rctx->flags) {
191 return;
192 }
193
194 if (rctx->flags & R600_CONTEXT_WAIT_3D_IDLE) {
195 wait_until |= S_008040_WAIT_3D_IDLE(1);
196 }
197 if (rctx->flags & R600_CONTEXT_WAIT_CP_DMA_IDLE) {
198 wait_until |= S_008040_WAIT_CP_DMA_IDLE(1);
199 }
200
201 if (wait_until) {
202 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
203 if (rctx->family >= CHIP_CAYMAN) {
204 /* emit a PS partial flush on Cayman/TN */
205 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
206 }
207 }
208
209 if (rctx->flags & R600_CONTEXT_PS_PARTIAL_FLUSH) {
210 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
211 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
212 }
213
214 if (rctx->chip_class >= R700 &&
215 (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
216 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
217 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0);
218 }
219
220 if (rctx->chip_class >= R700 &&
221 (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META)) {
222 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
223 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0);
224 }
225
226 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) {
227 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
228 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
229 if (rctx->chip_class >= EVERGREEN) {
230 cp_coher_cntl = S_0085F0_CB0_DEST_BASE_ENA(1) |
231 S_0085F0_CB1_DEST_BASE_ENA(1) |
232 S_0085F0_CB2_DEST_BASE_ENA(1) |
233 S_0085F0_CB3_DEST_BASE_ENA(1) |
234 S_0085F0_CB4_DEST_BASE_ENA(1) |
235 S_0085F0_CB5_DEST_BASE_ENA(1) |
236 S_0085F0_CB6_DEST_BASE_ENA(1) |
237 S_0085F0_CB7_DEST_BASE_ENA(1) |
238 S_0085F0_CB8_DEST_BASE_ENA(1) |
239 S_0085F0_CB9_DEST_BASE_ENA(1) |
240 S_0085F0_CB10_DEST_BASE_ENA(1) |
241 S_0085F0_CB11_DEST_BASE_ENA(1) |
242 S_0085F0_DB_DEST_BASE_ENA(1) |
243 S_0085F0_TC_ACTION_ENA(1) |
244 S_0085F0_CB_ACTION_ENA(1) |
245 S_0085F0_DB_ACTION_ENA(1) |
246 S_0085F0_SH_ACTION_ENA(1) |
247 S_0085F0_SMX_ACTION_ENA(1) |
248 S_0085F0_FULL_CACHE_ENA(1);
249 } else {
250 cp_coher_cntl = S_0085F0_SMX_ACTION_ENA(1) |
251 S_0085F0_SH_ACTION_ENA(1) |
252 S_0085F0_VC_ACTION_ENA(1) |
253 S_0085F0_TC_ACTION_ENA(1) |
254 S_0085F0_FULL_CACHE_ENA(1);
255 }
256 emit_flush = 1;
257 }
258
259 if (rctx->flags & R600_CONTEXT_INVAL_READ_CACHES) {
260 cp_coher_cntl |= S_0085F0_VC_ACTION_ENA(1) |
261 S_0085F0_TC_ACTION_ENA(1) |
262 S_0085F0_FULL_CACHE_ENA(1);
263 emit_flush = 1;
264 }
265
266 if (rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
267 cp_coher_cntl |= S_0085F0_SO0_DEST_BASE_ENA(1) |
268 S_0085F0_SO1_DEST_BASE_ENA(1) |
269 S_0085F0_SO2_DEST_BASE_ENA(1) |
270 S_0085F0_SO3_DEST_BASE_ENA(1) |
271 S_0085F0_SMX_ACTION_ENA(1);
272 emit_flush = 1;
273 }
274
275 if (emit_flush) {
276 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
277 cs->buf[cs->cdw++] = cp_coher_cntl; /* CP_COHER_CNTL */
278 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
279 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
280 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
281 }
282
283 if (wait_until) {
284 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
285 if (rctx->family < CHIP_CAYMAN) {
286 /* wait for things to settle */
287 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, wait_until);
288 }
289 }
290
291 /* everything is properly flushed */
292 rctx->flags = 0;
293 }
294
295 void r600_context_flush(struct r600_context *ctx, unsigned flags)
296 {
297 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
298
299 if (cs->cdw == ctx->start_cs_cmd.num_dw)
300 return;
301
302 ctx->nontimer_queries_suspended = false;
303 ctx->streamout.suspended = false;
304
305 /* suspend queries */
306 if (ctx->num_cs_dw_nontimer_queries_suspend) {
307 r600_suspend_nontimer_queries(ctx);
308 ctx->nontimer_queries_suspended = true;
309 }
310
311 if (ctx->streamout.begin_emitted) {
312 r600_emit_streamout_end(ctx);
313 ctx->streamout.suspended = true;
314 }
315
316 /* flush is needed to avoid lockups on some chips with user fences
317 * this will also flush the framebuffer cache
318 */
319 ctx->flags |= R600_CONTEXT_FLUSH_AND_INV |
320 R600_CONTEXT_FLUSH_AND_INV_CB_META |
321 R600_CONTEXT_FLUSH_AND_INV_DB_META |
322 R600_CONTEXT_WAIT_3D_IDLE |
323 R600_CONTEXT_WAIT_CP_DMA_IDLE;
324
325 r600_flush_emit(ctx);
326
327 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
328 if (ctx->chip_class <= R700) {
329 r600_write_context_reg(cs, R_028350_SX_MISC, 0);
330 }
331
332 /* force to keep tiling flags */
333 if (ctx->keep_tiling_flags) {
334 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
335 }
336
337 /* Flush the CS. */
338 ctx->ws->cs_flush(ctx->rings.gfx.cs, flags, ctx->screen->cs_count++);
339 }
340
341 void r600_begin_new_cs(struct r600_context *ctx)
342 {
343 unsigned shader;
344
345 ctx->flags = 0;
346 ctx->gtt = 0;
347 ctx->vram = 0;
348
349 /* Begin a new CS. */
350 r600_emit_command_buffer(ctx->rings.gfx.cs, &ctx->start_cs_cmd);
351
352 /* Re-emit states. */
353 ctx->alphatest_state.atom.dirty = true;
354 ctx->blend_color.atom.dirty = true;
355 ctx->cb_misc_state.atom.dirty = true;
356 ctx->clip_misc_state.atom.dirty = true;
357 ctx->clip_state.atom.dirty = true;
358 ctx->db_misc_state.atom.dirty = true;
359 ctx->db_state.atom.dirty = true;
360 ctx->framebuffer.atom.dirty = true;
361 ctx->pixel_shader.atom.dirty = true;
362 ctx->poly_offset_state.atom.dirty = true;
363 ctx->vgt_state.atom.dirty = true;
364 ctx->sample_mask.atom.dirty = true;
365 ctx->scissor.atom.dirty = true;
366 ctx->config_state.atom.dirty = true;
367 ctx->stencil_ref.atom.dirty = true;
368 ctx->vertex_fetch_shader.atom.dirty = true;
369 ctx->vertex_shader.atom.dirty = true;
370 ctx->viewport.atom.dirty = true;
371
372 if (ctx->blend_state.cso)
373 ctx->blend_state.atom.dirty = true;
374 if (ctx->dsa_state.cso)
375 ctx->dsa_state.atom.dirty = true;
376 if (ctx->rasterizer_state.cso)
377 ctx->rasterizer_state.atom.dirty = true;
378
379 if (ctx->chip_class <= R700) {
380 ctx->seamless_cube_map.atom.dirty = true;
381 }
382
383 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
384 r600_vertex_buffers_dirty(ctx);
385
386 /* Re-emit shader resources. */
387 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
388 struct r600_constbuf_state *constbuf = &ctx->constbuf_state[shader];
389 struct r600_textures_info *samplers = &ctx->samplers[shader];
390
391 constbuf->dirty_mask = constbuf->enabled_mask;
392 samplers->views.dirty_mask = samplers->views.enabled_mask;
393 samplers->states.dirty_mask = samplers->states.enabled_mask;
394
395 r600_constant_buffers_dirty(ctx, constbuf);
396 r600_sampler_views_dirty(ctx, &samplers->views);
397 r600_sampler_states_dirty(ctx, &samplers->states);
398 }
399
400 if (ctx->streamout.suspended) {
401 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
402 r600_streamout_buffers_dirty(ctx);
403 }
404
405 /* resume queries */
406 if (ctx->nontimer_queries_suspended) {
407 r600_resume_nontimer_queries(ctx);
408 }
409
410 /* Re-emit the draw state. */
411 ctx->last_primitive_type = -1;
412 ctx->last_start_instance = -1;
413 }
414
415 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
416 {
417 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
418 uint64_t va;
419
420 r600_need_cs_space(ctx, 10, FALSE);
421
422 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
423 va = va + (offset << 2);
424
425 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
426 if (ctx->family >= CHIP_CAYMAN) {
427 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
428 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
429 } else {
430 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
431 }
432
433 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
434 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
435 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */
436 /* DATA_SEL | INT_EN | ADDRESS_HI */
437 cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF);
438 cs->buf[cs->cdw++] = value; /* DATA_LO */
439 cs->buf[cs->cdw++] = 0; /* DATA_HI */
440 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
441 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, &ctx->rings.gfx, fence_bo, RADEON_USAGE_WRITE);
442 }
443
444 static void r600_flush_vgt_streamout(struct r600_context *ctx)
445 {
446 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
447
448 r600_write_config_reg(cs, R_008490_CP_STRMOUT_CNTL, 0);
449
450 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
451 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
452
453 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
454 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
455 cs->buf[cs->cdw++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */
456 cs->buf[cs->cdw++] = 0;
457 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */
458 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */
459 cs->buf[cs->cdw++] = 4; /* poll interval */
460 }
461
462 static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
463 {
464 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
465
466 if (buffer_enable_bit) {
467 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(1));
468 r600_write_context_reg(cs, R_028B20_VGT_STRMOUT_BUFFER_EN, buffer_enable_bit);
469 } else {
470 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(0));
471 }
472 }
473
474 void r600_emit_streamout_begin(struct r600_context *ctx, struct r600_atom *atom)
475 {
476 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
477 struct r600_so_target **t = ctx->streamout.targets;
478 unsigned *stride_in_dw = ctx->vs_shader->so.stride;
479 unsigned i, update_flags = 0;
480 uint64_t va;
481
482 if (ctx->chip_class >= EVERGREEN) {
483 evergreen_flush_vgt_streamout(ctx);
484 evergreen_set_streamout_enable(ctx, ctx->streamout.enabled_mask);
485 } else {
486 r600_flush_vgt_streamout(ctx);
487 r600_set_streamout_enable(ctx, ctx->streamout.enabled_mask);
488 }
489
490 for (i = 0; i < ctx->streamout.num_targets; i++) {
491 if (t[i]) {
492 t[i]->stride_in_dw = stride_in_dw[i];
493 t[i]->so_index = i;
494 va = r600_resource_va(&ctx->screen->screen,
495 (void*)t[i]->b.buffer);
496
497 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
498
499 r600_write_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
500 r600_write_value(cs, (t[i]->b.buffer_offset +
501 t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
502 r600_write_value(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
503 r600_write_value(cs, va >> 8); /* BUFFER_BASE */
504
505 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
506 cs->buf[cs->cdw++] =
507 r600_context_bo_reloc(ctx, &ctx->rings.gfx, r600_resource(t[i]->b.buffer),
508 RADEON_USAGE_WRITE);
509
510 /* R7xx requires this packet after updating BUFFER_BASE.
511 * Without this, R7xx locks up. */
512 if (ctx->family >= CHIP_RS780 && ctx->family <= CHIP_RV740) {
513 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0);
514 cs->buf[cs->cdw++] = i;
515 cs->buf[cs->cdw++] = va >> 8;
516
517 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
518 cs->buf[cs->cdw++] =
519 r600_context_bo_reloc(ctx, &ctx->rings.gfx, r600_resource(t[i]->b.buffer),
520 RADEON_USAGE_WRITE);
521 }
522
523 if (ctx->streamout.append_bitmask & (1 << i)) {
524 va = r600_resource_va(&ctx->screen->screen,
525 (void*)t[i]->buf_filled_size) + t[i]->buf_filled_size_offset;
526 /* Append. */
527 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
528 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
529 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
530 cs->buf[cs->cdw++] = 0; /* unused */
531 cs->buf[cs->cdw++] = 0; /* unused */
532 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
533 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
534
535 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
536 cs->buf[cs->cdw++] =
537 r600_context_bo_reloc(ctx, &ctx->rings.gfx, t[i]->buf_filled_size,
538 RADEON_USAGE_READ);
539 } else {
540 /* Start from the beginning. */
541 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
542 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
543 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
544 cs->buf[cs->cdw++] = 0; /* unused */
545 cs->buf[cs->cdw++] = 0; /* unused */
546 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
547 cs->buf[cs->cdw++] = 0; /* unused */
548 }
549 }
550 }
551
552 if (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770) {
553 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
554 cs->buf[cs->cdw++] = update_flags;
555 }
556 ctx->streamout.begin_emitted = true;
557 }
558
559 void r600_emit_streamout_end(struct r600_context *ctx)
560 {
561 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
562 struct r600_so_target **t = ctx->streamout.targets;
563 unsigned i;
564 uint64_t va;
565
566 if (ctx->chip_class >= EVERGREEN) {
567 evergreen_flush_vgt_streamout(ctx);
568 } else {
569 r600_flush_vgt_streamout(ctx);
570 }
571
572 for (i = 0; i < ctx->streamout.num_targets; i++) {
573 if (t[i]) {
574 va = r600_resource_va(&ctx->screen->screen,
575 (void*)t[i]->buf_filled_size) + t[i]->buf_filled_size_offset;
576 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
577 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
578 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
579 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
580 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* dst address lo */
581 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* dst address hi */
582 cs->buf[cs->cdw++] = 0; /* unused */
583 cs->buf[cs->cdw++] = 0; /* unused */
584
585 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
586 cs->buf[cs->cdw++] =
587 r600_context_bo_reloc(ctx, &ctx->rings.gfx, t[i]->buf_filled_size,
588 RADEON_USAGE_WRITE);
589 }
590 }
591
592 if (ctx->chip_class >= EVERGREEN) {
593 ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
594 evergreen_set_streamout_enable(ctx, 0);
595 } else {
596 if (ctx->chip_class >= R700) {
597 ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
598 }
599 r600_set_streamout_enable(ctx, 0);
600 }
601 ctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
602 ctx->streamout.begin_emitted = false;
603 }
604
605 /* The max number of bytes to copy per packet. */
606 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
607
608 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
609 struct pipe_resource *dst, uint64_t dst_offset,
610 struct pipe_resource *src, uint64_t src_offset,
611 unsigned size)
612 {
613 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
614
615 assert(size);
616 assert(rctx->screen->has_cp_dma);
617
618 dst_offset += r600_resource_va(&rctx->screen->screen, dst);
619 src_offset += r600_resource_va(&rctx->screen->screen, src);
620
621 /* We flush the caches, because we might read from or write
622 * to resources which are bound right now. */
623 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES |
624 R600_CONTEXT_FLUSH_AND_INV |
625 R600_CONTEXT_FLUSH_AND_INV_CB_META |
626 R600_CONTEXT_FLUSH_AND_INV_DB_META |
627 R600_CONTEXT_STREAMOUT_FLUSH |
628 R600_CONTEXT_WAIT_3D_IDLE;
629
630 /* There are differences between R700 and EG in CP DMA,
631 * but we only use the common bits here. */
632 while (size) {
633 unsigned sync = 0;
634 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
635 unsigned src_reloc, dst_reloc;
636
637 r600_need_cs_space(rctx, 10 + (rctx->flags ? R600_MAX_FLUSH_CS_DWORDS : 0), FALSE);
638
639 /* Flush the caches for the first copy only. */
640 if (rctx->flags) {
641 r600_flush_emit(rctx);
642 }
643
644 /* Do the synchronization after the last copy, so that all data is written to memory. */
645 if (size == byte_count) {
646 sync = PKT3_CP_DMA_CP_SYNC;
647 }
648
649 /* This must be done after r600_need_cs_space. */
650 src_reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)src, RADEON_USAGE_READ);
651 dst_reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)dst, RADEON_USAGE_WRITE);
652
653 r600_write_value(cs, PKT3(PKT3_CP_DMA, 4, 0));
654 r600_write_value(cs, src_offset); /* SRC_ADDR_LO [31:0] */
655 r600_write_value(cs, sync | ((src_offset >> 32) & 0xff)); /* CP_SYNC [31] | SRC_ADDR_HI [7:0] */
656 r600_write_value(cs, dst_offset); /* DST_ADDR_LO [31:0] */
657 r600_write_value(cs, (dst_offset >> 32) & 0xff); /* DST_ADDR_HI [7:0] */
658 r600_write_value(cs, byte_count); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
659
660 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
661 r600_write_value(cs, src_reloc);
662 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
663 r600_write_value(cs, dst_reloc);
664
665 size -= byte_count;
666 src_offset += byte_count;
667 dst_offset += byte_count;
668 }
669
670 /* Invalidate the read caches. */
671 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
672
673 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
674 dst_offset + size);
675 }
676
677 void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw)
678 {
679 /* The number of dwords we already used in the DMA so far. */
680 num_dw += ctx->rings.dma.cs->cdw;
681 /* Flush if there's not enough space. */
682 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
683 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
684 }
685 }
686
687 void r600_dma_copy(struct r600_context *rctx,
688 struct pipe_resource *dst,
689 struct pipe_resource *src,
690 uint64_t dst_offset,
691 uint64_t src_offset,
692 uint64_t size)
693 {
694 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
695 unsigned i, ncopy, csize, shift;
696 struct r600_resource *rdst = (struct r600_resource*)dst;
697 struct r600_resource *rsrc = (struct r600_resource*)src;
698
699 /* make sure that the dma ring is only one active */
700 rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
701
702 size >>= 2;
703 shift = 2;
704 ncopy = (size / 0xffff) + !!(size % 0xffff);
705
706 r600_need_dma_space(rctx, ncopy * 5);
707 for (i = 0; i < ncopy; i++) {
708 csize = size < 0xffff ? size : 0xffff;
709 /* emit reloc before writting cs so that cs is always in consistent state */
710 r600_context_bo_reloc(rctx, &rctx->rings.dma, rsrc, RADEON_USAGE_READ);
711 r600_context_bo_reloc(rctx, &rctx->rings.dma, rdst, RADEON_USAGE_WRITE);
712 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 0, 0, csize);
713 cs->buf[cs->cdw++] = dst_offset & 0xfffffffc;
714 cs->buf[cs->cdw++] = src_offset & 0xfffffffc;
715 cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xff;
716 cs->buf[cs->cdw++] = (src_offset >> 32UL) & 0xff;
717 dst_offset += csize << shift;
718 src_offset += csize << shift;
719 size -= csize;
720 }
721
722 util_range_add(&rdst->valid_buffer_range, dst_offset,
723 dst_offset + size);
724 }