2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "r600_pipe.h"
28 #include "util/u_memory.h"
32 /* Get backends mask */
33 void r600_get_backend_mask(struct r600_context
*ctx
)
35 struct radeon_winsys_cs
*cs
= ctx
->b
.rings
.gfx
.cs
;
36 struct r600_resource
*buffer
;
38 unsigned num_backends
= ctx
->screen
->b
.info
.r600_num_backends
;
42 /* if backend_map query is supported by the kernel */
43 if (ctx
->screen
->b
.info
.r600_backend_map_valid
) {
44 unsigned num_tile_pipes
= ctx
->screen
->b
.info
.r600_num_tile_pipes
;
45 unsigned backend_map
= ctx
->screen
->b
.info
.r600_backend_map
;
46 unsigned item_width
, item_mask
;
48 if (ctx
->b
.chip_class
>= EVERGREEN
) {
56 while(num_tile_pipes
--) {
57 i
= backend_map
& item_mask
;
59 backend_map
>>= item_width
;
62 ctx
->backend_mask
= mask
;
67 /* otherwise backup path for older kernels */
69 /* create buffer for event data */
70 buffer
= (struct r600_resource
*)
71 pipe_buffer_create(&ctx
->screen
->b
.b
, PIPE_BIND_CUSTOM
,
72 PIPE_USAGE_STAGING
, ctx
->max_db
*16);
75 va
= r600_resource_va(&ctx
->screen
->b
.b
, (void*)buffer
);
77 /* initialize buffer with zeroes */
78 results
= r600_buffer_map_sync_with_rings(&ctx
->b
, buffer
, PIPE_TRANSFER_WRITE
);
80 memset(results
, 0, ctx
->max_db
* 4 * 4);
81 ctx
->b
.ws
->buffer_unmap(buffer
->cs_buf
);
83 /* emit EVENT_WRITE for ZPASS_DONE */
84 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE
, 2, 0);
85 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1);
86 cs
->buf
[cs
->cdw
++] = va
;
87 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
89 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
90 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&ctx
->b
, &ctx
->b
.rings
.gfx
, buffer
, RADEON_USAGE_WRITE
);
93 results
= r600_buffer_map_sync_with_rings(&ctx
->b
, buffer
, PIPE_TRANSFER_READ
);
95 for(i
= 0; i
< ctx
->max_db
; i
++) {
96 /* at least highest bit will be set if backend is used */
100 ctx
->b
.ws
->buffer_unmap(buffer
->cs_buf
);
104 pipe_resource_reference((struct pipe_resource
**)&buffer
, NULL
);
107 ctx
->backend_mask
= mask
;
112 /* fallback to old method - set num_backends lower bits to 1 */
113 ctx
->backend_mask
= (~((uint32_t)0))>>(32-num_backends
);
117 void r600_need_cs_space(struct r600_context
*ctx
, unsigned num_dw
,
118 boolean count_draw_in
)
120 if (!ctx
->b
.ws
->cs_memory_below_limit(ctx
->b
.rings
.gfx
.cs
, ctx
->b
.vram
, ctx
->b
.gtt
)) {
123 ctx
->b
.rings
.gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
);
126 /* all will be accounted once relocation are emited */
130 /* The number of dwords we already used in the CS so far. */
131 num_dw
+= ctx
->b
.rings
.gfx
.cs
->cdw
;
136 /* The number of dwords all the dirty states would take. */
137 for (i
= 0; i
< R600_NUM_ATOMS
; i
++) {
138 if (ctx
->atoms
[i
] && ctx
->atoms
[i
]->dirty
) {
139 num_dw
+= ctx
->atoms
[i
]->num_dw
;
140 if (ctx
->screen
->trace_bo
) {
141 num_dw
+= R600_TRACE_CS_DWORDS
;
146 /* The upper-bound of how much space a draw command would take. */
147 num_dw
+= R600_MAX_FLUSH_CS_DWORDS
+ R600_MAX_DRAW_CS_DWORDS
;
148 if (ctx
->screen
->trace_bo
) {
149 num_dw
+= R600_TRACE_CS_DWORDS
;
153 /* Count in queries_suspend. */
154 num_dw
+= ctx
->num_cs_dw_nontimer_queries_suspend
;
156 /* Count in streamout_end at the end of CS. */
157 if (ctx
->b
.streamout
.begin_emitted
) {
158 num_dw
+= ctx
->b
.streamout
.num_dw_for_end
;
161 /* Count in render_condition(NULL) at the end of CS. */
162 if (ctx
->predicate_drawing
) {
167 if (ctx
->b
.chip_class
<= R700
) {
171 /* Count in framebuffer cache flushes at the end of CS. */
172 num_dw
+= R600_MAX_FLUSH_CS_DWORDS
;
174 /* The fence at the end of CS. */
177 /* Flush if there's not enough space. */
178 if (num_dw
> RADEON_MAX_CMDBUF_DWORDS
) {
179 ctx
->b
.rings
.gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
);
183 void r600_flush_emit(struct r600_context
*rctx
)
185 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
186 unsigned cp_coher_cntl
= 0;
187 unsigned wait_until
= 0;
189 if (!rctx
->b
.flags
) {
193 if (rctx
->b
.flags
& R600_CONTEXT_WAIT_3D_IDLE
) {
194 wait_until
|= S_008040_WAIT_3D_IDLE(1);
196 if (rctx
->b
.flags
& R600_CONTEXT_WAIT_CP_DMA_IDLE
) {
197 wait_until
|= S_008040_WAIT_CP_DMA_IDLE(1);
201 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
202 if (rctx
->b
.family
>= CHIP_CAYMAN
) {
203 /* emit a PS partial flush on Cayman/TN */
204 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
208 if (rctx
->b
.flags
& R600_CONTEXT_PS_PARTIAL_FLUSH
) {
209 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
210 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4);
213 if (rctx
->b
.chip_class
>= R700
&&
214 (rctx
->b
.flags
& R600_CONTEXT_FLUSH_AND_INV_CB_META
)) {
215 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
216 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0);
219 if (rctx
->b
.chip_class
>= R700
&&
220 (rctx
->b
.flags
& R600_CONTEXT_FLUSH_AND_INV_DB_META
)) {
221 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
222 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0);
224 /* Set FULL_CACHE_ENA for DB META flushes on r7xx and later.
226 * This hack predates use of FLUSH_AND_INV_DB_META, so it's
227 * unclear whether it's still needed or even whether it has
230 cp_coher_cntl
|= S_0085F0_FULL_CACHE_ENA(1);
233 if (rctx
->b
.flags
& R600_CONTEXT_FLUSH_AND_INV
) {
234 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
235 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT
) | EVENT_INDEX(0);
238 if (rctx
->b
.flags
& R600_CONTEXT_INV_CONST_CACHE
) {
239 /* Direct constant addressing uses the shader cache.
240 * Indirect contant addressing uses the vertex cache. */
241 cp_coher_cntl
|= S_0085F0_SH_ACTION_ENA(1) |
242 (rctx
->has_vertex_cache
? S_0085F0_VC_ACTION_ENA(1)
243 : S_0085F0_TC_ACTION_ENA(1));
245 if (rctx
->b
.flags
& R600_CONTEXT_INV_VERTEX_CACHE
) {
246 cp_coher_cntl
|= rctx
->has_vertex_cache
? S_0085F0_VC_ACTION_ENA(1)
247 : S_0085F0_TC_ACTION_ENA(1);
249 if (rctx
->b
.flags
& R600_CONTEXT_INV_TEX_CACHE
) {
250 /* Textures use the texture cache.
251 * Texture buffer objects use the vertex cache. */
252 cp_coher_cntl
|= S_0085F0_TC_ACTION_ENA(1) |
253 (rctx
->has_vertex_cache
? S_0085F0_VC_ACTION_ENA(1) : 0);
256 /* Don't use the DB CP COHER logic on r6xx.
259 if (rctx
->b
.chip_class
>= R700
&&
260 (rctx
->b
.flags
& R600_CONTEXT_FLUSH_AND_INV_DB
)) {
261 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
262 S_0085F0_DB_DEST_BASE_ENA(1) |
263 S_0085F0_SMX_ACTION_ENA(1);
266 /* Don't use the CB CP COHER logic on r6xx.
269 if (rctx
->b
.chip_class
>= R700
&&
270 (rctx
->b
.flags
& R600_CONTEXT_FLUSH_AND_INV_CB
)) {
271 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
272 S_0085F0_CB0_DEST_BASE_ENA(1) |
273 S_0085F0_CB1_DEST_BASE_ENA(1) |
274 S_0085F0_CB2_DEST_BASE_ENA(1) |
275 S_0085F0_CB3_DEST_BASE_ENA(1) |
276 S_0085F0_CB4_DEST_BASE_ENA(1) |
277 S_0085F0_CB5_DEST_BASE_ENA(1) |
278 S_0085F0_CB6_DEST_BASE_ENA(1) |
279 S_0085F0_CB7_DEST_BASE_ENA(1) |
280 S_0085F0_SMX_ACTION_ENA(1);
281 if (rctx
->b
.chip_class
>= EVERGREEN
)
282 cp_coher_cntl
|= S_0085F0_CB8_DEST_BASE_ENA(1) |
283 S_0085F0_CB9_DEST_BASE_ENA(1) |
284 S_0085F0_CB10_DEST_BASE_ENA(1) |
285 S_0085F0_CB11_DEST_BASE_ENA(1);
288 if (rctx
->b
.flags
& R600_CONTEXT_STREAMOUT_FLUSH
) {
289 cp_coher_cntl
|= S_0085F0_SO0_DEST_BASE_ENA(1) |
290 S_0085F0_SO1_DEST_BASE_ENA(1) |
291 S_0085F0_SO2_DEST_BASE_ENA(1) |
292 S_0085F0_SO3_DEST_BASE_ENA(1) |
293 S_0085F0_SMX_ACTION_ENA(1);
296 if (cp_coher_cntl
&& !rctx
->skip_surface_sync_on_next_cs_flush
) {
297 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SURFACE_SYNC
, 3, 0);
298 cs
->buf
[cs
->cdw
++] = cp_coher_cntl
; /* CP_COHER_CNTL */
299 cs
->buf
[cs
->cdw
++] = 0xffffffff; /* CP_COHER_SIZE */
300 cs
->buf
[cs
->cdw
++] = 0; /* CP_COHER_BASE */
301 cs
->buf
[cs
->cdw
++] = 0x0000000A; /* POLL_INTERVAL */
305 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
306 if (rctx
->b
.family
< CHIP_CAYMAN
) {
307 /* wait for things to settle */
308 r600_write_config_reg(cs
, R_008040_WAIT_UNTIL
, wait_until
);
312 /* everything is properly flushed */
316 void r600_context_flush(struct r600_context
*ctx
, unsigned flags
)
318 struct radeon_winsys_cs
*cs
= ctx
->b
.rings
.gfx
.cs
;
320 ctx
->nontimer_queries_suspended
= false;
321 ctx
->b
.streamout
.suspended
= false;
323 /* suspend queries */
324 if (ctx
->num_cs_dw_nontimer_queries_suspend
) {
325 r600_suspend_nontimer_queries(ctx
);
326 ctx
->nontimer_queries_suspended
= true;
329 if (ctx
->b
.streamout
.begin_emitted
) {
330 r600_emit_streamout_end(&ctx
->b
);
331 ctx
->b
.streamout
.suspended
= true;
334 /* flush the framebuffer cache */
335 ctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV
|
336 R600_CONTEXT_FLUSH_AND_INV_CB
|
337 R600_CONTEXT_FLUSH_AND_INV_DB
|
338 R600_CONTEXT_FLUSH_AND_INV_CB_META
|
339 R600_CONTEXT_FLUSH_AND_INV_DB_META
|
340 R600_CONTEXT_WAIT_3D_IDLE
|
341 R600_CONTEXT_WAIT_CP_DMA_IDLE
;
343 r600_flush_emit(ctx
);
345 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
346 if (ctx
->b
.chip_class
<= R700
) {
347 r600_write_context_reg(cs
, R_028350_SX_MISC
, 0);
350 /* force to keep tiling flags */
351 if (ctx
->keep_tiling_flags
) {
352 flags
|= RADEON_FLUSH_KEEP_TILING_FLAGS
;
356 ctx
->b
.ws
->cs_flush(ctx
->b
.rings
.gfx
.cs
, flags
, ctx
->screen
->cs_count
++);
358 ctx
->skip_surface_sync_on_next_cs_flush
= false;
361 void r600_begin_new_cs(struct r600_context
*ctx
)
369 /* Begin a new CS. */
370 r600_emit_command_buffer(ctx
->b
.rings
.gfx
.cs
, &ctx
->start_cs_cmd
);
372 /* Re-emit states. */
373 ctx
->alphatest_state
.atom
.dirty
= true;
374 ctx
->blend_color
.atom
.dirty
= true;
375 ctx
->cb_misc_state
.atom
.dirty
= true;
376 ctx
->clip_misc_state
.atom
.dirty
= true;
377 ctx
->clip_state
.atom
.dirty
= true;
378 ctx
->db_misc_state
.atom
.dirty
= true;
379 ctx
->db_state
.atom
.dirty
= true;
380 ctx
->framebuffer
.atom
.dirty
= true;
381 ctx
->pixel_shader
.atom
.dirty
= true;
382 ctx
->poly_offset_state
.atom
.dirty
= true;
383 ctx
->vgt_state
.atom
.dirty
= true;
384 ctx
->sample_mask
.atom
.dirty
= true;
385 ctx
->scissor
.atom
.dirty
= true;
386 ctx
->config_state
.atom
.dirty
= true;
387 ctx
->stencil_ref
.atom
.dirty
= true;
388 ctx
->vertex_fetch_shader
.atom
.dirty
= true;
389 ctx
->vertex_shader
.atom
.dirty
= true;
390 ctx
->viewport
.atom
.dirty
= true;
392 if (ctx
->blend_state
.cso
)
393 ctx
->blend_state
.atom
.dirty
= true;
394 if (ctx
->dsa_state
.cso
)
395 ctx
->dsa_state
.atom
.dirty
= true;
396 if (ctx
->rasterizer_state
.cso
)
397 ctx
->rasterizer_state
.atom
.dirty
= true;
399 if (ctx
->b
.chip_class
<= R700
) {
400 ctx
->seamless_cube_map
.atom
.dirty
= true;
403 ctx
->vertex_buffer_state
.dirty_mask
= ctx
->vertex_buffer_state
.enabled_mask
;
404 r600_vertex_buffers_dirty(ctx
);
406 /* Re-emit shader resources. */
407 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
408 struct r600_constbuf_state
*constbuf
= &ctx
->constbuf_state
[shader
];
409 struct r600_textures_info
*samplers
= &ctx
->samplers
[shader
];
411 constbuf
->dirty_mask
= constbuf
->enabled_mask
;
412 samplers
->views
.dirty_mask
= samplers
->views
.enabled_mask
;
413 samplers
->states
.dirty_mask
= samplers
->states
.enabled_mask
;
415 r600_constant_buffers_dirty(ctx
, constbuf
);
416 r600_sampler_views_dirty(ctx
, &samplers
->views
);
417 r600_sampler_states_dirty(ctx
, &samplers
->states
);
420 if (ctx
->b
.streamout
.suspended
) {
421 ctx
->b
.streamout
.append_bitmask
= ctx
->b
.streamout
.enabled_mask
;
422 r600_streamout_buffers_dirty(&ctx
->b
);
426 if (ctx
->nontimer_queries_suspended
) {
427 r600_resume_nontimer_queries(ctx
);
430 /* Re-emit the draw state. */
431 ctx
->last_primitive_type
= -1;
432 ctx
->last_start_instance
= -1;
434 ctx
->initial_gfx_cs_size
= ctx
->b
.rings
.gfx
.cs
->cdw
;
437 /* The max number of bytes to copy per packet. */
438 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
440 void r600_cp_dma_copy_buffer(struct r600_context
*rctx
,
441 struct pipe_resource
*dst
, uint64_t dst_offset
,
442 struct pipe_resource
*src
, uint64_t src_offset
,
445 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
448 assert(rctx
->screen
->b
.has_cp_dma
);
450 dst_offset
+= r600_resource_va(&rctx
->screen
->b
.b
, dst
);
451 src_offset
+= r600_resource_va(&rctx
->screen
->b
.b
, src
);
453 /* Flush the caches where the resources are bound. */
454 rctx
->b
.flags
|= R600_CONTEXT_INV_CONST_CACHE
|
455 R600_CONTEXT_INV_VERTEX_CACHE
|
456 R600_CONTEXT_INV_TEX_CACHE
|
457 R600_CONTEXT_FLUSH_AND_INV
|
458 R600_CONTEXT_FLUSH_AND_INV_CB
|
459 R600_CONTEXT_FLUSH_AND_INV_DB
|
460 R600_CONTEXT_FLUSH_AND_INV_CB_META
|
461 R600_CONTEXT_FLUSH_AND_INV_DB_META
|
462 R600_CONTEXT_STREAMOUT_FLUSH
|
463 R600_CONTEXT_WAIT_3D_IDLE
;
465 /* There are differences between R700 and EG in CP DMA,
466 * but we only use the common bits here. */
469 unsigned byte_count
= MIN2(size
, CP_DMA_MAX_BYTE_COUNT
);
470 unsigned src_reloc
, dst_reloc
;
472 r600_need_cs_space(rctx
, 10 + (rctx
->b
.flags
? R600_MAX_FLUSH_CS_DWORDS
: 0), FALSE
);
474 /* Flush the caches for the first copy only. */
476 r600_flush_emit(rctx
);
479 /* Do the synchronization after the last copy, so that all data is written to memory. */
480 if (size
== byte_count
) {
481 sync
= PKT3_CP_DMA_CP_SYNC
;
484 /* This must be done after r600_need_cs_space. */
485 src_reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, (struct r600_resource
*)src
, RADEON_USAGE_READ
);
486 dst_reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, (struct r600_resource
*)dst
, RADEON_USAGE_WRITE
);
488 radeon_emit(cs
, PKT3(PKT3_CP_DMA
, 4, 0));
489 radeon_emit(cs
, src_offset
); /* SRC_ADDR_LO [31:0] */
490 radeon_emit(cs
, sync
| ((src_offset
>> 32) & 0xff)); /* CP_SYNC [31] | SRC_ADDR_HI [7:0] */
491 radeon_emit(cs
, dst_offset
); /* DST_ADDR_LO [31:0] */
492 radeon_emit(cs
, (dst_offset
>> 32) & 0xff); /* DST_ADDR_HI [7:0] */
493 radeon_emit(cs
, byte_count
); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
495 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
496 radeon_emit(cs
, src_reloc
);
497 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
498 radeon_emit(cs
, dst_reloc
);
501 src_offset
+= byte_count
;
502 dst_offset
+= byte_count
;
505 /* Invalidate the read caches. */
506 rctx
->b
.flags
|= R600_CONTEXT_INV_CONST_CACHE
|
507 R600_CONTEXT_INV_VERTEX_CACHE
|
508 R600_CONTEXT_INV_TEX_CACHE
;
510 util_range_add(&r600_resource(dst
)->valid_buffer_range
, dst_offset
,
514 void r600_need_dma_space(struct r600_context
*ctx
, unsigned num_dw
)
516 /* The number of dwords we already used in the DMA so far. */
517 num_dw
+= ctx
->b
.rings
.dma
.cs
->cdw
;
518 /* Flush if there's not enough space. */
519 if (num_dw
> RADEON_MAX_CMDBUF_DWORDS
) {
520 ctx
->b
.rings
.dma
.flush(ctx
, RADEON_FLUSH_ASYNC
);
524 void r600_dma_copy(struct r600_context
*rctx
,
525 struct pipe_resource
*dst
,
526 struct pipe_resource
*src
,
531 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.dma
.cs
;
532 unsigned i
, ncopy
, csize
, shift
;
533 struct r600_resource
*rdst
= (struct r600_resource
*)dst
;
534 struct r600_resource
*rsrc
= (struct r600_resource
*)src
;
536 /* make sure that the dma ring is only one active */
537 rctx
->b
.rings
.gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
);
541 ncopy
= (size
/ 0xffff) + !!(size
% 0xffff);
543 r600_need_dma_space(rctx
, ncopy
* 5);
544 for (i
= 0; i
< ncopy
; i
++) {
545 csize
= size
< 0xffff ? size
: 0xffff;
546 /* emit reloc before writting cs so that cs is always in consistent state */
547 r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.dma
, rsrc
, RADEON_USAGE_READ
);
548 r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.dma
, rdst
, RADEON_USAGE_WRITE
);
549 cs
->buf
[cs
->cdw
++] = DMA_PACKET(DMA_PACKET_COPY
, 0, 0, csize
);
550 cs
->buf
[cs
->cdw
++] = dst_offset
& 0xfffffffc;
551 cs
->buf
[cs
->cdw
++] = src_offset
& 0xfffffffc;
552 cs
->buf
[cs
->cdw
++] = (dst_offset
>> 32UL) & 0xff;
553 cs
->buf
[cs
->cdw
++] = (src_offset
>> 32UL) & 0xff;
554 dst_offset
+= csize
<< shift
;
555 src_offset
+= csize
<< shift
;
559 util_range_add(&rdst
->valid_buffer_range
, dst_offset
,