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r600g: move DB_SHADER_CONTROL into db_misc_state
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_hw_context_priv.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30
31 /* Get backends mask */
32 void r600_get_backend_mask(struct r600_context *ctx)
33 {
34 struct radeon_winsys_cs *cs = ctx->cs;
35 struct r600_resource *buffer;
36 uint32_t *results;
37 unsigned num_backends = ctx->screen->info.r600_num_backends;
38 unsigned i, mask = 0;
39 uint64_t va;
40
41 /* if backend_map query is supported by the kernel */
42 if (ctx->screen->info.r600_backend_map_valid) {
43 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
44 unsigned backend_map = ctx->screen->info.r600_backend_map;
45 unsigned item_width, item_mask;
46
47 if (ctx->chip_class >= EVERGREEN) {
48 item_width = 4;
49 item_mask = 0x7;
50 } else {
51 item_width = 2;
52 item_mask = 0x3;
53 }
54
55 while(num_tile_pipes--) {
56 i = backend_map & item_mask;
57 mask |= (1<<i);
58 backend_map >>= item_width;
59 }
60 if (mask != 0) {
61 ctx->backend_mask = mask;
62 return;
63 }
64 }
65
66 /* otherwise backup path for older kernels */
67
68 /* create buffer for event data */
69 buffer = (struct r600_resource*)
70 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
71 PIPE_USAGE_STAGING, ctx->max_db*16);
72 if (!buffer)
73 goto err;
74
75 va = r600_resource_va(&ctx->screen->screen, (void*)buffer);
76
77 /* initialize buffer with zeroes */
78 results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE);
79 if (results) {
80 memset(results, 0, ctx->max_db * 4 * 4);
81 ctx->ws->buffer_unmap(buffer->cs_buf);
82
83 /* emit EVENT_WRITE for ZPASS_DONE */
84 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
85 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
86 cs->buf[cs->cdw++] = va;
87 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
88
89 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
90 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE);
91
92 /* analyze results */
93 results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_READ);
94 if (results) {
95 for(i = 0; i < ctx->max_db; i++) {
96 /* at least highest bit will be set if backend is used */
97 if (results[i*4 + 1])
98 mask |= (1<<i);
99 }
100 ctx->ws->buffer_unmap(buffer->cs_buf);
101 }
102 }
103
104 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
105
106 if (mask != 0) {
107 ctx->backend_mask = mask;
108 return;
109 }
110
111 err:
112 /* fallback to old method - set num_backends lower bits to 1 */
113 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
114 return;
115 }
116
117 static void r600_init_block(struct r600_context *ctx,
118 struct r600_block *block,
119 const struct r600_reg *reg, int index, int nreg,
120 unsigned opcode, unsigned offset_base)
121 {
122 int i = index;
123 int j, n = nreg;
124
125 /* initialize block */
126 block->flags = 0;
127 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
128 block->start_offset = reg[i].offset;
129 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
130 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
131 block->reg = &block->pm4[block->pm4_ndwords];
132 block->pm4_ndwords += n;
133 block->nreg = n;
134 block->nreg_dirty = n;
135 LIST_INITHEAD(&block->list);
136 LIST_INITHEAD(&block->enable_list);
137
138 for (j = 0; j < n; j++) {
139 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
140 block->flags |= REG_FLAG_DIRTY_ALWAYS;
141 }
142 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
143 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
144 block->status |= R600_BLOCK_STATUS_ENABLED;
145 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
146 LIST_ADDTAIL(&block->list,&ctx->dirty);
147 }
148 }
149 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
150 block->flags |= REG_FLAG_FLUSH_CHANGE;
151 }
152
153 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
154 block->nbo++;
155 assert(block->nbo < R600_BLOCK_MAX_BO);
156 block->pm4_bo_index[j] = block->nbo;
157 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
158 block->pm4[block->pm4_ndwords++] = 0x00000000;
159 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
160 }
161 }
162 /* check that we stay in limit */
163 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
164 }
165
166 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
167 unsigned opcode, unsigned offset_base)
168 {
169 struct r600_block *block;
170 struct r600_range *range;
171 int offset;
172
173 for (unsigned i = 0, n = 0; i < nreg; i += n) {
174 /* ignore new block balise */
175 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
176 n = 1;
177 continue;
178 }
179
180 /* register that need relocation are in their own group */
181 /* find number of consecutive registers */
182 n = 0;
183 offset = reg[i].offset;
184 while (reg[i + n].offset == offset) {
185 n++;
186 offset += 4;
187 if ((n + i) >= nreg)
188 break;
189 if (n >= (R600_BLOCK_MAX_REG - 2))
190 break;
191 }
192
193 /* allocate new block */
194 block = calloc(1, sizeof(struct r600_block));
195 if (block == NULL) {
196 return -ENOMEM;
197 }
198 ctx->nblocks++;
199 for (int j = 0; j < n; j++) {
200 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
201 /* create block table if it doesn't exist */
202 if (!range->blocks)
203 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
204 if (!range->blocks)
205 return -1;
206
207 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
208 }
209
210 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
211
212 }
213 return 0;
214 }
215
216 /* R600/R700 configuration */
217 static const struct r600_reg r600_config_reg_list[] = {
218 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
219 };
220
221 static const struct r600_reg r600_context_reg_list[] = {
222 {R_028D24_DB_HTILE_SURFACE, 0, 0},
223 {R_028614_SPI_VS_OUT_ID_0, 0, 0},
224 {R_028618_SPI_VS_OUT_ID_1, 0, 0},
225 {R_02861C_SPI_VS_OUT_ID_2, 0, 0},
226 {R_028620_SPI_VS_OUT_ID_3, 0, 0},
227 {R_028624_SPI_VS_OUT_ID_4, 0, 0},
228 {R_028628_SPI_VS_OUT_ID_5, 0, 0},
229 {R_02862C_SPI_VS_OUT_ID_6, 0, 0},
230 {R_028630_SPI_VS_OUT_ID_7, 0, 0},
231 {R_028634_SPI_VS_OUT_ID_8, 0, 0},
232 {R_028638_SPI_VS_OUT_ID_9, 0, 0},
233 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
234 {GROUP_FORCE_NEW_BLOCK, 0, 0},
235 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
236 {GROUP_FORCE_NEW_BLOCK, 0, 0},
237 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0},
238 {GROUP_FORCE_NEW_BLOCK, 0, 0},
239 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0},
240 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0},
241 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
242 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
243 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
244 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
245 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
246 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
247 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
248 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
249 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
250 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
251 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
252 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
253 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
254 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
255 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
256 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
257 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
258 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
259 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
260 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
261 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
262 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
263 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
264 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
265 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
266 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
267 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
268 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
269 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
270 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
271 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
272 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
273 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
274 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
275 {R_0286D8_SPI_INPUT_Z, 0, 0},
276 {GROUP_FORCE_NEW_BLOCK, 0, 0},
277 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
278 {GROUP_FORCE_NEW_BLOCK, 0, 0},
279 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
280 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
281 };
282
283 /* initialize */
284 void r600_context_fini(struct r600_context *ctx)
285 {
286 struct r600_block *block;
287 struct r600_range *range;
288
289 if (ctx->range) {
290 for (int i = 0; i < NUM_RANGES; i++) {
291 if (!ctx->range[i].blocks)
292 continue;
293 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
294 block = ctx->range[i].blocks[j];
295 if (block) {
296 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
297 range = &ctx->range[CTX_RANGE_ID(offset)];
298 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
299 }
300 for (int k = 1; k <= block->nbo; k++) {
301 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
302 }
303 free(block);
304 }
305 }
306 free(ctx->range[i].blocks);
307 }
308 }
309 free(ctx->blocks);
310 }
311
312 int r600_setup_block_table(struct r600_context *ctx)
313 {
314 /* setup block table */
315 int c = 0;
316 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
317 if (!ctx->blocks)
318 return -ENOMEM;
319 for (int i = 0; i < NUM_RANGES; i++) {
320 if (!ctx->range[i].blocks)
321 continue;
322 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
323 if (!ctx->range[i].blocks[j])
324 continue;
325
326 add = 1;
327 for (int k = 0; k < c; k++) {
328 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
329 add = 0;
330 break;
331 }
332 }
333 if (add) {
334 assert(c < ctx->nblocks);
335 ctx->blocks[c++] = ctx->range[i].blocks[j];
336 j += (ctx->range[i].blocks[j]->nreg) - 1;
337 }
338 }
339 }
340 return 0;
341 }
342
343 int r600_context_init(struct r600_context *ctx)
344 {
345 int r;
346
347 /* add blocks */
348 r = r600_context_add_block(ctx, r600_config_reg_list,
349 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
350 if (r)
351 goto out_err;
352 r = r600_context_add_block(ctx, r600_context_reg_list,
353 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
354 if (r)
355 goto out_err;
356
357 r = r600_setup_block_table(ctx);
358 if (r)
359 goto out_err;
360
361 ctx->max_db = 4;
362 return 0;
363 out_err:
364 r600_context_fini(ctx);
365 return r;
366 }
367
368 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
369 boolean count_draw_in)
370 {
371 /* The number of dwords we already used in the CS so far. */
372 num_dw += ctx->cs->cdw;
373
374 if (count_draw_in) {
375 unsigned i;
376
377 /* The number of dwords all the dirty states would take. */
378 for (i = 0; i < R600_NUM_ATOMS; i++) {
379 if (ctx->atoms[i] && ctx->atoms[i]->dirty) {
380 num_dw += ctx->atoms[i]->num_dw;
381 }
382 }
383
384 num_dw += ctx->pm4_dirty_cdwords;
385
386 /* The upper-bound of how much space a draw command would take. */
387 num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
388 }
389
390 /* Count in queries_suspend. */
391 num_dw += ctx->num_cs_dw_nontimer_queries_suspend;
392 num_dw += ctx->num_cs_dw_timer_queries_suspend;
393
394 /* Count in streamout_end at the end of CS. */
395 num_dw += ctx->num_cs_dw_streamout_end;
396
397 /* Count in render_condition(NULL) at the end of CS. */
398 if (ctx->predicate_drawing) {
399 num_dw += 3;
400 }
401
402 /* SX_MISC */
403 if (ctx->chip_class <= R700) {
404 num_dw += 3;
405 }
406
407 /* Count in framebuffer cache flushes at the end of CS. */
408 num_dw += R600_MAX_FLUSH_CS_DWORDS;
409
410 /* The fence at the end of CS. */
411 num_dw += 10;
412
413 /* Flush if there's not enough space. */
414 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
415 r600_flush(&ctx->context, NULL, RADEON_FLUSH_ASYNC);
416 }
417 }
418
419 void r600_context_dirty_block(struct r600_context *ctx,
420 struct r600_block *block,
421 int dirty, int index)
422 {
423 if ((index + 1) > block->nreg_dirty)
424 block->nreg_dirty = index + 1;
425
426 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
427 block->status |= R600_BLOCK_STATUS_DIRTY;
428 ctx->pm4_dirty_cdwords += block->pm4_ndwords;
429 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
430 block->status |= R600_BLOCK_STATUS_ENABLED;
431 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
432 }
433 LIST_ADDTAIL(&block->list,&ctx->dirty);
434
435 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
436 ctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
437 }
438 }
439 }
440
441 /**
442 * If reg needs a reloc, this function will add it to its block's reloc list.
443 * @return true if reg needs a reloc, false otherwise
444 */
445 static bool r600_reg_set_block_reloc(struct r600_pipe_reg *reg)
446 {
447 unsigned reloc_id;
448
449 if (!reg->block->pm4_bo_index[reg->id]) {
450 return false;
451 }
452 /* find relocation */
453 reloc_id = reg->block->pm4_bo_index[reg->id];
454 pipe_resource_reference(
455 (struct pipe_resource**)&reg->block->reloc[reloc_id].bo,
456 &reg->bo->b.b);
457 reg->block->reloc[reloc_id].bo_usage = reg->bo_usage;
458 return true;
459 }
460
461 /**
462 * This function will emit all the registers in state directly to the command
463 * stream allowing you to bypass the r600_context dirty list.
464 *
465 * This is used for dispatching compute shaders to avoid mixing compute and
466 * 3D states in the context's dirty list.
467 *
468 * @param pkt_flags Should be either 0 or RADEON_CP_PACKET3_COMPUTE_MODE. This
469 * value will be passed on to r600_context_block_emit_dirty an or'd against
470 * the PKT3 headers.
471 */
472 void r600_context_pipe_state_emit(struct r600_context *ctx,
473 struct r600_pipe_state *state,
474 unsigned pkt_flags)
475 {
476 unsigned i;
477
478 /* Mark all blocks as dirty:
479 * Since two registers can be in the same block, we need to make sure
480 * we mark all the blocks dirty before we emit any of them. If we were
481 * to mark blocks dirty and emit them in the same loop, like this:
482 *
483 * foreach (reg in state->regs) {
484 * mark_dirty(reg->block)
485 * emit_block(reg->block)
486 * }
487 *
488 * Then if we have two registers in this state that are in the same
489 * block, we would end up emitting that block twice.
490 */
491 for (i = 0; i < state->nregs; i++) {
492 struct r600_pipe_reg *reg = &state->regs[i];
493 /* Mark all the registers in the block as dirty */
494 reg->block->nreg_dirty = reg->block->nreg;
495 reg->block->status |= R600_BLOCK_STATUS_DIRTY;
496 /* Update the reloc for this register if necessary. */
497 r600_reg_set_block_reloc(reg);
498 }
499
500 /* Emit the registers writes */
501 for (i = 0; i < state->nregs; i++) {
502 struct r600_pipe_reg *reg = &state->regs[i];
503 if (reg->block->status & R600_BLOCK_STATUS_DIRTY) {
504 r600_context_block_emit_dirty(ctx, reg->block, pkt_flags);
505 }
506 }
507 }
508
509 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
510 {
511 struct r600_block *block;
512 int dirty;
513 for (int i = 0; i < state->nregs; i++) {
514 unsigned id;
515 struct r600_pipe_reg *reg = &state->regs[i];
516
517 block = reg->block;
518 id = reg->id;
519
520 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
521
522 if (reg->value != block->reg[id]) {
523 block->reg[id] = reg->value;
524 dirty |= R600_BLOCK_STATUS_DIRTY;
525 }
526 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
527 dirty |= R600_BLOCK_STATUS_DIRTY;
528 if (r600_reg_set_block_reloc(reg)) {
529 /* always force dirty for relocs for now */
530 dirty |= R600_BLOCK_STATUS_DIRTY;
531 }
532
533 if (dirty)
534 r600_context_dirty_block(ctx, block, dirty, id);
535 }
536 }
537
538 /**
539 * @param pkt_flags should be set to RADEON_CP_PACKET3_COMPUTE_MODE if this
540 * block will be used for compute shaders.
541 */
542 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block,
543 unsigned pkt_flags)
544 {
545 struct radeon_winsys_cs *cs = ctx->cs;
546 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
547 int cp_dwords = block->pm4_ndwords, start_dword = 0;
548 int new_dwords = 0;
549 int nbo = block->nbo;
550
551 if (block->nreg_dirty == 0 && optional) {
552 goto out;
553 }
554
555 if (nbo) {
556 for (int j = 0; j < block->nreg; j++) {
557 if (block->pm4_bo_index[j]) {
558 /* find relocation */
559 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
560 if (reloc->bo) {
561 block->pm4[reloc->bo_pm4_index] =
562 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage);
563 } else {
564 block->pm4[reloc->bo_pm4_index] = 0;
565 }
566 nbo--;
567 if (nbo == 0)
568 break;
569
570 }
571 }
572 }
573
574 optional &= (block->nreg_dirty != block->nreg);
575 if (optional) {
576 new_dwords = block->nreg_dirty;
577 start_dword = cs->cdw;
578 cp_dwords = new_dwords + 2;
579 }
580 memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4);
581
582 /* We are applying the pkt_flags after copying the register block to
583 * the the command stream, because it is possible this block will be
584 * emitted with a different pkt_flags, and we don't want to store the
585 * pkt_flags in the block.
586 */
587 cs->buf[cs->cdw] |= pkt_flags;
588 cs->cdw += cp_dwords;
589
590 if (optional) {
591 uint32_t newword;
592
593 newword = cs->buf[start_dword];
594 newword &= PKT_COUNT_C;
595 newword |= PKT_COUNT_S(new_dwords);
596 cs->buf[start_dword] = newword;
597 }
598 out:
599 block->status ^= R600_BLOCK_STATUS_DIRTY;
600 block->nreg_dirty = 0;
601 LIST_DELINIT(&block->list);
602 }
603
604 void r600_flush_emit(struct r600_context *rctx)
605 {
606 struct radeon_winsys_cs *cs = rctx->cs;
607
608 if (!rctx->flags) {
609 return;
610 }
611
612 if (rctx->flags & R600_CONTEXT_PS_PARTIAL_FLUSH) {
613 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
614 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
615 }
616
617 if (rctx->chip_class >= R700 &&
618 (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
619 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
620 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0);
621 }
622
623 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) {
624 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
625 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
626
627 /* DB flushes are special due to errata with hyperz, we need to
628 * insert a no-op, so that the cache has time to really flush.
629 */
630 if (rctx->chip_class <= R700 &&
631 rctx->flags & R600_CONTEXT_HTILE_ERRATA) {
632 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 31, 0);
633 cs->buf[cs->cdw++] = 0xdeadcafe;
634 cs->buf[cs->cdw++] = 0xdeadcafe;
635 cs->buf[cs->cdw++] = 0xdeadcafe;
636 cs->buf[cs->cdw++] = 0xdeadcafe;
637 cs->buf[cs->cdw++] = 0xdeadcafe;
638 cs->buf[cs->cdw++] = 0xdeadcafe;
639 cs->buf[cs->cdw++] = 0xdeadcafe;
640 cs->buf[cs->cdw++] = 0xdeadcafe;
641 cs->buf[cs->cdw++] = 0xdeadcafe;
642 cs->buf[cs->cdw++] = 0xdeadcafe;
643 cs->buf[cs->cdw++] = 0xdeadcafe;
644 cs->buf[cs->cdw++] = 0xdeadcafe;
645 cs->buf[cs->cdw++] = 0xdeadcafe;
646 cs->buf[cs->cdw++] = 0xdeadcafe;
647 cs->buf[cs->cdw++] = 0xdeadcafe;
648 cs->buf[cs->cdw++] = 0xdeadcafe;
649 cs->buf[cs->cdw++] = 0xdeadcafe;
650 cs->buf[cs->cdw++] = 0xdeadcafe;
651 cs->buf[cs->cdw++] = 0xdeadcafe;
652 cs->buf[cs->cdw++] = 0xdeadcafe;
653 cs->buf[cs->cdw++] = 0xdeadcafe;
654 cs->buf[cs->cdw++] = 0xdeadcafe;
655 cs->buf[cs->cdw++] = 0xdeadcafe;
656 cs->buf[cs->cdw++] = 0xdeadcafe;
657 cs->buf[cs->cdw++] = 0xdeadcafe;
658 cs->buf[cs->cdw++] = 0xdeadcafe;
659 cs->buf[cs->cdw++] = 0xdeadcafe;
660 cs->buf[cs->cdw++] = 0xdeadcafe;
661 cs->buf[cs->cdw++] = 0xdeadcafe;
662 cs->buf[cs->cdw++] = 0xdeadcafe;
663 cs->buf[cs->cdw++] = 0xdeadcafe;
664 cs->buf[cs->cdw++] = 0xdeadcafe;
665 }
666 }
667
668 if (rctx->flags & (R600_CONTEXT_CB_FLUSH |
669 R600_CONTEXT_DB_FLUSH |
670 R600_CONTEXT_SHADERCONST_FLUSH |
671 R600_CONTEXT_TEX_FLUSH |
672 R600_CONTEXT_VTX_FLUSH |
673 R600_CONTEXT_STREAMOUT_FLUSH)) {
674 /* anything left (cb, vtx, shader, streamout) can be flushed
675 * using the surface sync packet
676 */
677 unsigned flags = 0;
678
679 if (rctx->flags & R600_CONTEXT_CB_FLUSH) {
680 flags |= S_0085F0_CB_ACTION_ENA(1) |
681 S_0085F0_CB0_DEST_BASE_ENA(1) |
682 S_0085F0_CB1_DEST_BASE_ENA(1) |
683 S_0085F0_CB2_DEST_BASE_ENA(1) |
684 S_0085F0_CB3_DEST_BASE_ENA(1) |
685 S_0085F0_CB4_DEST_BASE_ENA(1) |
686 S_0085F0_CB5_DEST_BASE_ENA(1) |
687 S_0085F0_CB6_DEST_BASE_ENA(1) |
688 S_0085F0_CB7_DEST_BASE_ENA(1);
689
690 if (rctx->chip_class >= EVERGREEN) {
691 flags |= S_0085F0_CB8_DEST_BASE_ENA(1) |
692 S_0085F0_CB9_DEST_BASE_ENA(1) |
693 S_0085F0_CB10_DEST_BASE_ENA(1) |
694 S_0085F0_CB11_DEST_BASE_ENA(1);
695 }
696
697 /* RV670 errata
698 * (CB1_DEST_BASE_ENA is also required, which is
699 * included unconditionally above). */
700 if (rctx->family == CHIP_RV670 ||
701 rctx->family == CHIP_RS780 ||
702 rctx->family == CHIP_RS880) {
703 flags |= S_0085F0_DEST_BASE_0_ENA(1);
704 }
705 }
706
707 if (rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
708 flags |= S_0085F0_SO0_DEST_BASE_ENA(1) |
709 S_0085F0_SO1_DEST_BASE_ENA(1) |
710 S_0085F0_SO2_DEST_BASE_ENA(1) |
711 S_0085F0_SO3_DEST_BASE_ENA(1) |
712 S_0085F0_SMX_ACTION_ENA(1);
713
714 /* RV670 errata */
715 if (rctx->family == CHIP_RV670 ||
716 rctx->family == CHIP_RS780 ||
717 rctx->family == CHIP_RS880) {
718 flags |= S_0085F0_DEST_BASE_0_ENA(1);
719 }
720 }
721
722 flags |= (rctx->flags & R600_CONTEXT_DB_FLUSH) ? S_0085F0_DB_ACTION_ENA(1) |
723 S_0085F0_DB_DEST_BASE_ENA(1): 0;
724 flags |= (rctx->flags & R600_CONTEXT_SHADERCONST_FLUSH) ? S_0085F0_SH_ACTION_ENA(1) : 0;
725 flags |= (rctx->flags & R600_CONTEXT_TEX_FLUSH) ? S_0085F0_TC_ACTION_ENA(1) : 0;
726 flags |= (rctx->flags & R600_CONTEXT_VTX_FLUSH) ? S_0085F0_VC_ACTION_ENA(1) : 0;
727
728 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
729 cs->buf[cs->cdw++] = flags; /* CP_COHER_CNTL */
730 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
731 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
732 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
733 }
734
735 if (rctx->flags & R600_CONTEXT_WAIT_IDLE) {
736 /* wait for things to settle */
737 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
738 }
739
740 /* everything is properly flushed */
741 rctx->flags = 0;
742 }
743
744 void r600_context_flush(struct r600_context *ctx, unsigned flags)
745 {
746 struct radeon_winsys_cs *cs = ctx->cs;
747
748 if (cs->cdw == ctx->start_cs_cmd.num_dw)
749 return;
750
751 ctx->timer_queries_suspended = false;
752 ctx->nontimer_queries_suspended = false;
753 ctx->streamout_suspended = false;
754
755 /* suspend queries */
756 if (ctx->num_cs_dw_timer_queries_suspend) {
757 r600_suspend_timer_queries(ctx);
758 ctx->timer_queries_suspended = true;
759 }
760 if (ctx->num_cs_dw_nontimer_queries_suspend) {
761 r600_suspend_nontimer_queries(ctx);
762 ctx->nontimer_queries_suspended = true;
763 }
764
765 if (ctx->num_cs_dw_streamout_end) {
766 r600_context_streamout_end(ctx);
767 ctx->streamout_suspended = true;
768 }
769
770 /* partial flush is needed to avoid lockups on some chips with user fences */
771 ctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
772
773 /* flush the framebuffer */
774 ctx->flags |= R600_CONTEXT_CB_FLUSH | R600_CONTEXT_DB_FLUSH;
775
776 /* R6xx errata */
777 if (ctx->chip_class == R600) {
778 ctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
779 }
780
781 r600_flush_emit(ctx);
782
783 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
784 if (ctx->chip_class <= R700) {
785 r600_write_context_reg(cs, R_028350_SX_MISC, 0);
786 }
787
788 /* force to keep tiling flags */
789 if (ctx->keep_tiling_flags) {
790 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
791 }
792
793 /* Flush the CS. */
794 ctx->ws->cs_flush(ctx->cs, flags);
795
796 r600_begin_new_cs(ctx);
797 }
798
799 void r600_begin_new_cs(struct r600_context *ctx)
800 {
801 struct r600_block *enable_block = NULL;
802 unsigned shader;
803
804 ctx->pm4_dirty_cdwords = 0;
805 ctx->flags = 0;
806
807 /* Begin a new CS. */
808 r600_emit_command_buffer(ctx->cs, &ctx->start_cs_cmd);
809
810 /* Re-emit states. */
811 ctx->alphatest_state.atom.dirty = true;
812 ctx->blend_color.atom.dirty = true;
813 ctx->cb_misc_state.atom.dirty = true;
814 ctx->clip_misc_state.atom.dirty = true;
815 ctx->clip_state.atom.dirty = true;
816 ctx->db_misc_state.atom.dirty = true;
817 ctx->framebuffer.atom.dirty = true;
818 ctx->poly_offset_state.atom.dirty = true;
819 ctx->vgt_state.atom.dirty = true;
820 ctx->vgt2_state.atom.dirty = true;
821 ctx->sample_mask.atom.dirty = true;
822 ctx->scissor.atom.dirty = true;
823 ctx->stencil_ref.atom.dirty = true;
824 ctx->vertex_fetch_shader.atom.dirty = true;
825 ctx->viewport.atom.dirty = true;
826
827 if (ctx->blend_state.cso)
828 ctx->blend_state.atom.dirty = true;
829 if (ctx->dsa_state.cso)
830 ctx->dsa_state.atom.dirty = true;
831 if (ctx->rasterizer_state.cso)
832 ctx->rasterizer_state.atom.dirty = true;
833
834 if (ctx->chip_class <= R700) {
835 ctx->seamless_cube_map.atom.dirty = true;
836 }
837
838 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
839 r600_vertex_buffers_dirty(ctx);
840
841 /* Re-emit shader resources. */
842 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
843 struct r600_constbuf_state *constbuf = &ctx->constbuf_state[shader];
844 struct r600_textures_info *samplers = &ctx->samplers[shader];
845
846 constbuf->dirty_mask = constbuf->enabled_mask;
847 samplers->views.dirty_mask = samplers->views.enabled_mask;
848 samplers->states.dirty_mask = samplers->states.enabled_mask;
849
850 r600_constant_buffers_dirty(ctx, constbuf);
851 r600_sampler_views_dirty(ctx, &samplers->views);
852 r600_sampler_states_dirty(ctx, &samplers->states);
853 }
854
855 if (ctx->streamout_suspended) {
856 ctx->streamout_start = TRUE;
857 ctx->streamout_append_bitmask = ~0;
858 }
859
860 /* resume queries */
861 if (ctx->timer_queries_suspended) {
862 r600_resume_timer_queries(ctx);
863 }
864 if (ctx->nontimer_queries_suspended) {
865 r600_resume_nontimer_queries(ctx);
866 }
867
868 /* set all valid group as dirty so they get reemited on
869 * next draw command
870 */
871 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
872 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
873 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
874 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
875 }
876 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
877 enable_block->nreg_dirty = enable_block->nreg;
878 }
879
880 /* Re-emit the draw state. */
881 ctx->last_primitive_type = -1;
882 ctx->last_start_instance = -1;
883 }
884
885 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
886 {
887 struct radeon_winsys_cs *cs = ctx->cs;
888 uint64_t va;
889
890 r600_need_cs_space(ctx, 10, FALSE);
891
892 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
893 va = va + (offset << 2);
894
895 ctx->flags &= ~R600_CONTEXT_PS_PARTIAL_FLUSH;
896 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
897 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
898
899 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
900 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
901 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */
902 /* DATA_SEL | INT_EN | ADDRESS_HI */
903 cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF);
904 cs->buf[cs->cdw++] = value; /* DATA_LO */
905 cs->buf[cs->cdw++] = 0; /* DATA_HI */
906 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
907 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE);
908 }
909
910 static void r600_flush_vgt_streamout(struct r600_context *ctx)
911 {
912 struct radeon_winsys_cs *cs = ctx->cs;
913
914 r600_write_config_reg(cs, R_008490_CP_STRMOUT_CNTL, 0);
915
916 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
917 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
918
919 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
920 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
921 cs->buf[cs->cdw++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */
922 cs->buf[cs->cdw++] = 0;
923 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */
924 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */
925 cs->buf[cs->cdw++] = 4; /* poll interval */
926 }
927
928 static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
929 {
930 struct radeon_winsys_cs *cs = ctx->cs;
931
932 if (buffer_enable_bit) {
933 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(1));
934 r600_write_context_reg(cs, R_028B20_VGT_STRMOUT_BUFFER_EN, buffer_enable_bit);
935 } else {
936 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(0));
937 }
938 }
939
940 void r600_context_streamout_begin(struct r600_context *ctx)
941 {
942 struct radeon_winsys_cs *cs = ctx->cs;
943 struct r600_so_target **t = ctx->so_targets;
944 unsigned *stride_in_dw = ctx->vs_shader->so.stride;
945 unsigned buffer_en, i, update_flags = 0;
946 uint64_t va;
947
948 buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) |
949 (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) |
950 (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) |
951 (ctx->num_so_targets >= 4 && t[3] ? 8 : 0);
952
953 ctx->num_cs_dw_streamout_end =
954 12 + /* flush_vgt_streamout */
955 util_bitcount(buffer_en) * 8 + /* STRMOUT_BUFFER_UPDATE */
956 3 /* set_streamout_enable(0) */;
957
958 r600_need_cs_space(ctx,
959 12 + /* flush_vgt_streamout */
960 6 + /* set_streamout_enable */
961 util_bitcount(buffer_en) * 7 + /* SET_CONTEXT_REG */
962 (ctx->family >= CHIP_RS780 &&
963 ctx->family <= CHIP_RV740 ? util_bitcount(buffer_en) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
964 util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 + /* STRMOUT_BUFFER_UPDATE */
965 util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 + /* STRMOUT_BUFFER_UPDATE */
966 (ctx->family > CHIP_R600 && ctx->family < CHIP_RS780 ? 2 : 0) + /* SURFACE_BASE_UPDATE */
967 ctx->num_cs_dw_streamout_end, TRUE);
968
969 if (ctx->chip_class >= EVERGREEN) {
970 evergreen_flush_vgt_streamout(ctx);
971 evergreen_set_streamout_enable(ctx, buffer_en);
972 } else {
973 r600_flush_vgt_streamout(ctx);
974 r600_set_streamout_enable(ctx, buffer_en);
975 }
976
977 for (i = 0; i < ctx->num_so_targets; i++) {
978 if (t[i]) {
979 t[i]->stride_in_dw = stride_in_dw[i];
980 t[i]->so_index = i;
981 va = r600_resource_va(&ctx->screen->screen,
982 (void*)t[i]->b.buffer);
983
984 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
985
986 r600_write_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
987 r600_write_value(cs, (t[i]->b.buffer_offset +
988 t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
989 r600_write_value(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
990 r600_write_value(cs, va >> 8); /* BUFFER_BASE */
991
992 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
993 cs->buf[cs->cdw++] =
994 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
995 RADEON_USAGE_WRITE);
996
997 /* R7xx requires this packet after updating BUFFER_BASE.
998 * Without this, R7xx locks up. */
999 if (ctx->family >= CHIP_RS780 && ctx->family <= CHIP_RV740) {
1000 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0);
1001 cs->buf[cs->cdw++] = i;
1002 cs->buf[cs->cdw++] = va >> 8;
1003
1004 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1005 cs->buf[cs->cdw++] =
1006 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
1007 RADEON_USAGE_WRITE);
1008 }
1009
1010 if (ctx->streamout_append_bitmask & (1 << i)) {
1011 va = r600_resource_va(&ctx->screen->screen,
1012 (void*)t[i]->filled_size);
1013 /* Append. */
1014 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1015 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1016 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
1017 cs->buf[cs->cdw++] = 0; /* unused */
1018 cs->buf[cs->cdw++] = 0; /* unused */
1019 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1020 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1021
1022 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1023 cs->buf[cs->cdw++] =
1024 r600_context_bo_reloc(ctx, t[i]->filled_size,
1025 RADEON_USAGE_READ);
1026 } else {
1027 /* Start from the beginning. */
1028 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1029 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1030 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
1031 cs->buf[cs->cdw++] = 0; /* unused */
1032 cs->buf[cs->cdw++] = 0; /* unused */
1033 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
1034 cs->buf[cs->cdw++] = 0; /* unused */
1035 }
1036 }
1037 }
1038
1039 if (ctx->family > CHIP_R600 && ctx->family < CHIP_RS780) {
1040 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
1041 cs->buf[cs->cdw++] = update_flags;
1042 }
1043 }
1044
1045 void r600_context_streamout_end(struct r600_context *ctx)
1046 {
1047 struct radeon_winsys_cs *cs = ctx->cs;
1048 struct r600_so_target **t = ctx->so_targets;
1049 unsigned i;
1050 uint64_t va;
1051
1052 if (ctx->chip_class >= EVERGREEN) {
1053 evergreen_flush_vgt_streamout(ctx);
1054 } else {
1055 r600_flush_vgt_streamout(ctx);
1056 }
1057
1058 for (i = 0; i < ctx->num_so_targets; i++) {
1059 if (t[i]) {
1060 va = r600_resource_va(&ctx->screen->screen,
1061 (void*)t[i]->filled_size);
1062 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1063 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1064 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
1065 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
1066 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* dst address lo */
1067 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* dst address hi */
1068 cs->buf[cs->cdw++] = 0; /* unused */
1069 cs->buf[cs->cdw++] = 0; /* unused */
1070
1071 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1072 cs->buf[cs->cdw++] =
1073 r600_context_bo_reloc(ctx, t[i]->filled_size,
1074 RADEON_USAGE_WRITE);
1075
1076 }
1077 }
1078
1079 if (ctx->chip_class >= EVERGREEN) {
1080 evergreen_set_streamout_enable(ctx, 0);
1081 } else {
1082 r600_set_streamout_enable(ctx, 0);
1083 }
1084 ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
1085
1086 /* R6xx errata */
1087 if (ctx->chip_class == R600) {
1088 ctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
1089 }
1090 ctx->num_cs_dw_streamout_end = 0;
1091 }