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Revert "r600g: fix and improve rasterizer discard for r600-r700"
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_hw_context_priv.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30
31 /* Get backends mask */
32 void r600_get_backend_mask(struct r600_context *ctx)
33 {
34 struct radeon_winsys_cs *cs = ctx->cs;
35 struct r600_resource *buffer;
36 uint32_t *results;
37 unsigned num_backends = ctx->screen->info.r600_num_backends;
38 unsigned i, mask = 0;
39
40 /* if backend_map query is supported by the kernel */
41 if (ctx->screen->info.r600_backend_map_valid) {
42 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
43 unsigned backend_map = ctx->screen->info.r600_backend_map;
44 unsigned item_width, item_mask;
45
46 if (ctx->chip_class >= EVERGREEN) {
47 item_width = 4;
48 item_mask = 0x7;
49 } else {
50 item_width = 2;
51 item_mask = 0x3;
52 }
53
54 while(num_tile_pipes--) {
55 i = backend_map & item_mask;
56 mask |= (1<<i);
57 backend_map >>= item_width;
58 }
59 if (mask != 0) {
60 ctx->backend_mask = mask;
61 return;
62 }
63 }
64
65 /* otherwise backup path for older kernels */
66
67 /* create buffer for event data */
68 buffer = (struct r600_resource*)
69 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
70 PIPE_USAGE_STAGING, ctx->max_db*16);
71 if (!buffer)
72 goto err;
73
74 /* initialize buffer with zeroes */
75 results = ctx->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE);
76 if (results) {
77 memset(results, 0, ctx->max_db * 4 * 4);
78 ctx->ws->buffer_unmap(buffer->buf);
79
80 /* emit EVENT_WRITE for ZPASS_DONE */
81 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
82 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
83 cs->buf[cs->cdw++] = 0;
84 cs->buf[cs->cdw++] = 0;
85
86 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
87 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE);
88
89 /* analyze results */
90 results = ctx->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_READ);
91 if (results) {
92 for(i = 0; i < ctx->max_db; i++) {
93 /* at least highest bit will be set if backend is used */
94 if (results[i*4 + 1])
95 mask |= (1<<i);
96 }
97 ctx->ws->buffer_unmap(buffer->buf);
98 }
99 }
100
101 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
102
103 if (mask != 0) {
104 ctx->backend_mask = mask;
105 return;
106 }
107
108 err:
109 /* fallback to old method - set num_backends lower bits to 1 */
110 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
111 return;
112 }
113
114 void r600_context_ps_partial_flush(struct r600_context *ctx)
115 {
116 struct radeon_winsys_cs *cs = ctx->cs;
117
118 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
119 return;
120
121 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
122 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
123
124 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
125 }
126
127 static void r600_init_block(struct r600_context *ctx,
128 struct r600_block *block,
129 const struct r600_reg *reg, int index, int nreg,
130 unsigned opcode, unsigned offset_base)
131 {
132 int i = index;
133 int j, n = nreg;
134
135 /* initialize block */
136 if (opcode == PKT3_SET_RESOURCE) {
137 block->flags = BLOCK_FLAG_RESOURCE;
138 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; /* dirty all blocks at start */
139 } else {
140 block->flags = 0;
141 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
142 }
143 block->start_offset = reg[i].offset;
144 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
145 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
146 block->reg = &block->pm4[block->pm4_ndwords];
147 block->pm4_ndwords += n;
148 block->nreg = n;
149 block->nreg_dirty = n;
150 LIST_INITHEAD(&block->list);
151 LIST_INITHEAD(&block->enable_list);
152
153 for (j = 0; j < n; j++) {
154 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
155 block->flags |= REG_FLAG_DIRTY_ALWAYS;
156 }
157 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
158 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
159 block->status |= R600_BLOCK_STATUS_ENABLED;
160 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
161 LIST_ADDTAIL(&block->list,&ctx->dirty);
162 }
163 }
164 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
165 block->flags |= REG_FLAG_FLUSH_CHANGE;
166 }
167
168 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
169 block->nbo++;
170 assert(block->nbo < R600_BLOCK_MAX_BO);
171 block->pm4_bo_index[j] = block->nbo;
172 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
173 block->pm4[block->pm4_ndwords++] = 0x00000000;
174 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
175 }
176 if ((ctx->family > CHIP_R600) &&
177 (ctx->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
178 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
179 block->pm4[block->pm4_ndwords++] = reg[i+j].sbu_flags;
180 }
181 }
182 /* check that we stay in limit */
183 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
184 }
185
186 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
187 unsigned opcode, unsigned offset_base)
188 {
189 struct r600_block *block;
190 struct r600_range *range;
191 int offset;
192
193 for (unsigned i = 0, n = 0; i < nreg; i += n) {
194 /* ignore new block balise */
195 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
196 n = 1;
197 continue;
198 }
199
200 /* ignore regs not on R600 on R600 */
201 if ((reg[i].flags & REG_FLAG_NOT_R600) && ctx->family == CHIP_R600) {
202 n = 1;
203 continue;
204 }
205
206 /* register that need relocation are in their own group */
207 /* find number of consecutive registers */
208 n = 0;
209 offset = reg[i].offset;
210 while (reg[i + n].offset == offset) {
211 n++;
212 offset += 4;
213 if ((n + i) >= nreg)
214 break;
215 if (n >= (R600_BLOCK_MAX_REG - 2))
216 break;
217 }
218
219 /* allocate new block */
220 block = calloc(1, sizeof(struct r600_block));
221 if (block == NULL) {
222 return -ENOMEM;
223 }
224 ctx->nblocks++;
225 for (int j = 0; j < n; j++) {
226 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
227 /* create block table if it doesn't exist */
228 if (!range->blocks)
229 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
230 if (!range->blocks)
231 return -1;
232
233 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
234 }
235
236 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
237
238 }
239 return 0;
240 }
241
242 /* R600/R700 configuration */
243 static const struct r600_reg r600_config_reg_list[] = {
244 {R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
245 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
246 {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
247 };
248
249 static const struct r600_reg r600_ctl_const_list[] = {
250 {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
251 };
252
253 static const struct r600_reg r600_context_reg_list[] = {
254 {R_028A4C_PA_SC_MODE_CNTL, 0, 0},
255 {GROUP_FORCE_NEW_BLOCK, 0, 0},
256 {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0)},
257 {GROUP_FORCE_NEW_BLOCK, 0, 0},
258 {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
259 {R_028060_CB_COLOR0_SIZE, 0, 0},
260 {R_028080_CB_COLOR0_VIEW, 0, 0},
261 {GROUP_FORCE_NEW_BLOCK, 0, 0},
262 {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0},
263 {GROUP_FORCE_NEW_BLOCK, 0, 0},
264 {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0},
265 {GROUP_FORCE_NEW_BLOCK, 0, 0},
266 {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1)},
267 {GROUP_FORCE_NEW_BLOCK, 0, 0},
268 {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
269 {R_028064_CB_COLOR1_SIZE, 0, 0},
270 {R_028084_CB_COLOR1_VIEW, 0, 0},
271 {GROUP_FORCE_NEW_BLOCK, 0, 0},
272 {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0},
273 {GROUP_FORCE_NEW_BLOCK, 0, 0},
274 {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0},
275 {GROUP_FORCE_NEW_BLOCK, 0, 0},
276 {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2)},
277 {GROUP_FORCE_NEW_BLOCK, 0, 0},
278 {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
279 {R_028068_CB_COLOR2_SIZE, 0, 0},
280 {R_028088_CB_COLOR2_VIEW, 0, 0},
281 {GROUP_FORCE_NEW_BLOCK, 0, 0},
282 {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0},
283 {GROUP_FORCE_NEW_BLOCK, 0, 0},
284 {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0},
285 {GROUP_FORCE_NEW_BLOCK, 0, 0},
286 {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3)},
287 {GROUP_FORCE_NEW_BLOCK, 0, 0},
288 {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
289 {R_02806C_CB_COLOR3_SIZE, 0, 0},
290 {R_02808C_CB_COLOR3_VIEW, 0, 0},
291 {GROUP_FORCE_NEW_BLOCK, 0, 0},
292 {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0},
293 {GROUP_FORCE_NEW_BLOCK, 0, 0},
294 {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0},
295 {GROUP_FORCE_NEW_BLOCK, 0, 0},
296 {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4)},
297 {GROUP_FORCE_NEW_BLOCK, 0, 0},
298 {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
299 {R_028070_CB_COLOR4_SIZE, 0, 0},
300 {R_028090_CB_COLOR4_VIEW, 0, 0},
301 {GROUP_FORCE_NEW_BLOCK, 0, 0},
302 {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0},
303 {GROUP_FORCE_NEW_BLOCK, 0, 0},
304 {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0},
305 {GROUP_FORCE_NEW_BLOCK, 0, 0},
306 {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5)},
307 {GROUP_FORCE_NEW_BLOCK, 0, 0},
308 {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
309 {R_028074_CB_COLOR5_SIZE, 0, 0},
310 {R_028094_CB_COLOR5_VIEW, 0, 0},
311 {GROUP_FORCE_NEW_BLOCK, 0, 0},
312 {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0},
313 {GROUP_FORCE_NEW_BLOCK, 0, 0},
314 {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0},
315 {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6)},
316 {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
317 {R_028078_CB_COLOR6_SIZE, 0, 0},
318 {R_028098_CB_COLOR6_VIEW, 0, 0},
319 {GROUP_FORCE_NEW_BLOCK, 0, 0},
320 {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0},
321 {GROUP_FORCE_NEW_BLOCK, 0, 0},
322 {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0},
323 {GROUP_FORCE_NEW_BLOCK, 0, 0},
324 {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7)},
325 {GROUP_FORCE_NEW_BLOCK, 0, 0},
326 {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
327 {R_02807C_CB_COLOR7_SIZE, 0, 0},
328 {R_02809C_CB_COLOR7_VIEW, 0, 0},
329 {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0},
330 {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0},
331 {R_028120_CB_CLEAR_RED, 0, 0},
332 {R_028124_CB_CLEAR_GREEN, 0, 0},
333 {R_028128_CB_CLEAR_BLUE, 0, 0},
334 {R_02812C_CB_CLEAR_ALPHA, 0, 0},
335 {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0},
336 {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0},
337 {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0},
338 {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0},
339 {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0},
340 {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0},
341 {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0},
342 {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0},
343 {R_02823C_CB_SHADER_MASK, 0, 0},
344 {R_028238_CB_TARGET_MASK, 0, 0},
345 {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
346 {R_028414_CB_BLEND_RED, 0, 0},
347 {R_028418_CB_BLEND_GREEN, 0, 0},
348 {R_02841C_CB_BLEND_BLUE, 0, 0},
349 {R_028420_CB_BLEND_ALPHA, 0, 0},
350 {R_028424_CB_FOG_RED, 0, 0},
351 {R_028428_CB_FOG_GREEN, 0, 0},
352 {R_02842C_CB_FOG_BLUE, 0, 0},
353 {R_028430_DB_STENCILREFMASK, 0, 0},
354 {R_028434_DB_STENCILREFMASK_BF, 0, 0},
355 {R_028438_SX_ALPHA_REF, 0, 0},
356 {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0},
357 {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0},
358 {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0},
359 {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0},
360 {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0},
361 {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0},
362 {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0},
363 {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0},
364 {R_0287A0_CB_SHADER_CONTROL, 0, 0},
365 {R_028800_DB_DEPTH_CONTROL, 0, 0},
366 {R_028804_CB_BLEND_CONTROL, 0, 0},
367 {R_028808_CB_COLOR_CONTROL, 0, 0},
368 {R_02880C_DB_SHADER_CONTROL, 0, 0},
369 {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH},
370 {R_028000_DB_DEPTH_SIZE, 0, 0},
371 {R_028004_DB_DEPTH_VIEW, 0, 0},
372 {GROUP_FORCE_NEW_BLOCK, 0, 0},
373 {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0},
374 {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
375 {R_028D24_DB_HTILE_SURFACE, 0, 0},
376 {R_028D34_DB_PREFETCH_LIMIT, 0, 0},
377 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
378 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
379 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
380 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
381 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
382 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
383 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
384 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
385 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
386 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
387 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
388 {R_028810_PA_CL_CLIP_CNTL, 0, 0},
389 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
390 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
391 {R_028A00_PA_SU_POINT_SIZE, 0, 0},
392 {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
393 {R_028A08_PA_SU_LINE_CNTL, 0, 0},
394 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
395 {R_028C08_PA_SU_VTX_CNTL, 0, 0},
396 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
397 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
398 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
399 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
400 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
401 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
402 {R_028E20_PA_CL_UCP0_X, 0, 0},
403 {R_028E24_PA_CL_UCP0_Y, 0, 0},
404 {R_028E28_PA_CL_UCP0_Z, 0, 0},
405 {R_028E2C_PA_CL_UCP0_W, 0, 0},
406 {R_028E30_PA_CL_UCP1_X, 0, 0},
407 {R_028E34_PA_CL_UCP1_Y, 0, 0},
408 {R_028E38_PA_CL_UCP1_Z, 0, 0},
409 {R_028E3C_PA_CL_UCP1_W, 0, 0},
410 {R_028E40_PA_CL_UCP2_X, 0, 0},
411 {R_028E44_PA_CL_UCP2_Y, 0, 0},
412 {R_028E48_PA_CL_UCP2_Z, 0, 0},
413 {R_028E4C_PA_CL_UCP2_W, 0, 0},
414 {R_028E50_PA_CL_UCP3_X, 0, 0},
415 {R_028E54_PA_CL_UCP3_Y, 0, 0},
416 {R_028E58_PA_CL_UCP3_Z, 0, 0},
417 {R_028E5C_PA_CL_UCP3_W, 0, 0},
418 {R_028E60_PA_CL_UCP4_X, 0, 0},
419 {R_028E64_PA_CL_UCP4_Y, 0, 0},
420 {R_028E68_PA_CL_UCP4_Z, 0, 0},
421 {R_028E6C_PA_CL_UCP4_W, 0, 0},
422 {R_028E70_PA_CL_UCP5_X, 0, 0},
423 {R_028E74_PA_CL_UCP5_Y, 0, 0},
424 {R_028E78_PA_CL_UCP5_Z, 0, 0},
425 {R_028E7C_PA_CL_UCP5_W, 0, 0},
426 {R_028380_SQ_VTX_SEMANTIC_0, 0, 0},
427 {R_028384_SQ_VTX_SEMANTIC_1, 0, 0},
428 {R_028388_SQ_VTX_SEMANTIC_2, 0, 0},
429 {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0},
430 {R_028390_SQ_VTX_SEMANTIC_4, 0, 0},
431 {R_028394_SQ_VTX_SEMANTIC_5, 0, 0},
432 {R_028398_SQ_VTX_SEMANTIC_6, 0, 0},
433 {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0},
434 {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0},
435 {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0},
436 {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0},
437 {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0},
438 {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0},
439 {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0},
440 {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0},
441 {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0},
442 {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0},
443 {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0},
444 {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0},
445 {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0},
446 {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0},
447 {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0},
448 {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0},
449 {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0},
450 {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0},
451 {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0},
452 {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0},
453 {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0},
454 {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0},
455 {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0},
456 {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0},
457 {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0},
458 {R_028614_SPI_VS_OUT_ID_0, 0, 0},
459 {R_028618_SPI_VS_OUT_ID_1, 0, 0},
460 {R_02861C_SPI_VS_OUT_ID_2, 0, 0},
461 {R_028620_SPI_VS_OUT_ID_3, 0, 0},
462 {R_028624_SPI_VS_OUT_ID_4, 0, 0},
463 {R_028628_SPI_VS_OUT_ID_5, 0, 0},
464 {R_02862C_SPI_VS_OUT_ID_6, 0, 0},
465 {R_028630_SPI_VS_OUT_ID_7, 0, 0},
466 {R_028634_SPI_VS_OUT_ID_8, 0, 0},
467 {R_028638_SPI_VS_OUT_ID_9, 0, 0},
468 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
469 {GROUP_FORCE_NEW_BLOCK, 0, 0},
470 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
471 {GROUP_FORCE_NEW_BLOCK, 0, 0},
472 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0},
473 {GROUP_FORCE_NEW_BLOCK, 0, 0},
474 {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
475 {GROUP_FORCE_NEW_BLOCK, 0, 0},
476 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0},
477 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0},
478 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
479 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
480 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
481 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
482 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
483 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
484 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
485 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
486 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
487 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
488 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
489 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
490 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
491 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
492 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
493 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
494 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
495 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
496 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
497 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
498 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
499 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
500 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
501 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
502 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
503 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
504 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
505 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
506 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
507 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
508 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
509 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
510 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
511 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
512 {R_0286D8_SPI_INPUT_Z, 0, 0},
513 {GROUP_FORCE_NEW_BLOCK, 0, 0},
514 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
515 {GROUP_FORCE_NEW_BLOCK, 0, 0},
516 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
517 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
518 {R_028408_VGT_INDX_OFFSET, 0, 0},
519 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
520 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
521 };
522
523 /* SHADER RESOURCE R600/R700 */
524 int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base)
525 {
526 int i;
527 struct r600_block *block;
528 range->blocks = calloc(nblocks, sizeof(struct r600_block *));
529 if (range->blocks == NULL)
530 return -ENOMEM;
531
532 reg[0].offset += offset;
533 for (i = 0; i < nblocks; i++) {
534 block = calloc(1, sizeof(struct r600_block));
535 if (block == NULL) {
536 return -ENOMEM;
537 }
538 ctx->nblocks++;
539 range->blocks[i] = block;
540 r600_init_block(ctx, block, reg, 0, nreg, PKT3_SET_RESOURCE, offset_base);
541
542 reg[0].offset += stride;
543 }
544 return 0;
545 }
546
547
548 static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
549 {
550 struct r600_reg r600_shader_resource[] = {
551 {R_038000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, 0},
552 {R_038004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, 0},
553 {R_038008_RESOURCE0_WORD2, 0, 0},
554 {R_03800C_RESOURCE0_WORD3, 0, 0},
555 {R_038010_RESOURCE0_WORD4, 0, 0},
556 {R_038014_RESOURCE0_WORD5, 0, 0},
557 {R_038018_RESOURCE0_WORD6, 0, 0},
558 };
559 unsigned nreg = Elements(r600_shader_resource);
560
561 return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, R600_RESOURCE_OFFSET);
562 }
563
564 /* SHADER SAMPLER R600/R700/EG/CM */
565 int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset)
566 {
567 struct r600_reg r600_shader_sampler[] = {
568 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0},
569 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0},
570 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0},
571 };
572 unsigned nreg = Elements(r600_shader_sampler);
573
574 for (int i = 0; i < nreg; i++) {
575 r600_shader_sampler[i].offset += offset;
576 }
577 return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET);
578 }
579
580 /* SHADER SAMPLER BORDER R600/R700 */
581 static int r600_state_sampler_border_init(struct r600_context *ctx, uint32_t offset)
582 {
583 struct r600_reg r600_shader_sampler_border[] = {
584 {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0},
585 {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0},
586 {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0},
587 {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0},
588 };
589 unsigned nreg = Elements(r600_shader_sampler_border);
590
591 for (int i = 0; i < nreg; i++) {
592 r600_shader_sampler_border[i].offset += offset;
593 }
594 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
595 }
596
597 static int r600_loop_const_init(struct r600_context *ctx, uint32_t offset)
598 {
599 unsigned nreg = 32;
600 struct r600_reg r600_loop_consts[32];
601 int i;
602
603 for (i = 0; i < nreg; i++) {
604 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
605 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
606 r600_loop_consts[i].sbu_flags = 0;
607 }
608 return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET);
609 }
610
611 static void r600_free_resource_range(struct r600_context *ctx, struct r600_range *range, int nblocks)
612 {
613 struct r600_block *block;
614 int i;
615
616 if (!range->blocks) {
617 return; /* nothing to do */
618 }
619
620 for (i = 0; i < nblocks; i++) {
621 block = range->blocks[i];
622 if (block) {
623 for (int k = 1; k <= block->nbo; k++)
624 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
625 free(block);
626 }
627 }
628 free(range->blocks);
629 }
630
631 /* initialize */
632 void r600_context_fini(struct r600_context *ctx)
633 {
634 struct r600_block *block;
635 struct r600_range *range;
636
637 if (ctx->range) {
638 for (int i = 0; i < NUM_RANGES; i++) {
639 if (!ctx->range[i].blocks)
640 continue;
641 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
642 block = ctx->range[i].blocks[j];
643 if (block) {
644 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
645 range = &ctx->range[CTX_RANGE_ID(offset)];
646 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
647 }
648 for (int k = 1; k <= block->nbo; k++) {
649 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
650 }
651 free(block);
652 }
653 }
654 free(ctx->range[i].blocks);
655 }
656 }
657 r600_free_resource_range(ctx, &ctx->ps_resources, ctx->num_ps_resources);
658 r600_free_resource_range(ctx, &ctx->vs_resources, ctx->num_vs_resources);
659 r600_free_resource_range(ctx, &ctx->fs_resources, ctx->num_fs_resources);
660 free(ctx->blocks);
661 }
662
663 static void r600_add_resource_block(struct r600_context *ctx, struct r600_range *range, int num_blocks, int *index)
664 {
665 int c = *index;
666 for (int j = 0; j < num_blocks; j++) {
667 if (!range->blocks[j])
668 continue;
669
670 ctx->blocks[c++] = range->blocks[j];
671 }
672 *index = c;
673 }
674
675 int r600_setup_block_table(struct r600_context *ctx)
676 {
677 /* setup block table */
678 int c = 0;
679 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
680 if (!ctx->blocks)
681 return -ENOMEM;
682 for (int i = 0; i < NUM_RANGES; i++) {
683 if (!ctx->range[i].blocks)
684 continue;
685 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
686 if (!ctx->range[i].blocks[j])
687 continue;
688
689 add = 1;
690 for (int k = 0; k < c; k++) {
691 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
692 add = 0;
693 break;
694 }
695 }
696 if (add) {
697 assert(c < ctx->nblocks);
698 ctx->blocks[c++] = ctx->range[i].blocks[j];
699 j += (ctx->range[i].blocks[j]->nreg) - 1;
700 }
701 }
702 }
703
704 r600_add_resource_block(ctx, &ctx->ps_resources, ctx->num_ps_resources, &c);
705 r600_add_resource_block(ctx, &ctx->vs_resources, ctx->num_vs_resources, &c);
706 r600_add_resource_block(ctx, &ctx->fs_resources, ctx->num_fs_resources, &c);
707 return 0;
708 }
709
710 int r600_context_init(struct r600_context *ctx)
711 {
712 int r;
713
714 /* add blocks */
715 r = r600_context_add_block(ctx, r600_config_reg_list,
716 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
717 if (r)
718 goto out_err;
719 r = r600_context_add_block(ctx, r600_context_reg_list,
720 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
721 if (r)
722 goto out_err;
723 r = r600_context_add_block(ctx, r600_ctl_const_list,
724 Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
725 if (r)
726 goto out_err;
727
728 /* PS SAMPLER BORDER */
729 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
730 r = r600_state_sampler_border_init(ctx, offset);
731 if (r)
732 goto out_err;
733 }
734
735 /* VS SAMPLER BORDER */
736 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
737 r = r600_state_sampler_border_init(ctx, offset);
738 if (r)
739 goto out_err;
740 }
741 /* PS SAMPLER */
742 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
743 r = r600_state_sampler_init(ctx, offset);
744 if (r)
745 goto out_err;
746 }
747 /* VS SAMPLER */
748 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
749 r = r600_state_sampler_init(ctx, offset);
750 if (r)
751 goto out_err;
752 }
753
754 ctx->num_ps_resources = 160;
755 ctx->num_vs_resources = 160;
756 ctx->num_fs_resources = 16;
757 r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 160, 0x1c);
758 if (r)
759 goto out_err;
760 r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1180, 160, 0x1c);
761 if (r)
762 goto out_err;
763 r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x2300, 16, 0x1c);
764 if (r)
765 goto out_err;
766
767 /* PS loop const */
768 r600_loop_const_init(ctx, 0);
769 /* VS loop const */
770 r600_loop_const_init(ctx, 32);
771
772 r = r600_setup_block_table(ctx);
773 if (r)
774 goto out_err;
775
776 ctx->max_db = 4;
777 return 0;
778 out_err:
779 r600_context_fini(ctx);
780 return r;
781 }
782
783 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
784 boolean count_draw_in)
785 {
786 struct r600_atom *state;
787
788 /* The number of dwords we already used in the CS so far. */
789 num_dw += ctx->cs->cdw;
790
791 if (count_draw_in) {
792 /* The number of dwords all the dirty states would take. */
793 LIST_FOR_EACH_ENTRY(state, &ctx->dirty_states, head) {
794 num_dw += state->num_dw;
795 }
796
797 num_dw += ctx->pm4_dirty_cdwords;
798
799 /* The upper-bound of how much a draw command would take. */
800 num_dw += R600_MAX_DRAW_CS_DWORDS;
801 }
802
803 /* Count in queries_suspend. */
804 num_dw += ctx->num_cs_dw_nontimer_queries_suspend;
805 num_dw += ctx->num_cs_dw_timer_queries_suspend;
806
807 /* Count in streamout_end at the end of CS. */
808 num_dw += ctx->num_cs_dw_streamout_end;
809
810 /* Count in render_condition(NULL) at the end of CS. */
811 if (ctx->predicate_drawing) {
812 num_dw += 3;
813 }
814
815 /* Count in framebuffer cache flushes at the end of CS. */
816 num_dw += 7; /* one SURFACE_SYNC and CACHE_FLUSH_AND_INV (r6xx-only) */
817
818 /* Save 16 dwords for the fence mechanism. */
819 num_dw += 16;
820
821 /* Flush if there's not enough space. */
822 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
823 r600_flush(&ctx->context, NULL, RADEON_FLUSH_ASYNC);
824 }
825 }
826
827 void r600_context_dirty_block(struct r600_context *ctx,
828 struct r600_block *block,
829 int dirty, int index)
830 {
831 if ((index + 1) > block->nreg_dirty)
832 block->nreg_dirty = index + 1;
833
834 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
835 block->status |= R600_BLOCK_STATUS_DIRTY;
836 ctx->pm4_dirty_cdwords += block->pm4_ndwords;
837 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
838 block->status |= R600_BLOCK_STATUS_ENABLED;
839 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
840 }
841 LIST_ADDTAIL(&block->list,&ctx->dirty);
842
843 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
844 r600_context_ps_partial_flush(ctx);
845 }
846 }
847 }
848
849 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
850 {
851 struct r600_block *block;
852 int dirty;
853 for (int i = 0; i < state->nregs; i++) {
854 unsigned id, reloc_id;
855 struct r600_pipe_reg *reg = &state->regs[i];
856
857 block = reg->block;
858 id = reg->id;
859
860 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
861
862 if (reg->value != block->reg[id]) {
863 block->reg[id] = reg->value;
864 dirty |= R600_BLOCK_STATUS_DIRTY;
865 }
866 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
867 dirty |= R600_BLOCK_STATUS_DIRTY;
868 if (block->pm4_bo_index[id]) {
869 /* find relocation */
870 reloc_id = block->pm4_bo_index[id];
871 pipe_resource_reference((struct pipe_resource**)&block->reloc[reloc_id].bo, &reg->bo->b.b.b);
872 block->reloc[reloc_id].bo_usage = reg->bo_usage;
873 /* always force dirty for relocs for now */
874 dirty |= R600_BLOCK_STATUS_DIRTY;
875 }
876
877 if (dirty)
878 r600_context_dirty_block(ctx, block, dirty, id);
879 }
880 }
881
882 static void r600_context_dirty_resource_block(struct r600_context *ctx,
883 struct r600_block *block,
884 int dirty, int index)
885 {
886 block->nreg_dirty = index + 1;
887
888 if ((dirty != (block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
889 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
890 ctx->pm4_dirty_cdwords += block->pm4_ndwords;
891 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
892 block->status |= R600_BLOCK_STATUS_ENABLED;
893 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
894 }
895 LIST_ADDTAIL(&block->list,&ctx->resource_dirty);
896 }
897 }
898
899 void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block)
900 {
901 int dirty;
902 int num_regs = ctx->chip_class >= EVERGREEN ? 8 : 7;
903 boolean is_vertex;
904
905 if (state == NULL) {
906 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_RESOURCE_DIRTY);
907 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, NULL);
908 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL);
909 LIST_DELINIT(&block->list);
910 LIST_DELINIT(&block->enable_list);
911 return;
912 }
913
914 is_vertex = ((state->val[num_regs-1] & 0xc0000000) == 0xc0000000);
915 dirty = block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY;
916
917 if (memcmp(block->reg, state->val, num_regs*4)) {
918 memcpy(block->reg, state->val, num_regs * 4);
919 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
920 }
921
922 /* if no BOs on block, force dirty */
923 if (!block->reloc[1].bo || !block->reloc[2].bo)
924 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
925
926 if (!dirty) {
927 if (is_vertex) {
928 if (block->reloc[1].bo->buf != state->bo[0]->buf)
929 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
930 } else {
931 if ((block->reloc[1].bo->buf != state->bo[0]->buf) ||
932 (block->reloc[2].bo->buf != state->bo[1]->buf))
933 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
934 }
935 }
936
937 if (dirty) {
938 if (is_vertex) {
939 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
940 * we have single case btw VERTEX & TEXTURE resource
941 */
942 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b);
943 block->reloc[1].bo_usage = state->bo_usage[0];
944 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL);
945 } else {
946 /* TEXTURE RESOURCE */
947 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b);
948 block->reloc[1].bo_usage = state->bo_usage[0];
949 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, &state->bo[1]->b.b.b);
950 block->reloc[2].bo_usage = state->bo_usage[1];
951 }
952
953 if (is_vertex)
954 block->status |= R600_BLOCK_STATUS_RESOURCE_VERTEX;
955 else
956 block->status &= ~R600_BLOCK_STATUS_RESOURCE_VERTEX;
957
958 r600_context_dirty_resource_block(ctx, block, dirty, num_regs - 1);
959 }
960 }
961
962 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
963 {
964 struct r600_block *block = ctx->ps_resources.blocks[rid];
965
966 r600_context_pipe_state_set_resource(ctx, state, block);
967 }
968
969 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
970 {
971 struct r600_block *block = ctx->vs_resources.blocks[rid];
972
973 r600_context_pipe_state_set_resource(ctx, state, block);
974 }
975
976 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
977 {
978 struct r600_block *block = ctx->fs_resources.blocks[rid];
979
980 r600_context_pipe_state_set_resource(ctx, state, block);
981 }
982
983 void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
984 {
985 struct r600_range *range;
986 struct r600_block *block;
987 int i;
988 int dirty;
989
990 range = &ctx->range[CTX_RANGE_ID(offset)];
991 block = range->blocks[CTX_BLOCK_ID(offset)];
992 if (state == NULL) {
993 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
994 LIST_DELINIT(&block->list);
995 LIST_DELINIT(&block->enable_list);
996 return;
997 }
998 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
999
1000 for (i = 0; i < 3; i++) {
1001 if (block->reg[i] != state->regs[i].value) {
1002 block->reg[i] = state->regs[i].value;
1003 dirty |= R600_BLOCK_STATUS_DIRTY;
1004 }
1005 }
1006
1007 if (dirty)
1008 r600_context_dirty_block(ctx, block, dirty, 2);
1009 }
1010
1011 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1012 {
1013 struct r600_range *range;
1014 struct r600_block *block;
1015 int i;
1016 int dirty;
1017
1018 range = &ctx->range[CTX_RANGE_ID(offset)];
1019 block = range->blocks[CTX_BLOCK_ID(offset)];
1020 if (state == NULL) {
1021 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1022 LIST_DELINIT(&block->list);
1023 LIST_DELINIT(&block->enable_list);
1024 return;
1025 }
1026 if (state->nregs <= 3) {
1027 return;
1028 }
1029 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1030 for (i = 0; i < 4; i++) {
1031 if (block->reg[i] != state->regs[i + 3].value) {
1032 block->reg[i] = state->regs[i + 3].value;
1033 dirty |= R600_BLOCK_STATUS_DIRTY;
1034 }
1035 }
1036
1037 /* We have to flush the shaders before we change the border color
1038 * registers, or previous draw commands that haven't completed yet
1039 * will end up using the new border color. */
1040 if (dirty & R600_BLOCK_STATUS_DIRTY)
1041 r600_context_ps_partial_flush(ctx);
1042 if (dirty)
1043 r600_context_dirty_block(ctx, block, dirty, 3);
1044 }
1045
1046 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1047 {
1048 unsigned offset;
1049
1050 offset = R_03C000_SQ_TEX_SAMPLER_WORD0_0 + 12*id;
1051 r600_context_pipe_state_set_sampler(ctx, state, offset);
1052 offset = R_00A400_TD_PS_SAMPLER0_BORDER_RED + 16*id;
1053 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1054 }
1055
1056 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1057 {
1058 unsigned offset;
1059
1060 offset = R_03C000_SQ_TEX_SAMPLER_WORD0_0 + 12*(id + 18);
1061 r600_context_pipe_state_set_sampler(ctx, state, offset);
1062 offset = R_00A600_TD_VS_SAMPLER0_BORDER_RED + 16*id;
1063 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1064 }
1065
1066 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1067 {
1068 struct radeon_winsys_cs *cs = ctx->cs;
1069 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
1070 int cp_dwords = block->pm4_ndwords, start_dword = 0;
1071 int new_dwords = 0;
1072 int nbo = block->nbo;
1073
1074 if (block->nreg_dirty == 0 && optional) {
1075 goto out;
1076 }
1077
1078 if (nbo) {
1079 for (int j = 0; j < block->nreg; j++) {
1080 if (block->pm4_bo_index[j]) {
1081 /* find relocation */
1082 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
1083 if (reloc->bo) {
1084 block->pm4[reloc->bo_pm4_index] =
1085 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage);
1086 } else {
1087 block->pm4[reloc->bo_pm4_index] = 0;
1088 }
1089 nbo--;
1090 if (nbo == 0)
1091 break;
1092
1093 }
1094 }
1095 }
1096
1097 optional &= (block->nreg_dirty != block->nreg);
1098 if (optional) {
1099 new_dwords = block->nreg_dirty;
1100 start_dword = cs->cdw;
1101 cp_dwords = new_dwords + 2;
1102 }
1103 memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4);
1104 cs->cdw += cp_dwords;
1105
1106 if (optional) {
1107 uint32_t newword;
1108
1109 newword = cs->buf[start_dword];
1110 newword &= PKT_COUNT_C;
1111 newword |= PKT_COUNT_S(new_dwords);
1112 cs->buf[start_dword] = newword;
1113 }
1114 out:
1115 block->status ^= R600_BLOCK_STATUS_DIRTY;
1116 block->nreg_dirty = 0;
1117 LIST_DELINIT(&block->list);
1118 }
1119
1120 void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1121 {
1122 struct radeon_winsys_cs *cs = ctx->cs;
1123 int cp_dwords = block->pm4_ndwords;
1124 int nbo = block->nbo;
1125
1126 if (block->status & R600_BLOCK_STATUS_RESOURCE_VERTEX) {
1127 nbo = 1;
1128 cp_dwords -= 2; /* don't copy the second NOP */
1129 }
1130
1131 for (int j = 0; j < nbo; j++) {
1132 if (block->pm4_bo_index[j]) {
1133 /* find relocation */
1134 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
1135 block->pm4[reloc->bo_pm4_index] =
1136 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage);
1137 }
1138 }
1139
1140 memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4);
1141 cs->cdw += cp_dwords;
1142
1143 block->status ^= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1144 block->nreg_dirty = 0;
1145 LIST_DELINIT(&block->list);
1146 }
1147
1148 void r600_inval_shader_cache(struct r600_context *ctx)
1149 {
1150 ctx->surface_sync_cmd.flush_flags |= S_0085F0_SH_ACTION_ENA(1);
1151 r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
1152 }
1153
1154 void r600_inval_texture_cache(struct r600_context *ctx)
1155 {
1156 ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
1157 r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
1158 }
1159
1160 void r600_inval_vertex_cache(struct r600_context *ctx)
1161 {
1162 if (ctx->family == CHIP_RV610 ||
1163 ctx->family == CHIP_RV620 ||
1164 ctx->family == CHIP_RS780 ||
1165 ctx->family == CHIP_RS880 ||
1166 ctx->family == CHIP_RV710 ||
1167 ctx->family == CHIP_CEDAR ||
1168 ctx->family == CHIP_PALM ||
1169 ctx->family == CHIP_SUMO ||
1170 ctx->family == CHIP_SUMO2 ||
1171 ctx->family == CHIP_CAICOS ||
1172 ctx->family == CHIP_CAYMAN) {
1173 /* Some GPUs don't have the vertex cache and must use the texture cache instead. */
1174 ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
1175 } else {
1176 ctx->surface_sync_cmd.flush_flags |= S_0085F0_VC_ACTION_ENA(1);
1177 }
1178 r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
1179 }
1180
1181 void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now)
1182 {
1183 if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
1184 return;
1185
1186 ctx->surface_sync_cmd.flush_flags |=
1187 r600_get_cb_flush_flags(ctx) |
1188 (ctx->framebuffer.zsbuf ? S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1) : 0);
1189
1190 if (flush_now) {
1191 r600_emit_atom(ctx, &ctx->surface_sync_cmd.atom);
1192 } else {
1193 r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
1194 }
1195
1196 /* Also add a complete cache flush to work around broken flushing on R6xx. */
1197 if (ctx->chip_class == R600) {
1198 if (flush_now) {
1199 r600_emit_atom(ctx, &ctx->r6xx_flush_and_inv_cmd);
1200 } else {
1201 r600_atom_dirty(ctx, &ctx->r6xx_flush_and_inv_cmd);
1202 }
1203 }
1204
1205 ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
1206 }
1207
1208 void r600_context_flush(struct r600_context *ctx, unsigned flags)
1209 {
1210 struct radeon_winsys_cs *cs = ctx->cs;
1211 struct r600_block *enable_block = NULL;
1212 bool timer_queries_suspended = false;
1213 bool nontimer_queries_suspended = false;
1214 bool streamout_suspended = false;
1215
1216 if (cs->cdw == ctx->start_cs_cmd.atom.num_dw)
1217 return;
1218
1219 /* suspend queries */
1220 if (ctx->num_cs_dw_timer_queries_suspend) {
1221 r600_suspend_timer_queries(ctx);
1222 timer_queries_suspended = true;
1223 }
1224 if (ctx->num_cs_dw_nontimer_queries_suspend) {
1225 r600_suspend_nontimer_queries(ctx);
1226 nontimer_queries_suspended = true;
1227 }
1228
1229 if (ctx->num_cs_dw_streamout_end) {
1230 r600_context_streamout_end(ctx);
1231 streamout_suspended = true;
1232 }
1233
1234 r600_flush_framebuffer(ctx, true);
1235
1236 /* partial flush is needed to avoid lockups on some chips with user fences */
1237 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1238 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1239
1240 /* force to keep tiling flags */
1241 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
1242
1243 /* Flush the CS. */
1244 ctx->ws->cs_flush(ctx->cs, flags);
1245
1246 ctx->pm4_dirty_cdwords = 0;
1247 ctx->flags = 0;
1248
1249 r600_emit_atom(ctx, &ctx->start_cs_cmd.atom);
1250 r600_atom_dirty(ctx, &ctx->db_misc_state.atom);
1251
1252 if (streamout_suspended) {
1253 ctx->streamout_start = TRUE;
1254 ctx->streamout_append_bitmask = ~0;
1255 }
1256
1257 /* resume queries */
1258 if (timer_queries_suspended) {
1259 r600_resume_timer_queries(ctx);
1260 }
1261 if (nontimer_queries_suspended) {
1262 r600_resume_nontimer_queries(ctx);
1263 }
1264
1265 /* set all valid group as dirty so they get reemited on
1266 * next draw command
1267 */
1268 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
1269 if (!(enable_block->flags & BLOCK_FLAG_RESOURCE)) {
1270 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
1271 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
1272 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
1273 }
1274 } else {
1275 if(!(enable_block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) {
1276 LIST_ADDTAIL(&enable_block->list,&ctx->resource_dirty);
1277 enable_block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1278 }
1279 }
1280 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
1281 enable_block->nreg_dirty = enable_block->nreg;
1282 }
1283 }
1284
1285 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
1286 {
1287 struct radeon_winsys_cs *cs = ctx->cs;
1288 uint64_t va;
1289
1290 r600_need_cs_space(ctx, 10, FALSE);
1291
1292 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
1293 va = va + (offset << 2);
1294
1295 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1296 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1297 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1298 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1299 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */
1300 /* DATA_SEL | INT_EN | ADDRESS_HI */
1301 cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF);
1302 cs->buf[cs->cdw++] = value; /* DATA_LO */
1303 cs->buf[cs->cdw++] = 0; /* DATA_HI */
1304 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1305 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE);
1306 }
1307
1308 static void r600_flush_vgt_streamout(struct r600_context *ctx)
1309 {
1310 struct radeon_winsys_cs *cs = ctx->cs;
1311
1312 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
1313 cs->buf[cs->cdw++] = (R_008490_CP_STRMOUT_CNTL - R600_CONFIG_REG_OFFSET) >> 2;
1314 cs->buf[cs->cdw++] = 0;
1315
1316 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1317 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
1318
1319 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
1320 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
1321 cs->buf[cs->cdw++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */
1322 cs->buf[cs->cdw++] = 0;
1323 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */
1324 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */
1325 cs->buf[cs->cdw++] = 4; /* poll interval */
1326 }
1327
1328 static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
1329 {
1330 struct radeon_winsys_cs *cs = ctx->cs;
1331
1332 if (buffer_enable_bit) {
1333 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1334 cs->buf[cs->cdw++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2;
1335 cs->buf[cs->cdw++] = S_028AB0_STREAMOUT(1);
1336
1337 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1338 cs->buf[cs->cdw++] = (R_028B20_VGT_STRMOUT_BUFFER_EN - R600_CONTEXT_REG_OFFSET) >> 2;
1339 cs->buf[cs->cdw++] = buffer_enable_bit;
1340 } else {
1341 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1342 cs->buf[cs->cdw++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2;
1343 cs->buf[cs->cdw++] = S_028AB0_STREAMOUT(0);
1344 }
1345 }
1346
1347 void r600_context_streamout_begin(struct r600_context *ctx)
1348 {
1349 struct radeon_winsys_cs *cs = ctx->cs;
1350 struct r600_so_target **t = ctx->so_targets;
1351 unsigned *stride_in_dw = ctx->vs_shader->so.stride;
1352 unsigned buffer_en, i, update_flags = 0;
1353 uint64_t va;
1354
1355 buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) |
1356 (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) |
1357 (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) |
1358 (ctx->num_so_targets >= 4 && t[3] ? 8 : 0);
1359
1360 ctx->num_cs_dw_streamout_end =
1361 12 + /* flush_vgt_streamout */
1362 util_bitcount(buffer_en) * 8 +
1363 3;
1364
1365 r600_need_cs_space(ctx,
1366 12 + /* flush_vgt_streamout */
1367 6 + /* enables */
1368 util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 +
1369 util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 +
1370 (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770 ? 2 : 0) +
1371 ctx->num_cs_dw_streamout_end, TRUE);
1372
1373 if (ctx->chip_class >= EVERGREEN) {
1374 evergreen_flush_vgt_streamout(ctx);
1375 evergreen_set_streamout_enable(ctx, buffer_en);
1376 } else {
1377 r600_flush_vgt_streamout(ctx);
1378 r600_set_streamout_enable(ctx, buffer_en);
1379 }
1380
1381 for (i = 0; i < ctx->num_so_targets; i++) {
1382 if (t[i]) {
1383 t[i]->stride_in_dw = stride_in_dw[i];
1384 t[i]->so_index = i;
1385 va = r600_resource_va(&ctx->screen->screen,
1386 (void*)t[i]->b.buffer);
1387
1388 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
1389
1390 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 3, 0);
1391 cs->buf[cs->cdw++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 +
1392 16*i - R600_CONTEXT_REG_OFFSET) >> 2;
1393 cs->buf[cs->cdw++] = (t[i]->b.buffer_offset +
1394 t[i]->b.buffer_size) >> 2; /* BUFFER_SIZE (in DW) */
1395 cs->buf[cs->cdw++] = stride_in_dw[i]; /* VTX_STRIDE (in DW) */
1396 cs->buf[cs->cdw++] = va >> 8; /* BUFFER_BASE */
1397
1398 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1399 cs->buf[cs->cdw++] =
1400 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
1401 RADEON_USAGE_WRITE);
1402
1403 if (ctx->streamout_append_bitmask & (1 << i)) {
1404 va = r600_resource_va(&ctx->screen->screen,
1405 (void*)t[i]->filled_size);
1406 /* Append. */
1407 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1408 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1409 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
1410 cs->buf[cs->cdw++] = 0; /* unused */
1411 cs->buf[cs->cdw++] = 0; /* unused */
1412 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1413 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1414
1415 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1416 cs->buf[cs->cdw++] =
1417 r600_context_bo_reloc(ctx, t[i]->filled_size,
1418 RADEON_USAGE_READ);
1419 } else {
1420 /* Start from the beginning. */
1421 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1422 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1423 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
1424 cs->buf[cs->cdw++] = 0; /* unused */
1425 cs->buf[cs->cdw++] = 0; /* unused */
1426 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
1427 cs->buf[cs->cdw++] = 0; /* unused */
1428 }
1429 }
1430 }
1431
1432 if (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770) {
1433 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
1434 cs->buf[cs->cdw++] = update_flags;
1435 }
1436 }
1437
1438 void r600_context_streamout_end(struct r600_context *ctx)
1439 {
1440 struct radeon_winsys_cs *cs = ctx->cs;
1441 struct r600_so_target **t = ctx->so_targets;
1442 unsigned i, flush_flags = 0;
1443 uint64_t va;
1444
1445 if (ctx->chip_class >= EVERGREEN) {
1446 evergreen_flush_vgt_streamout(ctx);
1447 } else {
1448 r600_flush_vgt_streamout(ctx);
1449 }
1450
1451 for (i = 0; i < ctx->num_so_targets; i++) {
1452 if (t[i]) {
1453 va = r600_resource_va(&ctx->screen->screen,
1454 (void*)t[i]->filled_size);
1455 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1456 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1457 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
1458 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
1459 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* dst address lo */
1460 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* dst address hi */
1461 cs->buf[cs->cdw++] = 0; /* unused */
1462 cs->buf[cs->cdw++] = 0; /* unused */
1463
1464 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1465 cs->buf[cs->cdw++] =
1466 r600_context_bo_reloc(ctx, t[i]->filled_size,
1467 RADEON_USAGE_WRITE);
1468
1469 flush_flags |= S_0085F0_SO0_DEST_BASE_ENA(1) << i;
1470 }
1471 }
1472
1473 if (ctx->chip_class >= EVERGREEN) {
1474 evergreen_set_streamout_enable(ctx, 0);
1475 } else {
1476 r600_set_streamout_enable(ctx, 0);
1477 }
1478
1479 /* This is needed to fix cache flushes on r600. */
1480 if (ctx->chip_class == R600) {
1481 if (ctx->family == CHIP_RV670 ||
1482 ctx->family == CHIP_RS780 ||
1483 ctx->family == CHIP_RS880) {
1484 flush_flags |= S_0085F0_DEST_BASE_0_ENA(1);
1485 }
1486
1487 r600_atom_dirty(ctx, &ctx->r6xx_flush_and_inv_cmd);
1488 }
1489
1490 /* Flush streamout caches. */
1491 ctx->surface_sync_cmd.flush_flags |= flush_flags;
1492 r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
1493
1494 ctx->num_cs_dw_streamout_end = 0;
1495
1496 #if 0
1497 for (i = 0; i < ctx->num_so_targets; i++) {
1498 if (!t[i])
1499 continue;
1500
1501 uint32_t *ptr = ctx->ws->buffer_map(t[i]->filled_size->buf, ctx->cs, RADEON_USAGE_READ);
1502 printf("FILLED_SIZE%i: %u\n", i, *ptr);
1503 ctx->ws->buffer_unmap(t[i]->filled_size->buf);
1504 }
1505 #endif
1506 }
1507
1508 void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t)
1509 {
1510 struct radeon_winsys_cs *cs = ctx->cs;
1511 uint64_t va = r600_resource_va(&ctx->screen->screen,
1512 (void*)t->filled_size);
1513
1514 r600_need_cs_space(ctx, 14 + 21, TRUE);
1515
1516 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1517 cs->buf[cs->cdw++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - R600_CONTEXT_REG_OFFSET) >> 2;
1518 cs->buf[cs->cdw++] = 0;
1519
1520 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1521 cs->buf[cs->cdw++] = (R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE - R600_CONTEXT_REG_OFFSET) >> 2;
1522 cs->buf[cs->cdw++] = t->stride_in_dw;
1523
1524 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1525 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1526 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1527 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1528 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1529 cs->buf[cs->cdw++] = 0; /* unused */
1530
1531 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1532 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, t->filled_size, RADEON_USAGE_READ);
1533 }