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[mesa.git] / src / gallium / drivers / r600 / r600_hw_states.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * 2010 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse
26 * Dave Airlie
27 */
28
29 #include <util/u_inlines.h>
30 #include <util/u_format.h>
31 #include <util/u_memory.h>
32 #include <util/u_blitter.h>
33 #include "util/u_pack_color.h"
34 #include "r600_screen.h"
35 #include "r600_context.h"
36 #include "r600_resource.h"
37 #include "r600_state_inlines.h"
38 #include "r600d.h"
39
40 static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
41 {
42 struct r600_screen *rscreen = rctx->screen;
43 int i;
44
45 radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
46 rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
47 rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
48 rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
49 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
50 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
51 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
52 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
53 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
54 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
55 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
56 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
57 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
58 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
59
60 for (i = 0; i < 8; i++) {
61 unsigned eqRGB = state->rt[i].rgb_func;
62 unsigned srcRGB = state->rt[i].rgb_src_factor;
63 unsigned dstRGB = state->rt[i].rgb_dst_factor;
64
65 unsigned eqA = state->rt[i].alpha_func;
66 unsigned srcA = state->rt[i].alpha_src_factor;
67 unsigned dstA = state->rt[i].alpha_dst_factor;
68 uint32_t bc = 0;
69
70 if (!state->rt[i].blend_enable)
71 continue;
72
73 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
74 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
75 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
76
77 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
78 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
79 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
80 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
81 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
82 }
83
84 rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
85 if (i == 0)
86 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
87 }
88
89 radeon_state_pm4(rstate);
90 }
91
92 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate,
93 const struct pipe_clip_state *state)
94 {
95 struct r600_screen *rscreen = rctx->screen;
96
97 radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
98
99 for (int i = 0; i < state->nr; i++) {
100 rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
101 rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
102 rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
103 rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
104 }
105 radeon_state_pm4(rstate);
106 }
107
108 static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
109 const struct pipe_framebuffer_state *state, int cb)
110 {
111 struct r600_screen *rscreen = rctx->screen;
112 struct r600_resource_texture *rtex;
113 struct r600_resource *rbuffer;
114 unsigned level = state->cbufs[cb]->level;
115 unsigned pitch, slice;
116 unsigned color_info;
117 unsigned format, swap, ntype;
118 const struct util_format_description *desc;
119
120 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
121 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
122 rbuffer = &rtex->resource;
123 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
124 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
125 rstate->nbo = 1;
126 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
127 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
128
129 ntype = 0;
130 desc = util_format_description(rtex->resource.base.b.format);
131 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
132 ntype = V_0280A0_NUMBER_SRGB;
133
134 format = r600_translate_colorformat(rtex->resource.base.b.format);
135 swap = r600_translate_colorswap(rtex->resource.base.b.format);
136
137 color_info = S_0280A0_FORMAT(format) |
138 S_0280A0_COMP_SWAP(swap) |
139 S_0280A0_BLEND_CLAMP(1) |
140 S_0280A0_SOURCE_FORMAT(1) |
141 S_0280A0_NUMBER_TYPE(ntype);
142
143 rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
144 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
145 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
146 S_028060_SLICE_TILE_MAX(slice);
147 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
148 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
149 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
150 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
151 radeon_state_pm4(rstate);
152 }
153
154 static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
155 const struct pipe_framebuffer_state *state)
156 {
157 struct r600_screen *rscreen = rctx->screen;
158 struct r600_resource_texture *rtex;
159 struct r600_resource *rbuffer;
160 unsigned level;
161 unsigned pitch, slice, format;
162
163 radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
164 if (state->zsbuf == NULL)
165 return;
166
167 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
168 rtex->tilled = 1;
169 rtex->array_mode = 2;
170 rtex->tile_type = 1;
171 rtex->depth = 1;
172 rbuffer = &rtex->resource;
173
174 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
175 rstate->nbo = 1;
176 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
177 level = state->zsbuf->level;
178 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
179 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
180 format = r600_translate_dbformat(state->zsbuf->texture->format);
181 rstate->states[R600_DB__DB_DEPTH_BASE] = state->zsbuf->offset >> 8;
182 rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
183 S_028010_FORMAT(format);
184 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
185 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
186 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
187 S_028000_SLICE_TILE_MAX(slice);
188 radeon_state_pm4(rstate);
189 }
190
191 static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
192 {
193 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
194 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
195 const struct pipe_clip_state *clip = NULL;
196 struct r600_screen *rscreen = rctx->screen;
197 float offset_units = 0, offset_scale = 0;
198 char depth = 0;
199 unsigned offset_db_fmt_cntl = 0;
200 unsigned tmp;
201 unsigned prov_vtx = 1;
202
203 if (rctx->clip)
204 clip = &rctx->clip->state.clip;
205 if (fb->zsbuf) {
206 offset_units = state->offset_units;
207 offset_scale = state->offset_scale * 12.0f;
208 switch (fb->zsbuf->texture->format) {
209 case PIPE_FORMAT_Z24X8_UNORM:
210 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
211 depth = -24;
212 offset_units *= 2.0f;
213 break;
214 case PIPE_FORMAT_Z32_FLOAT:
215 depth = -23;
216 offset_units *= 1.0f;
217 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
218 break;
219 case PIPE_FORMAT_Z16_UNORM:
220 depth = -16;
221 offset_units *= 4.0f;
222 break;
223 default:
224 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
225 return;
226 }
227 }
228 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
229
230 if (state->flatshade_first)
231 prov_vtx = 0;
232
233 rctx->flat_shade = state->flatshade;
234 radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
235 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
236 if (state->sprite_coord_enable) {
237 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
238 S_0286D4_PNT_SPRITE_ENA(1) |
239 S_0286D4_PNT_SPRITE_OVRD_X(2) |
240 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
241 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
242 S_0286D4_PNT_SPRITE_OVRD_W(1);
243 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
244 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
245 S_0286D4_PNT_SPRITE_TOP_1(1);
246 }
247 }
248 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
249 if (clip) {
250 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
251 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
252 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
253 }
254 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
255 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
256 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
257 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
258 S_028814_FACE(!state->front_ccw) |
259 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
260 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
261 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
262 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] =
263 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
264 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
265 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
266 /* point size 12.4 fixed point */
267 tmp = (unsigned)(state->point_size * 8.0);
268 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
269 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
270 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
271 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
272 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
273 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
274 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
275 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
276 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
277 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
278 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
279 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
280 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
281 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
282 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
283 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
284 radeon_state_pm4(rstate);
285 }
286
287 static void r600_scissor(struct r600_context *rctx, struct radeon_state *rstate)
288 {
289 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
290 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
291 struct r600_screen *rscreen = rctx->screen;
292 enum radeon_family family;
293 unsigned minx, maxx, miny, maxy;
294 u32 tl, br;
295
296 family = radeon_get_family(rctx->rw);
297
298 if (state == NULL) {
299 minx = 0;
300 miny = 0;
301 maxx = fb->cbufs[0]->width;
302 maxy = fb->cbufs[0]->height;
303 } else {
304 minx = state->minx;
305 miny = state->miny;
306 maxx = state->maxx;
307 maxy = state->maxy;
308 }
309 tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
310 br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
311 radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
312 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
313 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
314 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
315 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
316 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
317 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
318 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
319 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
320 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
321 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
322 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
323 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
324 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
325 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
326
327 if (family >= CHIP_RV770)
328 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
329
330 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
331 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
332 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
333 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
334 radeon_state_pm4(rstate);
335 }
336
337 static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
338 {
339 struct r600_screen *rscreen = rctx->screen;
340
341 radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
342 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
343 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
344 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
345 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
346 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
347 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
348 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
349 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
350 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
351 radeon_state_pm4(rstate);
352 }
353
354 static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
355 {
356 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
357 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
358 struct r600_screen *rscreen = rctx->screen;
359 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
360 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
361 struct r600_shader *rshader;
362 struct r600_query *rquery = NULL;
363 boolean query_running;
364 int i;
365
366 if (rctx->ps_shader == NULL) {
367 return;
368 }
369 radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
370
371 db_shader_control = 0;
372 db_shader_control |= S_02880C_DUAL_EXPORT_ENABLE(1);
373 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
374
375 rshader = &rctx->ps_shader->shader;
376 if (rshader->uses_kill)
377 db_shader_control |= S_02880C_KILL_ENABLE(1);
378 for (i = 0; i < rshader->noutput; i++) {
379 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
380 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
381 }
382 stencil_ref_mask = 0;
383 stencil_ref_mask_bf = 0;
384 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
385 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
386 S_028800_ZFUNC(state->depth.func);
387 /* set stencil enable */
388
389 if (state->stencil[0].enabled) {
390 db_depth_control |= S_028800_STENCIL_ENABLE(1);
391 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
392 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
393 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
394 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
395
396 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
397 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
398 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
399 if (state->stencil[1].enabled) {
400 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
401 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
402 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
403 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
404 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
405 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
406 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
407 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
408 }
409 }
410
411 alpha_test_control = 0;
412 alpha_ref = 0;
413 if (state->alpha.enabled) {
414 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
415 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
416 alpha_ref = fui(state->alpha.ref_value);
417 }
418
419 db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) |
420 S_028D0C_DEPTH_COMPRESS_DISABLE(1);
421 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
422 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
423 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
424
425 query_running = false;
426
427 LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
428 if (rquery->state & R600_QUERY_STATE_STARTED) {
429 query_running = true;
430 }
431 }
432
433 if (query_running) {
434 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
435 if (rscreen->chip_class == R700)
436 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
437 }
438
439 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
440 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
441 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
442 rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
443 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
444 rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
445 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
446 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
447 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
448 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
449 rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
450 rstate->states[R600_DSA__DB_RENDER_CONTROL] = db_render_control;
451 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = db_render_override;
452
453 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
454 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
455 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
456 radeon_state_pm4(rstate);
457 }
458
459
460 static INLINE u32 S_FIXED(float value, u32 frac_bits)
461 {
462 return value * (1 << frac_bits);
463 }
464
465 static void r600_sampler_border(struct r600_context *rctx, struct radeon_state *rstate,
466 const struct pipe_sampler_state *state, unsigned id)
467 {
468 struct r600_screen *rscreen = rctx->screen;
469 union util_color uc;
470
471 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
472
473 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER_BORDER, id, R600_SHADER_PS);
474 if (uc.ui) {
475 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED] = fui(state->border_color[0]);
476 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN] = fui(state->border_color[1]);
477 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE] = fui(state->border_color[2]);
478 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA] = fui(state->border_color[3]);
479 }
480 radeon_state_pm4(rstate);
481 }
482
483 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate,
484 const struct pipe_sampler_state *state, unsigned id)
485 {
486 struct r600_screen *rscreen = rctx->screen;
487 union util_color uc;
488
489 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
490
491 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
492 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
493 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
494 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
495 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
496 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
497 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
498 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
499 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
500 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
501 /* FIXME LOD it depends on texture base level ... */
502 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
503 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
504 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
505 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
506 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
507 radeon_state_pm4(rstate);
508
509 }
510
511
512 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
513 const struct pipe_sampler_view *view, unsigned id)
514 {
515 struct r600_context *rctx = r600_context(ctx);
516 struct r600_screen *rscreen = rctx->screen;
517 const struct util_format_description *desc;
518 struct r600_resource_texture *tmp;
519 struct r600_resource *rbuffer;
520 unsigned format;
521 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
522 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
523 int r;
524
525 rstate->cpm4 = 0;
526 swizzle[0] = view->swizzle_r;
527 swizzle[1] = view->swizzle_g;
528 swizzle[2] = view->swizzle_b;
529 swizzle[3] = view->swizzle_a;
530 format = r600_translate_texformat(view->texture->format,
531 swizzle,
532 &word4, &yuv_format);
533 if (format == ~0) {
534 return;
535 }
536 desc = util_format_description(view->texture->format);
537 if (desc == NULL) {
538 R600_ERR("unknow format %d\n", view->texture->format);
539 return;
540 }
541 radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
542 tmp = (struct r600_resource_texture*)view->texture;
543 rbuffer = &tmp->resource;
544 if (tmp->depth) {
545 r = r600_texture_from_depth(ctx, tmp, view->first_level);
546 if (r) {
547 return;
548 }
549 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], tmp->uncompressed);
550 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], tmp->uncompressed);
551 } else {
552 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
553 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
554 }
555 rstate->nbo = 2;
556 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
557 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
558 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
559 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
560
561 pitch = (tmp->pitch[0] / tmp->bpt);
562 pitch = (pitch + 0x7) & ~0x7;
563
564 /* FIXME properly handle first level != 0 */
565 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
566 S_038000_DIM(r600_tex_dim(view->texture->target)) |
567 S_038000_TILE_MODE(array_mode) |
568 S_038000_TILE_TYPE(tile_type) |
569 S_038000_PITCH((pitch / 8) - 1) |
570 S_038000_TEX_WIDTH(view->texture->width0 - 1);
571 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
572 S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
573 S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
574 S_038004_DATA_FORMAT(format);
575 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
576 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
577 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
578 word4 |
579 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
580 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
581 S_038010_REQUEST_SIZE(1) |
582 S_038010_BASE_LEVEL(view->first_level);
583 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
584 S_038014_LAST_LEVEL(view->last_level) |
585 S_038014_BASE_ARRAY(0) |
586 S_038014_LAST_ARRAY(0);
587 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
588 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
589 radeon_state_pm4(rstate);
590 }
591
592 static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
593 {
594 struct r600_screen *rscreen = rctx->screen;
595 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
596 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
597 uint32_t color_control, target_mask, shader_mask;
598 int i;
599
600 target_mask = 0;
601 shader_mask = 0;
602 color_control = S_028808_PER_MRT_BLEND(1);
603
604 for (i = 0; i < nr_cbufs; i++) {
605 shader_mask |= 0xf << (i * 4);
606 }
607
608 if (pbs->logicop_enable) {
609 color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20);
610 } else {
611 color_control |= (0xcc << 16);
612 }
613
614 if (pbs->independent_blend_enable) {
615 for (i = 0; i < nr_cbufs; i++) {
616 if (pbs->rt[i].blend_enable) {
617 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
618 }
619 target_mask |= (pbs->rt[i].colormask << (4 * i));
620 }
621 } else {
622 for (i = 0; i < nr_cbufs; i++) {
623 if (pbs->rt[0].blend_enable) {
624 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
625 }
626 target_mask |= (pbs->rt[0].colormask << (4 * i));
627 }
628 }
629 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
630 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
631 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
632 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
633 rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
634 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
635 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
636 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
637 rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
638 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
639 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
640 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
641 radeon_state_pm4(rstate);
642 }
643
644 static void r600_init_config(struct r600_context *rctx)
645 {
646 int ps_prio;
647 int vs_prio;
648 int gs_prio;
649 int es_prio;
650 int num_ps_gprs;
651 int num_vs_gprs;
652 int num_gs_gprs;
653 int num_es_gprs;
654 int num_temp_gprs;
655 int num_ps_threads;
656 int num_vs_threads;
657 int num_gs_threads;
658 int num_es_threads;
659 int num_ps_stack_entries;
660 int num_vs_stack_entries;
661 int num_gs_stack_entries;
662 int num_es_stack_entries;
663 enum radeon_family family;
664
665 family = radeon_get_family(rctx->rw);
666 ps_prio = 0;
667 vs_prio = 1;
668 gs_prio = 2;
669 es_prio = 3;
670 switch (family) {
671 case CHIP_R600:
672 num_ps_gprs = 192;
673 num_vs_gprs = 56;
674 num_temp_gprs = 4;
675 num_gs_gprs = 0;
676 num_es_gprs = 0;
677 num_ps_threads = 136;
678 num_vs_threads = 48;
679 num_gs_threads = 4;
680 num_es_threads = 4;
681 num_ps_stack_entries = 128;
682 num_vs_stack_entries = 128;
683 num_gs_stack_entries = 0;
684 num_es_stack_entries = 0;
685 break;
686 case CHIP_RV630:
687 case CHIP_RV635:
688 num_ps_gprs = 84;
689 num_vs_gprs = 36;
690 num_temp_gprs = 4;
691 num_gs_gprs = 0;
692 num_es_gprs = 0;
693 num_ps_threads = 144;
694 num_vs_threads = 40;
695 num_gs_threads = 4;
696 num_es_threads = 4;
697 num_ps_stack_entries = 40;
698 num_vs_stack_entries = 40;
699 num_gs_stack_entries = 32;
700 num_es_stack_entries = 16;
701 break;
702 case CHIP_RV610:
703 case CHIP_RV620:
704 case CHIP_RS780:
705 case CHIP_RS880:
706 default:
707 num_ps_gprs = 84;
708 num_vs_gprs = 36;
709 num_temp_gprs = 4;
710 num_gs_gprs = 0;
711 num_es_gprs = 0;
712 num_ps_threads = 136;
713 num_vs_threads = 48;
714 num_gs_threads = 4;
715 num_es_threads = 4;
716 num_ps_stack_entries = 40;
717 num_vs_stack_entries = 40;
718 num_gs_stack_entries = 32;
719 num_es_stack_entries = 16;
720 break;
721 case CHIP_RV670:
722 num_ps_gprs = 144;
723 num_vs_gprs = 40;
724 num_temp_gprs = 4;
725 num_gs_gprs = 0;
726 num_es_gprs = 0;
727 num_ps_threads = 136;
728 num_vs_threads = 48;
729 num_gs_threads = 4;
730 num_es_threads = 4;
731 num_ps_stack_entries = 40;
732 num_vs_stack_entries = 40;
733 num_gs_stack_entries = 32;
734 num_es_stack_entries = 16;
735 break;
736 case CHIP_RV770:
737 num_ps_gprs = 192;
738 num_vs_gprs = 56;
739 num_temp_gprs = 4;
740 num_gs_gprs = 0;
741 num_es_gprs = 0;
742 num_ps_threads = 188;
743 num_vs_threads = 60;
744 num_gs_threads = 0;
745 num_es_threads = 0;
746 num_ps_stack_entries = 256;
747 num_vs_stack_entries = 256;
748 num_gs_stack_entries = 0;
749 num_es_stack_entries = 0;
750 break;
751 case CHIP_RV730:
752 case CHIP_RV740:
753 num_ps_gprs = 84;
754 num_vs_gprs = 36;
755 num_temp_gprs = 4;
756 num_gs_gprs = 0;
757 num_es_gprs = 0;
758 num_ps_threads = 188;
759 num_vs_threads = 60;
760 num_gs_threads = 0;
761 num_es_threads = 0;
762 num_ps_stack_entries = 128;
763 num_vs_stack_entries = 128;
764 num_gs_stack_entries = 0;
765 num_es_stack_entries = 0;
766 break;
767 case CHIP_RV710:
768 num_ps_gprs = 192;
769 num_vs_gprs = 56;
770 num_temp_gprs = 4;
771 num_gs_gprs = 0;
772 num_es_gprs = 0;
773 num_ps_threads = 144;
774 num_vs_threads = 48;
775 num_gs_threads = 0;
776 num_es_threads = 0;
777 num_ps_stack_entries = 128;
778 num_vs_stack_entries = 128;
779 num_gs_stack_entries = 0;
780 num_es_stack_entries = 0;
781 break;
782 }
783 radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0);
784
785 rctx->config.states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
786 switch (family) {
787 case CHIP_RV610:
788 case CHIP_RV620:
789 case CHIP_RS780:
790 case CHIP_RS880:
791 case CHIP_RV710:
792 break;
793 default:
794 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
795 break;
796 }
797
798 if (!rctx->screen->use_mem_constant)
799 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
800
801 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
802 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
803 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
804 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
805 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
806
807 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
808 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
809 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
810 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
811
812 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
813 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
814 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
815
816 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
817 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
818 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
819 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
820 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
821
822 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
823 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
824 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
825
826 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
827 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
828 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
829
830 rctx->config.states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
831 rctx->config.states[R600_CONFIG__SX_MISC] = 0x00000000;
832
833 if (family >= CHIP_RV770) {
834 rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
835 rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
836 rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x00000000;
837 rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
838 rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000000;
839 rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
840 } else {
841 rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000;
842 rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000003;
843 rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x82000000;
844 rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x01020204;
845 rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
846 rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00004010;
847 }
848 rctx->config.states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
849 rctx->config.states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
850 rctx->config.states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
851 rctx->config.states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
852 rctx->config.states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
853 rctx->config.states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
854 rctx->config.states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
855 rctx->config.states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
856 rctx->config.states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
857 rctx->config.states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
858 rctx->config.states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
859 rctx->config.states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
860 rctx->config.states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
861 rctx->config.states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
862 rctx->config.states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
863 rctx->config.states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
864 rctx->config.states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
865 rctx->config.states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
866 rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
867 rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
868 rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
869 rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
870 rctx->config.states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
871 rctx->config.states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
872 rctx->config.states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
873 rctx->config.states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
874 rctx->config.states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
875 radeon_state_pm4(&rctx->config);
876 }
877
878 static int r600_vs_resource(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset,
879 uint32_t stride, uint32_t format)
880 {
881 struct radeon_state *vs_resource = &rctx->vs_resource[id];
882 struct r600_screen *rscreen = rctx->screen;
883
884 radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS);
885 radeon_ws_bo_reference(rscreen->rw, &vs_resource->bo[0], rbuffer->bo);
886 vs_resource->nbo = 1;
887 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
888 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->size - offset - 1;
889 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(stride) |
890 S_038008_DATA_FORMAT(format);
891 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
892 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
893 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
894 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
895 vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
896 vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
897 return radeon_state_pm4(vs_resource);
898 }
899
900 static int r600_draw_vgt_init(struct r600_draw *draw,
901 int vgt_draw_initiator)
902 {
903 struct r600_context *rctx = r600_context(draw->ctx);
904 struct r600_screen *rscreen = rctx->screen;
905 struct r600_resource *rbuffer = (struct r600_resource *)draw->index_buffer;
906 radeon_state_init(&draw->draw, rscreen->rw, R600_STATE_DRAW, 0, 0);
907 draw->draw.states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
908 draw->draw.states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
909 draw->draw.states[R600_DRAW__VGT_DMA_BASE] = draw->index_buffer_offset;
910 if (rbuffer) {
911 radeon_ws_bo_reference(rscreen->rw, &draw->draw.bo[0], rbuffer->bo);
912 draw->draw.placement[0] = RADEON_GEM_DOMAIN_GTT;
913 draw->draw.placement[1] = RADEON_GEM_DOMAIN_GTT;
914 draw->draw.nbo = 1;
915 }
916 return radeon_state_pm4(&draw->draw);
917 }
918
919 static int r600_draw_vgt_prim(struct r600_draw *draw,
920 uint32_t prim, uint32_t vgt_dma_index_type)
921 {
922 struct r600_context *rctx = r600_context(draw->ctx);
923 struct r600_screen *rscreen = rctx->screen;
924 radeon_state_init(&draw->vgt, rscreen->rw, R600_STATE_VGT, 0, 0);
925 draw->vgt.states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
926 draw->vgt.states[R600_VGT__VGT_MAX_VTX_INDX] = draw->max_index;
927 draw->vgt.states[R600_VGT__VGT_MIN_VTX_INDX] = draw->min_index;
928 draw->vgt.states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
929 draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
930 draw->vgt.states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
931 draw->vgt.states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
932 draw->vgt.states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
933 draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
934 draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
935 draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
936 return radeon_state_pm4(&draw->vgt);
937 }
938
939 static int r600_ps_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
940 struct radeon_state *state)
941 {
942 struct r600_screen *rscreen = rctx->screen;
943 const struct pipe_rasterizer_state *rasterizer;
944 struct r600_shader *rshader = &rpshader->shader;
945 unsigned i, tmp, exports_ps, num_cout;
946 boolean have_pos = FALSE, have_face = FALSE;
947
948 rasterizer = &rctx->rasterizer->state.rasterizer;
949
950 radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
951 for (i = 0; i < rshader->ninput; i++) {
952 tmp = S_028644_SEMANTIC(i);
953 tmp |= S_028644_SEL_CENTROID(1);
954 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
955 have_pos = TRUE;
956 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
957 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
958 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
959 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
960 }
961
962 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
963 have_face = TRUE;
964
965 if (rasterizer->sprite_coord_enable & (1 << i)) {
966 tmp |= S_028644_PT_SPRITE_TEX(1);
967 }
968 state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
969 }
970
971 exports_ps = 0;
972 num_cout = 0;
973 for (i = 0; i < rshader->noutput; i++) {
974 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
975 exports_ps |= 1;
976 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
977 exports_ps |= (1 << (num_cout+1));
978 num_cout++;
979 }
980 }
981 if (!exports_ps) {
982 /* always at least export 1 component per pixel */
983 exports_ps = 2;
984 }
985 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
986 S_0286CC_PERSP_GRADIENT_ENA(1);
987 if (have_pos) {
988 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] |= S_0286CC_POSITION_ENA(1) |
989 S_0286CC_BARYC_SAMPLE_CNTL(1);
990 state->states[R600_PS_SHADER__SPI_INPUT_Z] |= 1;
991 }
992
993 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
994 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] |= S_0286D0_FRONT_FACE_ENA(have_face);
995
996 state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
997 S_028868_STACK_SIZE(rshader->bc.nstack);
998 state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
999 radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
1000 state->nbo = 1;
1001 state->placement[0] = RADEON_GEM_DOMAIN_GTT;
1002 return radeon_state_pm4(state);
1003 }
1004
1005 static int r600_vs_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
1006 struct radeon_state *state)
1007 {
1008 struct r600_screen *rscreen = rctx->screen;
1009 struct r600_shader *rshader = &rpshader->shader;
1010 unsigned i, tmp;
1011
1012 radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
1013 for (i = 0; i < 10; i++) {
1014 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
1015 }
1016 /* so far never got proper semantic id from tgsi */
1017 for (i = 0; i < 32; i++) {
1018 tmp = i << ((i & 3) * 8);
1019 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
1020 }
1021 state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
1022 state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
1023 S_028868_STACK_SIZE(rshader->bc.nstack);
1024 radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
1025 radeon_ws_bo_reference(rscreen->rw, &state->bo[1], rpshader->bo);
1026 state->nbo = 2;
1027 state->placement[0] = RADEON_GEM_DOMAIN_GTT;
1028 state->placement[2] = RADEON_GEM_DOMAIN_GTT;
1029 return radeon_state_pm4(state);
1030 }
1031
1032 static void r600_texture_state_scissor(struct r600_screen *rscreen,
1033 struct r600_resource_texture *rtexture,
1034 unsigned level)
1035 {
1036 struct radeon_state *rstate = &rtexture->scissor[level];
1037 enum radeon_family family;
1038
1039 family = radeon_get_family(rscreen->rw);
1040
1041 radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
1042 /* set states (most default value are 0 and struct already
1043 * initialized to 0, thus avoid resetting them)
1044 */
1045 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
1046 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = 0x80000000;
1047 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
1048 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = 0x80000000;
1049 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
1050 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = 0x80000000;
1051 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
1052 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = 0x80000000;
1053 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
1054
1055 if (family >= CHIP_RV770)
1056 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
1057
1058 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
1059 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = 0x80000000;
1060 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
1061 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = 0x80000000;
1062 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
1063 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = 0x80000000;
1064 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
1065 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = 0x80000000;
1066
1067 radeon_state_pm4(rstate);
1068 }
1069
1070 static void r600_texture_state_cb(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
1071 {
1072 struct radeon_state *rstate;
1073 struct r600_resource *rbuffer;
1074 unsigned pitch, slice;
1075 unsigned color_info;
1076 unsigned format, swap, ntype;
1077 const struct util_format_description *desc;
1078
1079 rstate = &rtexture->cb[cb][level];
1080 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
1081 rbuffer = &rtexture->resource;
1082
1083 /* set states (most default value are 0 and struct already
1084 * initialized to 0, thus avoid resetting them)
1085 */
1086 pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
1087 slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
1088 ntype = 0;
1089 desc = util_format_description(rbuffer->base.b.format);
1090 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1091 ntype = V_0280A0_NUMBER_SRGB;
1092 format = r600_translate_colorformat(rtexture->resource.base.b.format);
1093 swap = r600_translate_colorswap(rtexture->resource.base.b.format);
1094 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
1095 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rtexture->uncompressed);
1096 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rtexture->uncompressed);
1097 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[2], rtexture->uncompressed);
1098 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1099 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1100 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
1101 rstate->nbo = 3;
1102 color_info = 0;
1103 } else {
1104 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
1105 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
1106 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[2], rbuffer->bo);
1107 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1108 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1109 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
1110 rstate->nbo = 3;
1111 color_info = S_0280A0_SOURCE_FORMAT(1);
1112 }
1113 color_info |= S_0280A0_FORMAT(format) |
1114 S_0280A0_COMP_SWAP(swap) |
1115 S_0280A0_BLEND_CLAMP(1) |
1116 S_0280A0_NUMBER_TYPE(ntype);
1117 rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
1118 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
1119 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
1120 S_028060_SLICE_TILE_MAX(slice);
1121
1122 radeon_state_pm4(rstate);
1123 }
1124
1125 static void r600_texture_state_db(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
1126 {
1127 struct radeon_state *rstate = &rtexture->db[level];
1128 struct r600_resource *rbuffer;
1129 unsigned pitch, slice, format;
1130
1131 radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
1132 rbuffer = &rtexture->resource;
1133 rtexture->tilled = 1;
1134 rtexture->array_mode = 2;
1135 rtexture->tile_type = 1;
1136 rtexture->depth = 1;
1137
1138 /* set states (most default value are 0 and struct already
1139 * initialized to 0, thus avoid resetting them)
1140 */
1141 pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
1142 slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
1143 format = r600_translate_dbformat(rbuffer->base.b.format);
1144 rstate->states[R600_DB__DB_DEPTH_BASE] = rtexture->offset[level] >> 8;
1145 rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtexture->array_mode) |
1146 S_028010_FORMAT(format);
1147 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
1148 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
1149 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
1150 S_028000_SLICE_TILE_MAX(slice);
1151 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
1152 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1153 rstate->nbo = 1;
1154
1155 radeon_state_pm4(rstate);
1156 }
1157
1158 static void r600_texture_state_viewport(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
1159 {
1160 struct radeon_state *rstate = &rtexture->viewport[level];
1161
1162 radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
1163
1164 /* set states (most default value are 0 and struct already
1165 * initialized to 0, thus avoid resetting them)
1166 */
1167 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui((float)rtexture->width[level]/2.0);
1168 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui((float)rtexture->width[level]/2.0);
1169 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui((float)rtexture->height[level]/2.0);
1170 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui((float)-rtexture->height[level]/2.0);
1171 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = 0x3F000000;
1172 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = 0x3F000000;
1173 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
1174 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
1175
1176 radeon_state_pm4(rstate);
1177 }
1178
1179 struct r600_context_hw_state_vtbl r600_hw_state_vtbl = {
1180 .blend = r600_blend,
1181 .ucp = r600_ucp,
1182 .cb = r600_cb,
1183 .db = r600_db,
1184 .rasterizer = r600_rasterizer,
1185 .scissor = r600_scissor,
1186 .viewport = r600_viewport,
1187 .dsa = r600_dsa,
1188 .sampler_border = r600_sampler_border,
1189 .sampler = r600_sampler,
1190 .resource = r600_resource,
1191 .cb_cntl = r600_cb_cntl,
1192 .vs_resource = r600_vs_resource,
1193 .vgt_init = r600_draw_vgt_init,
1194 .vgt_prim = r600_draw_vgt_prim,
1195 .vs_shader = r600_vs_shader,
1196 .ps_shader = r600_ps_shader,
1197 .init_config = r600_init_config,
1198 .texture_state_viewport = r600_texture_state_viewport,
1199 .texture_state_db = r600_texture_state_db,
1200 .texture_state_cb = r600_texture_state_cb,
1201 .texture_state_scissor = r600_texture_state_scissor,
1202 };
1203
1204 void r600_set_constant_buffer_file(struct pipe_context *ctx,
1205 uint shader, uint index,
1206 struct pipe_resource *buffer)
1207 {
1208 struct r600_screen *rscreen = r600_screen(ctx->screen);
1209 struct r600_context *rctx = r600_context(ctx);
1210 unsigned nconstant = 0, i, type, shader_class;
1211 struct radeon_state *rstate, *rstates;
1212 struct pipe_transfer *transfer;
1213 u32 *ptr;
1214
1215 type = R600_STATE_CONSTANT;
1216
1217 switch (shader) {
1218 case PIPE_SHADER_VERTEX:
1219 shader_class = R600_SHADER_VS;
1220 rstates = rctx->vs_constant;
1221 break;
1222 case PIPE_SHADER_FRAGMENT:
1223 shader_class = R600_SHADER_PS;
1224 rstates = rctx->ps_constant;
1225 break;
1226 default:
1227 R600_ERR("unsupported %d\n", shader);
1228 return;
1229 }
1230 if (buffer && buffer->width0 > 0) {
1231 nconstant = buffer->width0 / 16;
1232 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
1233 if (ptr == NULL)
1234 return;
1235 for (i = 0; i < nconstant; i++) {
1236 rstate = &rstates[i];
1237 radeon_state_init(rstate, rscreen->rw, type, i, shader_class);
1238 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
1239 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
1240 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
1241 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
1242 if (radeon_state_pm4(rstate))
1243 return;
1244 radeon_draw_bind(&rctx->draw, rstate);
1245 }
1246 pipe_buffer_unmap(ctx, buffer, transfer);
1247 }
1248 }
1249
1250 void r600_set_constant_buffer_mem(struct pipe_context *ctx,
1251 uint shader, uint index,
1252 struct pipe_resource *buffer)
1253 {
1254 struct r600_screen *rscreen = r600_screen(ctx->screen);
1255 struct r600_context *rctx = r600_context(ctx);
1256 unsigned nconstant = 0, type, shader_class, size;
1257 struct radeon_state *rstate, *rstates;
1258 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1259
1260 type = R600_STATE_CBUF;
1261
1262 switch (shader) {
1263 case PIPE_SHADER_VERTEX:
1264 shader_class = R600_SHADER_VS;
1265 rstates = rctx->vs_constant;
1266 break;
1267 case PIPE_SHADER_FRAGMENT:
1268 shader_class = R600_SHADER_PS;
1269 rstates = rctx->ps_constant;
1270 break;
1271 default:
1272 R600_ERR("unsupported %d\n", shader);
1273 return;
1274 }
1275
1276 rstate = &rstates[0];
1277
1278 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1279
1280 nconstant = buffer->width0 / 16;
1281 size = ALIGN_DIVUP(nconstant, 16);
1282
1283 radeon_state_init(rstate, rscreen->rw, type, 0, shader_class);
1284 rstate->states[R600_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0] = size;
1285 rstate->states[R600_VS_CBUF__ALU_CONST_CACHE_VS_0] = 0;
1286
1287 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
1288 rstate->nbo = 1;
1289 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
1290 if (radeon_state_pm4(rstate))
1291 return;
1292 radeon_draw_bind(&rctx->draw, rstate);
1293 }
1294