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r600g: move chip class to radeon common structure
[mesa.git] / src / gallium / drivers / r600 / r600_hw_states.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * 2010 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse
26 * Dave Airlie
27 */
28
29 #include <util/u_inlines.h>
30 #include <util/u_format.h>
31 #include <util/u_memory.h>
32 #include <util/u_blitter.h>
33 #include "util/u_pack_color.h"
34 #include "r600_screen.h"
35 #include "r600_context.h"
36 #include "r600_resource.h"
37 #include "r600_state_inlines.h"
38 #include "r600d.h"
39
40 static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
41 {
42 struct r600_screen *rscreen = rctx->screen;
43 int i;
44
45 radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
46 rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
47 rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
48 rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
49 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
50 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
51 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
52 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
53 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
54 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
55 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
56 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
57 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
58 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
59
60 for (i = 0; i < 8; i++) {
61 unsigned eqRGB = state->rt[i].rgb_func;
62 unsigned srcRGB = state->rt[i].rgb_src_factor;
63 unsigned dstRGB = state->rt[i].rgb_dst_factor;
64
65 unsigned eqA = state->rt[i].alpha_func;
66 unsigned srcA = state->rt[i].alpha_src_factor;
67 unsigned dstA = state->rt[i].alpha_dst_factor;
68 uint32_t bc = 0;
69
70 if (!state->rt[i].blend_enable)
71 continue;
72
73 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
74 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
75 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
76
77 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
78 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
79 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
80 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
81 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
82 }
83
84 rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
85 if (i == 0)
86 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
87 }
88
89 radeon_state_pm4(rstate);
90 }
91
92 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate,
93 const struct pipe_clip_state *state)
94 {
95 struct r600_screen *rscreen = rctx->screen;
96
97 radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
98
99 for (int i = 0; i < state->nr; i++) {
100 rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
101 rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
102 rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
103 rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
104 }
105 radeon_state_pm4(rstate);
106 }
107
108 static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
109 const struct pipe_framebuffer_state *state, int cb)
110 {
111 struct r600_screen *rscreen = rctx->screen;
112 struct r600_resource_texture *rtex;
113 struct r600_resource *rbuffer;
114 unsigned level = state->cbufs[cb]->level;
115 unsigned pitch, slice;
116 unsigned color_info;
117 unsigned format, swap, ntype;
118 const struct util_format_description *desc;
119
120 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
121 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
122 rbuffer = &rtex->resource;
123 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
124 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
125 rstate->nbo = 1;
126 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
127 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
128
129 ntype = 0;
130 desc = util_format_description(rtex->resource.base.b.format);
131 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
132 ntype = V_0280A0_NUMBER_SRGB;
133
134 format = r600_translate_colorformat(rtex->resource.base.b.format);
135 swap = r600_translate_colorswap(rtex->resource.base.b.format);
136
137 color_info = S_0280A0_FORMAT(format) |
138 S_0280A0_COMP_SWAP(swap) |
139 S_0280A0_BLEND_CLAMP(1) |
140 S_0280A0_SOURCE_FORMAT(1) |
141 S_0280A0_NUMBER_TYPE(ntype);
142
143 rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
144 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
145 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
146 S_028060_SLICE_TILE_MAX(slice);
147 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
148 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
149 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
150 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
151 radeon_state_pm4(rstate);
152 }
153
154 static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
155 const struct pipe_framebuffer_state *state)
156 {
157 struct r600_screen *rscreen = rctx->screen;
158 struct r600_resource_texture *rtex;
159 struct r600_resource *rbuffer;
160 unsigned level;
161 unsigned pitch, slice, format;
162
163 radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
164 if (state->zsbuf == NULL)
165 return;
166
167 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
168 rtex->tilled = 1;
169 rtex->array_mode = 2;
170 rtex->tile_type = 1;
171 rtex->depth = 1;
172 rbuffer = &rtex->resource;
173
174 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
175 rstate->nbo = 1;
176 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
177 level = state->zsbuf->level;
178 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
179 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
180 format = r600_translate_dbformat(state->zsbuf->texture->format);
181 rstate->states[R600_DB__DB_DEPTH_BASE] = state->zsbuf->offset >> 8;
182 rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
183 S_028010_FORMAT(format);
184 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
185 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
186 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
187 S_028000_SLICE_TILE_MAX(slice);
188 radeon_state_pm4(rstate);
189 }
190
191 static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
192 {
193 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
194 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
195 const struct pipe_clip_state *clip = NULL;
196 struct r600_screen *rscreen = rctx->screen;
197 float offset_units = 0, offset_scale = 0;
198 char depth = 0;
199 unsigned offset_db_fmt_cntl = 0;
200 unsigned point_size;
201 unsigned prov_vtx = 1;
202
203 if (rctx->clip)
204 clip = &rctx->clip->state.clip;
205 if (fb->zsbuf) {
206 offset_units = state->offset_units;
207 offset_scale = state->offset_scale * 12.0f;
208 switch (fb->zsbuf->texture->format) {
209 case PIPE_FORMAT_Z24X8_UNORM:
210 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
211 depth = -24;
212 offset_units *= 2.0f;
213 break;
214 case PIPE_FORMAT_Z32_FLOAT:
215 depth = -23;
216 offset_units *= 1.0f;
217 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
218 break;
219 case PIPE_FORMAT_Z16_UNORM:
220 depth = -16;
221 offset_units *= 4.0f;
222 break;
223 default:
224 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
225 return;
226 }
227 }
228 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
229
230 if (state->flatshade_first)
231 prov_vtx = 0;
232
233 rctx->flat_shade = state->flatshade;
234 radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
235 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] =
236 S_0286D4_FLAT_SHADE_ENA(1);
237 if (state->sprite_coord_enable) {
238 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
239 S_0286D4_PNT_SPRITE_ENA(1) |
240 S_0286D4_PNT_SPRITE_OVRD_X(2) |
241 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
242 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
243 S_0286D4_PNT_SPRITE_OVRD_W(1);
244 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
245 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
246 S_0286D4_PNT_SPRITE_TOP_1(1);
247 }
248 }
249 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
250 if (clip) {
251 /* Clip plane enable bits are stashed in the lower six bits of
252 * PA_CL_CLIP_CNTL, so just set all of the corresponding bits with a
253 * pinch of bit twiddling.
254 *
255 * PS_UCP_MODE 3 is "expand and clip as trifan," which is the same
256 * setting that we use on r300-r500. I believe that fglrx always uses
257 * this mode as well. */
258 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] =
259 ((1 << clip->nr) - 1) |
260 S_028810_PS_UCP_MODE(3) |
261 S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp) |
262 S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
263 }
264 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
265 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
266 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
267 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
268 S_028814_FACE(!state->front_ccw) |
269 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
270 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
271 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
272 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] =
273 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
274 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
275 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
276 /* Point size for PA_SU_POINT_SIZE and PA_SU_POINT_MINMAX is fixed-point,
277 * 12.4.
278 *
279 * For some reason, maximum point size is set to 0x8000 (2048.0) instead
280 * of the maximum value 0xFFF0 (4095.0). */
281 point_size = (unsigned)(state->point_size * 8.0);
282 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] =
283 S_028A00_HEIGHT(point_size) | S_028A00_WIDTH(point_size);
284 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] =
285 S_028A04_MIN_SIZE(0) | S_028A04_MAX_SIZE(0x8000);
286 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = S_028A08_WIDTH(8);
287 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
288 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
289 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = S_028C00_LAST_PIXEL(1);
290 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = fui(1);
291 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = fui(1);
292 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = fui(1);
293 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = fui(1);
294 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
295 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
296 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
297 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
298 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
299 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
300 radeon_state_pm4(rstate);
301 }
302
303 static void r600_scissor(struct r600_context *rctx, struct radeon_state *rstate)
304 {
305 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
306 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
307 struct r600_screen *rscreen = rctx->screen;
308 enum radeon_family family;
309 unsigned minx, maxx, miny, maxy;
310 u32 tl, br;
311
312 family = radeon_get_family(rctx->rw);
313
314 if (state == NULL) {
315 minx = 0;
316 miny = 0;
317 maxx = fb->cbufs[0]->width;
318 maxy = fb->cbufs[0]->height;
319 } else {
320 minx = state->minx;
321 miny = state->miny;
322 maxx = state->maxx;
323 maxy = state->maxy;
324 }
325 tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
326 br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
327 radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
328 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
329 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
330 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
331 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
332 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
333 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] =
334 S_02820C_CLIP_RULE(0xFFFF);
335 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
336 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
337 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
338 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
339 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
340 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
341 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
342 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
343
344 if (family >= CHIP_RV770)
345 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
346
347 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
348 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
349 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
350 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
351 radeon_state_pm4(rstate);
352 }
353
354 static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
355 {
356 struct r600_screen *rscreen = rctx->screen;
357
358 radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
359 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = fui(0);
360 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = fui(1);
361 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
362 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
363 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
364 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
365 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
366 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
367 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] =
368 S_028818_VPORT_X_SCALE_ENA(1) |
369 S_028818_VPORT_X_OFFSET_ENA(1) |
370 S_028818_VPORT_Y_SCALE_ENA(1) |
371 S_028818_VPORT_Y_OFFSET_ENA(1) |
372 S_028818_VPORT_Z_SCALE_ENA(1) |
373 S_028818_VPORT_Z_OFFSET_ENA(1) |
374 S_028818_VTX_W0_FMT(1);
375 radeon_state_pm4(rstate);
376 }
377
378 static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
379 {
380 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
381 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
382 struct r600_screen *rscreen = rctx->screen;
383 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
384 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
385 struct r600_shader *rshader;
386 struct r600_query *rquery = NULL;
387 boolean query_running;
388 int i;
389
390 if (rctx->ps_shader == NULL) {
391 return;
392 }
393 radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
394
395 db_shader_control = S_02880C_DUAL_EXPORT_ENABLE(1) |
396 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
397
398 rshader = &rctx->ps_shader->shader;
399 if (rshader->uses_kill)
400 db_shader_control |= S_02880C_KILL_ENABLE(1);
401 for (i = 0; i < rshader->noutput; i++) {
402 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
403 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
404 }
405 stencil_ref_mask = 0;
406 stencil_ref_mask_bf = 0;
407 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
408 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
409 S_028800_ZFUNC(state->depth.func);
410
411 /* set stencil enable */
412 if (state->stencil[0].enabled) {
413 db_depth_control |= S_028800_STENCIL_ENABLE(1) |
414 S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func)) |
415 S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)) |
416 S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)) |
417 S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
418
419 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
420 S_028430_STENCILWRITEMASK(state->stencil[0].writemask) |
421 S_028430_STENCILREF(stencil_ref->ref_value[0]);
422
423 if (state->stencil[1].enabled) {
424 db_depth_control |= S_028800_BACKFACE_ENABLE(1) |
425 S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func)) |
426 S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)) |
427 S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)) |
428 S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
429 stencil_ref_mask_bf =
430 S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
431 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask) |
432 S_028430_STENCILREF(stencil_ref->ref_value[1]);
433 }
434 }
435
436 alpha_test_control = 0;
437 alpha_ref = 0;
438 if (state->alpha.enabled) {
439 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func) |
440 S_028410_ALPHA_TEST_ENABLE(1);
441 alpha_ref = fui(state->alpha.ref_value);
442 }
443
444 db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) |
445 S_028D0C_DEPTH_COMPRESS_DISABLE(1);
446 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
447 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
448 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
449
450 query_running = FALSE;
451
452 LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
453 if (rquery->state & R600_QUERY_STATE_STARTED) {
454 query_running = TRUE;
455 }
456 }
457
458 if (query_running) {
459 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
460 if (radeon_get_family_class(rscreen->rw) == R700)
461 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
462 }
463
464 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
465 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = fui(1);
466 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
467 rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
468 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
469 rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
470 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
471 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
472 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
473 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
474 rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
475 rstate->states[R600_DSA__DB_RENDER_CONTROL] = db_render_control;
476 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = db_render_override;
477
478 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
479 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
480 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
481 radeon_state_pm4(rstate);
482 }
483
484
485 static INLINE u32 S_FIXED(float value, u32 frac_bits)
486 {
487 return value * (1 << frac_bits);
488 }
489
490 static void r600_sampler_border(struct r600_context *rctx, struct radeon_state *rstate,
491 const struct pipe_sampler_state *state, unsigned id)
492 {
493 struct r600_screen *rscreen = rctx->screen;
494 union util_color uc;
495
496 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
497
498 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER_BORDER, id, R600_SHADER_PS);
499 if (uc.ui) {
500 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED] = fui(state->border_color[0]);
501 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN] = fui(state->border_color[1]);
502 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE] = fui(state->border_color[2]);
503 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA] = fui(state->border_color[3]);
504 }
505 radeon_state_pm4(rstate);
506 }
507
508 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate,
509 const struct pipe_sampler_state *state, unsigned id)
510 {
511 struct r600_screen *rscreen = rctx->screen;
512 union util_color uc;
513
514 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
515
516 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
517 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
518 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
519 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
520 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
521 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
522 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
523 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
524 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
525 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
526 /* FIXME LOD it depends on texture base level ... */
527 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
528 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
529 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
530 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
531 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
532 radeon_state_pm4(rstate);
533
534 }
535
536
537 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
538 const struct pipe_sampler_view *view, unsigned id)
539 {
540 struct r600_context *rctx = r600_context(ctx);
541 struct r600_screen *rscreen = rctx->screen;
542 const struct util_format_description *desc;
543 struct r600_resource_texture *texture;
544 struct r600_resource *rbuffer;
545 unsigned format;
546 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
547 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
548 int r;
549
550 rstate->cpm4 = 0;
551 swizzle[0] = view->swizzle_r;
552 swizzle[1] = view->swizzle_g;
553 swizzle[2] = view->swizzle_b;
554 swizzle[3] = view->swizzle_a;
555 format = r600_translate_texformat(view->texture->format,
556 swizzle,
557 &word4, &yuv_format);
558 if (format == ~0) {
559 return;
560 }
561 desc = util_format_description(view->texture->format);
562 if (desc == NULL) {
563 R600_ERR("unknow format %d\n", view->texture->format);
564 return;
565 }
566 radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
567 texture = (struct r600_resource_texture*)view->texture;
568 rbuffer = &texture->resource;
569 if (texture->depth) {
570 r = r600_texture_from_depth(ctx, texture, view->first_level);
571 if (r) {
572 return;
573 }
574 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], texture->uncompressed);
575 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], texture->uncompressed);
576 } else {
577 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
578 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
579 }
580 rstate->nbo = 2;
581 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
582 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
583 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
584 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
585
586 pitch = align(texture->pitch[0] / texture->bpt, 8);
587
588 /* FIXME properly handle first level != 0 */
589 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
590 S_038000_DIM(r600_tex_dim(view->texture->target)) |
591 S_038000_TILE_MODE(array_mode) |
592 S_038000_TILE_TYPE(tile_type) |
593 S_038000_PITCH((pitch / 8) - 1) |
594 S_038000_TEX_WIDTH(view->texture->width0 - 1);
595 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
596 S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
597 S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
598 S_038004_DATA_FORMAT(format);
599 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = texture->offset[0] >> 8;
600 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = texture->offset[1] >> 8;
601 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
602 word4 |
603 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
604 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
605 S_038010_REQUEST_SIZE(1) |
606 S_038010_BASE_LEVEL(view->first_level);
607 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
608 S_038014_LAST_LEVEL(view->last_level) |
609 S_038014_BASE_ARRAY(0) |
610 S_038014_LAST_ARRAY(0);
611 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
612 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
613 radeon_state_pm4(rstate);
614 }
615
616 static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
617 {
618 struct r600_screen *rscreen = rctx->screen;
619 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
620 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
621 uint32_t color_control, target_mask, shader_mask, shader_control;
622 int i;
623
624 target_mask = 0;
625 shader_mask = 0;
626 shader_control = 0;
627 color_control = S_028808_PER_MRT_BLEND(1);
628
629 for (i = 0; i < nr_cbufs; i++) {
630 shader_mask |= 0xf << (i * 4);
631 shader_control |= (1 << i);
632 }
633
634 if (pbs->logicop_enable) {
635 color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20);
636 } else {
637 color_control |= (0xcc << 16);
638 }
639
640 if (pbs->independent_blend_enable) {
641 for (i = 0; i < nr_cbufs; i++) {
642 if (pbs->rt[i].blend_enable) {
643 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
644 }
645 target_mask |= (pbs->rt[i].colormask << (4 * i));
646 }
647 } else {
648 for (i = 0; i < nr_cbufs; i++) {
649 if (pbs->rt[0].blend_enable) {
650 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
651 }
652 target_mask |= (pbs->rt[0].colormask << (4 * i));
653 }
654 }
655 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
656 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
657 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
658 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
659 if (radeon_get_family_class(rscreen->rw) == R700)
660 rstate->states[R600_CB_CNTL__CB_SHADER_CONTROL] = shader_control;
661 rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
662 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
663 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
664 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
665 rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
666 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
667 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
668 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
669 radeon_state_pm4(rstate);
670 }
671
672 static void r600_init_config(struct r600_context *rctx)
673 {
674 int ps_prio;
675 int vs_prio;
676 int gs_prio;
677 int es_prio;
678 int num_ps_gprs;
679 int num_vs_gprs;
680 int num_gs_gprs;
681 int num_es_gprs;
682 int num_temp_gprs;
683 int num_ps_threads;
684 int num_vs_threads;
685 int num_gs_threads;
686 int num_es_threads;
687 int num_ps_stack_entries;
688 int num_vs_stack_entries;
689 int num_gs_stack_entries;
690 int num_es_stack_entries;
691 enum radeon_family family;
692
693 family = radeon_get_family(rctx->rw);
694 ps_prio = 0;
695 vs_prio = 1;
696 gs_prio = 2;
697 es_prio = 3;
698 switch (family) {
699 case CHIP_R600:
700 num_ps_gprs = 192;
701 num_vs_gprs = 56;
702 num_temp_gprs = 4;
703 num_gs_gprs = 0;
704 num_es_gprs = 0;
705 num_ps_threads = 136;
706 num_vs_threads = 48;
707 num_gs_threads = 4;
708 num_es_threads = 4;
709 num_ps_stack_entries = 128;
710 num_vs_stack_entries = 128;
711 num_gs_stack_entries = 0;
712 num_es_stack_entries = 0;
713 break;
714 case CHIP_RV630:
715 case CHIP_RV635:
716 num_ps_gprs = 84;
717 num_vs_gprs = 36;
718 num_temp_gprs = 4;
719 num_gs_gprs = 0;
720 num_es_gprs = 0;
721 num_ps_threads = 144;
722 num_vs_threads = 40;
723 num_gs_threads = 4;
724 num_es_threads = 4;
725 num_ps_stack_entries = 40;
726 num_vs_stack_entries = 40;
727 num_gs_stack_entries = 32;
728 num_es_stack_entries = 16;
729 break;
730 case CHIP_RV610:
731 case CHIP_RV620:
732 case CHIP_RS780:
733 case CHIP_RS880:
734 default:
735 num_ps_gprs = 84;
736 num_vs_gprs = 36;
737 num_temp_gprs = 4;
738 num_gs_gprs = 0;
739 num_es_gprs = 0;
740 num_ps_threads = 136;
741 num_vs_threads = 48;
742 num_gs_threads = 4;
743 num_es_threads = 4;
744 num_ps_stack_entries = 40;
745 num_vs_stack_entries = 40;
746 num_gs_stack_entries = 32;
747 num_es_stack_entries = 16;
748 break;
749 case CHIP_RV670:
750 num_ps_gprs = 144;
751 num_vs_gprs = 40;
752 num_temp_gprs = 4;
753 num_gs_gprs = 0;
754 num_es_gprs = 0;
755 num_ps_threads = 136;
756 num_vs_threads = 48;
757 num_gs_threads = 4;
758 num_es_threads = 4;
759 num_ps_stack_entries = 40;
760 num_vs_stack_entries = 40;
761 num_gs_stack_entries = 32;
762 num_es_stack_entries = 16;
763 break;
764 case CHIP_RV770:
765 num_ps_gprs = 192;
766 num_vs_gprs = 56;
767 num_temp_gprs = 4;
768 num_gs_gprs = 0;
769 num_es_gprs = 0;
770 num_ps_threads = 188;
771 num_vs_threads = 60;
772 num_gs_threads = 0;
773 num_es_threads = 0;
774 num_ps_stack_entries = 256;
775 num_vs_stack_entries = 256;
776 num_gs_stack_entries = 0;
777 num_es_stack_entries = 0;
778 break;
779 case CHIP_RV730:
780 case CHIP_RV740:
781 num_ps_gprs = 84;
782 num_vs_gprs = 36;
783 num_temp_gprs = 4;
784 num_gs_gprs = 0;
785 num_es_gprs = 0;
786 num_ps_threads = 188;
787 num_vs_threads = 60;
788 num_gs_threads = 0;
789 num_es_threads = 0;
790 num_ps_stack_entries = 128;
791 num_vs_stack_entries = 128;
792 num_gs_stack_entries = 0;
793 num_es_stack_entries = 0;
794 break;
795 case CHIP_RV710:
796 num_ps_gprs = 192;
797 num_vs_gprs = 56;
798 num_temp_gprs = 4;
799 num_gs_gprs = 0;
800 num_es_gprs = 0;
801 num_ps_threads = 144;
802 num_vs_threads = 48;
803 num_gs_threads = 0;
804 num_es_threads = 0;
805 num_ps_stack_entries = 128;
806 num_vs_stack_entries = 128;
807 num_gs_stack_entries = 0;
808 num_es_stack_entries = 0;
809 break;
810 }
811 radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0);
812
813 rctx->config.states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
814 switch (family) {
815 case CHIP_RV610:
816 case CHIP_RV620:
817 case CHIP_RS780:
818 case CHIP_RS880:
819 case CHIP_RV710:
820 break;
821 default:
822 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
823 break;
824 }
825
826 if (!rctx->screen->use_mem_constant)
827 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
828
829 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
830 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
831 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
832 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
833 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
834
835 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
836 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
837 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
838 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
839
840 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
841 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
842 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
843
844 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
845 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
846 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
847 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
848 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
849
850 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
851 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
852 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
853
854 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
855 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
856 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
857
858 rctx->config.states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
859 rctx->config.states[R600_CONFIG__SX_MISC] = 0x00000000;
860
861 if (family >= CHIP_RV770) {
862 rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] =
863 S_008D8C_VS_PC_LIMIT_ENABLE(1);
864 rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
865 rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x00000000;
866 rctx->config.states[R600_CONFIG__DB_WATERMARKS] =
867 S_009838_DEPTH_FREE(4) |
868 S_009838_DEPTH_FLUSH(16) |
869 S_009838_DEPTH_PENDING_FREE(4) |
870 S_009838_DEPTH_CACHELINE_FREE(4);
871 rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000000;
872 rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00500000 |
873 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
874 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
875 } else {
876 rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000;
877 rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002 |
878 S_009508_DISABLE_CUBE_WRAP(1);
879 rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x82000000;
880 rctx->config.states[R600_CONFIG__DB_WATERMARKS] =
881 S_009838_DEPTH_FREE(4) |
882 S_009838_DEPTH_FLUSH(16) |
883 S_009838_DEPTH_PENDING_FREE(4) |
884 S_009838_DEPTH_CACHELINE_FREE(16);
885 rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] =
886 S_0286C8_PS_GROUPING(1);
887 rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] =
888 S_028A4C_WALK_ORDER_ENABLE(1) |
889 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
890 }
891 rctx->config.states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
892 rctx->config.states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
893 rctx->config.states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
894 rctx->config.states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
895 rctx->config.states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
896 rctx->config.states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
897 rctx->config.states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
898 rctx->config.states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
899 rctx->config.states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
900 rctx->config.states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
901 rctx->config.states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
902 rctx->config.states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
903 rctx->config.states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
904 rctx->config.states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
905 rctx->config.states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
906 rctx->config.states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
907 rctx->config.states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
908 rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
909 rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
910 rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
911 rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
912 rctx->config.states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
913 rctx->config.states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
914 rctx->config.states[R600_CONFIG__VGT_REUSE_OFF] = S_028AB4_REUSE_OFF(1);
915 rctx->config.states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
916 rctx->config.states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
917 radeon_state_pm4(&rctx->config);
918 }
919
920 static int r600_vs_resource(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset,
921 uint32_t stride, uint32_t format)
922 {
923 struct radeon_state *vs_resource = &rctx->vs_resource[id];
924 struct r600_screen *rscreen = rctx->screen;
925
926 radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS);
927 radeon_ws_bo_reference(rscreen->rw, &vs_resource->bo[0], rbuffer->bo);
928 vs_resource->nbo = 1;
929 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
930 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->size - offset - 1;
931 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(stride) |
932 S_038008_DATA_FORMAT(format);
933 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
934 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
935 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
936 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
937 vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
938 vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
939 return radeon_state_pm4(vs_resource);
940 }
941
942 static int r600_draw_vgt_init(struct r600_draw *draw,
943 int vgt_draw_initiator)
944 {
945 struct r600_context *rctx = r600_context(draw->ctx);
946 struct r600_screen *rscreen = rctx->screen;
947 struct r600_resource *rbuffer = (struct r600_resource *)draw->index_buffer;
948 radeon_state_init(&draw->draw, rscreen->rw, R600_STATE_DRAW, 0, 0);
949 draw->draw.states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
950 draw->draw.states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
951 draw->draw.states[R600_DRAW__VGT_DMA_BASE] = draw->index_buffer_offset;
952 if (rbuffer) {
953 radeon_ws_bo_reference(rscreen->rw, &draw->draw.bo[0], rbuffer->bo);
954 draw->draw.placement[0] = RADEON_GEM_DOMAIN_GTT;
955 draw->draw.placement[1] = RADEON_GEM_DOMAIN_GTT;
956 draw->draw.nbo = 1;
957 }
958 return radeon_state_pm4(&draw->draw);
959 }
960
961 static int r600_draw_vgt_prim(struct r600_draw *draw,
962 uint32_t prim, uint32_t vgt_dma_index_type)
963 {
964 struct r600_context *rctx = r600_context(draw->ctx);
965 struct r600_screen *rscreen = rctx->screen;
966 radeon_state_init(&draw->vgt, rscreen->rw, R600_STATE_VGT, 0, 0);
967 draw->vgt.states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
968 draw->vgt.states[R600_VGT__VGT_MAX_VTX_INDX] = draw->max_index;
969 draw->vgt.states[R600_VGT__VGT_MIN_VTX_INDX] = draw->min_index;
970 draw->vgt.states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
971 draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
972 draw->vgt.states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
973 draw->vgt.states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
974 draw->vgt.states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
975 draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
976 draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
977 draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
978 return radeon_state_pm4(&draw->vgt);
979 }
980
981 static int r600_ps_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
982 struct radeon_state *state)
983 {
984 struct r600_screen *rscreen = rctx->screen;
985 const struct pipe_rasterizer_state *rasterizer;
986 struct r600_shader *rshader = &rpshader->shader;
987 unsigned i, tmp, exports_ps, num_cout;
988 boolean have_pos = FALSE, have_face = FALSE;
989
990 rasterizer = &rctx->rasterizer->state.rasterizer;
991
992 radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
993 for (i = 0; i < rshader->ninput; i++) {
994 tmp = S_028644_SEMANTIC(i) | S_028644_SEL_CENTROID(1);
995 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
996 have_pos = TRUE;
997 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
998 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
999 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
1000 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
1001 }
1002
1003 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1004 have_face = TRUE;
1005
1006 if (rasterizer->sprite_coord_enable & (1 << i)) {
1007 tmp |= S_028644_PT_SPRITE_TEX(1);
1008 }
1009 state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
1010 }
1011
1012 exports_ps = 0;
1013 num_cout = 0;
1014 for (i = 0; i < rshader->noutput; i++) {
1015 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1016 exports_ps |= S_028854_EXPORT_Z(1);
1017 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1018 num_cout++;
1019 }
1020 }
1021 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
1022 if (exports_ps == 0) {
1023 /* Always at least export 1 color component per pixel. */
1024 exports_ps = S_028854_EXPORT_COLORS(1);
1025 }
1026 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] =
1027 S_0286CC_NUM_INTERP(rshader->ninput) |
1028 S_0286CC_PERSP_GRADIENT_ENA(1);
1029
1030 if (have_pos) {
1031 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] |=
1032 S_0286CC_POSITION_ENA(1) |
1033 S_0286CC_BARYC_SAMPLE_CNTL(1);
1034 state->states[R600_PS_SHADER__SPI_INPUT_Z] |=
1035 S_0286D8_PROVIDE_Z_TO_SPI(1);
1036 }
1037
1038 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] =
1039 S_0286D0_FRONT_FACE_ENA(have_face);
1040
1041 state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] =
1042 S_028868_NUM_GPRS(rshader->bc.ngpr) |
1043 S_028868_STACK_SIZE(rshader->bc.nstack);
1044 state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
1045 radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
1046 state->nbo = 1;
1047 state->placement[0] = RADEON_GEM_DOMAIN_GTT;
1048 return radeon_state_pm4(state);
1049 }
1050
1051 static int r600_vs_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
1052 struct radeon_state *state)
1053 {
1054 struct r600_screen *rscreen = rctx->screen;
1055 struct r600_shader *rshader = &rpshader->shader;
1056 unsigned i, tmp;
1057
1058 radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
1059 for (i = 0; i < 10; i++) {
1060 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
1061 }
1062 /* so far never got proper semantic id from tgsi */
1063 for (i = 0; i < 32; i++) {
1064 tmp = i << ((i & 3) * 8);
1065 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
1066 }
1067 state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] =
1068 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
1069 state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] =
1070 S_028868_NUM_GPRS(rshader->bc.ngpr) |
1071 S_028868_STACK_SIZE(rshader->bc.nstack);
1072 radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
1073 radeon_ws_bo_reference(rscreen->rw, &state->bo[1], rpshader->bo);
1074 state->nbo = 2;
1075 state->placement[0] = RADEON_GEM_DOMAIN_GTT;
1076 state->placement[2] = RADEON_GEM_DOMAIN_GTT;
1077 return radeon_state_pm4(state);
1078 }
1079
1080 static void r600_texture_state_scissor(struct r600_screen *rscreen,
1081 struct r600_resource_texture *rtexture,
1082 unsigned level)
1083 {
1084 struct radeon_state *rstate = &rtexture->scissor[level];
1085 enum radeon_family family;
1086
1087 family = radeon_get_family(rscreen->rw);
1088
1089 radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
1090 /* set states (most default value are 0 and struct already
1091 * initialized to 0, thus avoid resetting them)
1092 */
1093 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
1094 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = 0x80000000;
1095 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
1096 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = 0x80000000;
1097 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
1098 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = 0x80000000;
1099 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
1100 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = 0x80000000;
1101 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
1102
1103 if (family >= CHIP_RV770)
1104 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
1105
1106 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
1107 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = 0x80000000;
1108 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
1109 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = 0x80000000;
1110 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
1111 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = 0x80000000;
1112 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
1113 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = 0x80000000;
1114
1115 radeon_state_pm4(rstate);
1116 }
1117
1118 static void r600_texture_state_cb(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
1119 {
1120 struct radeon_state *rstate;
1121 struct r600_resource *rbuffer;
1122 unsigned pitch, slice;
1123 unsigned color_info;
1124 unsigned format, swap, ntype;
1125 const struct util_format_description *desc;
1126
1127 rstate = &rtexture->cb[cb][level];
1128 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
1129 rbuffer = &rtexture->resource;
1130
1131 /* set states (most default value are 0 and struct already
1132 * initialized to 0, thus avoid resetting them)
1133 */
1134 pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
1135 slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
1136 ntype = 0;
1137 desc = util_format_description(rbuffer->base.b.format);
1138 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1139 ntype = V_0280A0_NUMBER_SRGB;
1140 format = r600_translate_colorformat(rtexture->resource.base.b.format);
1141 swap = r600_translate_colorswap(rtexture->resource.base.b.format);
1142 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
1143 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rtexture->uncompressed);
1144 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rtexture->uncompressed);
1145 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[2], rtexture->uncompressed);
1146 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1147 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1148 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
1149 rstate->nbo = 3;
1150 color_info = 0;
1151 } else {
1152 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
1153 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
1154 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[2], rbuffer->bo);
1155 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1156 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1157 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
1158 rstate->nbo = 3;
1159 color_info = S_0280A0_SOURCE_FORMAT(1);
1160 }
1161 color_info |= S_0280A0_FORMAT(format) |
1162 S_0280A0_COMP_SWAP(swap) |
1163 S_0280A0_BLEND_CLAMP(1) |
1164 S_0280A0_NUMBER_TYPE(ntype);
1165 rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
1166 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
1167 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
1168 S_028060_SLICE_TILE_MAX(slice);
1169
1170 radeon_state_pm4(rstate);
1171 }
1172
1173 static void r600_texture_state_db(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
1174 {
1175 struct radeon_state *rstate = &rtexture->db[level];
1176 struct r600_resource *rbuffer;
1177 unsigned pitch, slice, format;
1178
1179 radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
1180 rbuffer = &rtexture->resource;
1181 rtexture->tilled = 1;
1182 rtexture->array_mode = 2;
1183 rtexture->tile_type = 1;
1184 rtexture->depth = 1;
1185
1186 /* set states (most default value are 0 and struct already
1187 * initialized to 0, thus avoid resetting them)
1188 */
1189 pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
1190 slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
1191 format = r600_translate_dbformat(rbuffer->base.b.format);
1192 rstate->states[R600_DB__DB_DEPTH_BASE] = rtexture->offset[level] >> 8;
1193 rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtexture->array_mode) |
1194 S_028010_FORMAT(format);
1195 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
1196 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
1197 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
1198 S_028000_SLICE_TILE_MAX(slice);
1199 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
1200 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1201 rstate->nbo = 1;
1202
1203 radeon_state_pm4(rstate);
1204 }
1205
1206 static void r600_texture_state_viewport(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
1207 {
1208 struct radeon_state *rstate = &rtexture->viewport[level];
1209 float width, height;
1210
1211 radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
1212
1213 width = rtexture->width[level] * 0.5;
1214 height = rtexture->height[level] * 0.5;
1215
1216 /* set states (most default value are 0 and struct already
1217 * initialized to 0, thus avoid resetting them)
1218 */
1219 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(width);
1220 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(width);
1221 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(height);
1222 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(height);
1223 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(0.5);
1224 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(0.5);
1225 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] =
1226 S_028818_VPORT_X_SCALE_ENA(1) |
1227 S_028818_VPORT_X_OFFSET_ENA(1) |
1228 S_028818_VPORT_Y_SCALE_ENA(1) |
1229 S_028818_VPORT_Y_OFFSET_ENA(1) |
1230 S_028818_VPORT_Z_SCALE_ENA(1) |
1231 S_028818_VPORT_Z_OFFSET_ENA(1) |
1232 S_028818_VTX_W0_FMT(1);
1233 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = fui(1);
1234
1235 radeon_state_pm4(rstate);
1236 }
1237
1238 struct r600_context_hw_state_vtbl r600_hw_state_vtbl = {
1239 .blend = r600_blend,
1240 .ucp = r600_ucp,
1241 .cb = r600_cb,
1242 .db = r600_db,
1243 .rasterizer = r600_rasterizer,
1244 .scissor = r600_scissor,
1245 .viewport = r600_viewport,
1246 .dsa = r600_dsa,
1247 .sampler_border = r600_sampler_border,
1248 .sampler = r600_sampler,
1249 .resource = r600_resource,
1250 .cb_cntl = r600_cb_cntl,
1251 .vs_resource = r600_vs_resource,
1252 .vgt_init = r600_draw_vgt_init,
1253 .vgt_prim = r600_draw_vgt_prim,
1254 .vs_shader = r600_vs_shader,
1255 .ps_shader = r600_ps_shader,
1256 .init_config = r600_init_config,
1257 .texture_state_viewport = r600_texture_state_viewport,
1258 .texture_state_db = r600_texture_state_db,
1259 .texture_state_cb = r600_texture_state_cb,
1260 .texture_state_scissor = r600_texture_state_scissor,
1261 };
1262
1263 void r600_set_constant_buffer_file(struct pipe_context *ctx,
1264 uint shader, uint index,
1265 struct pipe_resource *buffer)
1266 {
1267 struct r600_screen *rscreen = r600_screen(ctx->screen);
1268 struct r600_context *rctx = r600_context(ctx);
1269 unsigned nconstant = 0, i, type, shader_class;
1270 struct radeon_state *rstate, *rstates;
1271 struct pipe_transfer *transfer;
1272 u32 *ptr;
1273
1274 type = R600_STATE_CONSTANT;
1275
1276 switch (shader) {
1277 case PIPE_SHADER_VERTEX:
1278 shader_class = R600_SHADER_VS;
1279 rstates = rctx->vs_constant;
1280 break;
1281 case PIPE_SHADER_FRAGMENT:
1282 shader_class = R600_SHADER_PS;
1283 rstates = rctx->ps_constant;
1284 break;
1285 default:
1286 R600_ERR("unsupported %d\n", shader);
1287 return;
1288 }
1289 if (buffer && buffer->width0 > 0) {
1290 nconstant = buffer->width0 / 16;
1291 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
1292 if (ptr == NULL)
1293 return;
1294 for (i = 0; i < nconstant; i++) {
1295 rstate = &rstates[i];
1296 radeon_state_init(rstate, rscreen->rw, type, i, shader_class);
1297 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
1298 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
1299 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
1300 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
1301 if (radeon_state_pm4(rstate))
1302 return;
1303 radeon_draw_bind(&rctx->draw, rstate);
1304 }
1305 pipe_buffer_unmap(ctx, buffer, transfer);
1306 }
1307 }
1308
1309 void r600_set_constant_buffer_mem(struct pipe_context *ctx,
1310 uint shader, uint index,
1311 struct pipe_resource *buffer)
1312 {
1313 struct r600_screen *rscreen = r600_screen(ctx->screen);
1314 struct r600_context *rctx = r600_context(ctx);
1315 unsigned nconstant = 0, type, shader_class, size;
1316 struct radeon_state *rstate, *rstates;
1317 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1318
1319 type = R600_STATE_CBUF;
1320
1321 switch (shader) {
1322 case PIPE_SHADER_VERTEX:
1323 shader_class = R600_SHADER_VS;
1324 rstates = rctx->vs_constant;
1325 break;
1326 case PIPE_SHADER_FRAGMENT:
1327 shader_class = R600_SHADER_PS;
1328 rstates = rctx->ps_constant;
1329 break;
1330 default:
1331 R600_ERR("unsupported %d\n", shader);
1332 return;
1333 }
1334
1335 rstate = &rstates[0];
1336
1337 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1338
1339 nconstant = buffer->width0 / 16;
1340 size = ALIGN_DIVUP(nconstant, 16);
1341
1342 radeon_state_init(rstate, rscreen->rw, type, 0, shader_class);
1343 rstate->states[R600_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0] = size;
1344 rstate->states[R600_VS_CBUF__ALU_CONST_CACHE_VS_0] = 0;
1345
1346 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
1347 rstate->nbo = 1;
1348 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
1349 if (radeon_state_pm4(rstate))
1350 return;
1351 radeon_draw_bind(&rctx->draw, rstate);
1352 }
1353