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r600g: fix warning in r600 pipe driver
[mesa.git] / src / gallium / drivers / r600 / r600_hw_states.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * 2010 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse
26 * Dave Airlie
27 */
28
29 #include <util/u_inlines.h>
30 #include <util/u_format.h>
31 #include <util/u_memory.h>
32 #include <util/u_blitter.h>
33 #include "util/u_pack_color.h"
34 #include "r600_screen.h"
35 #include "r600_context.h"
36 #include "r600_resource.h"
37 #include "r600_state_inlines.h"
38 #include "r600d.h"
39
40 static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
41 {
42 struct r600_screen *rscreen = rctx->screen;
43 int i;
44
45 radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
46 rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
47 rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
48 rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
49 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
50 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
51 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
52 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
53 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
54 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
55 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
56 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
57 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
58 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
59
60 for (i = 0; i < 8; i++) {
61 unsigned eqRGB = state->rt[i].rgb_func;
62 unsigned srcRGB = state->rt[i].rgb_src_factor;
63 unsigned dstRGB = state->rt[i].rgb_dst_factor;
64
65 unsigned eqA = state->rt[i].alpha_func;
66 unsigned srcA = state->rt[i].alpha_src_factor;
67 unsigned dstA = state->rt[i].alpha_dst_factor;
68 uint32_t bc = 0;
69
70 if (!state->rt[i].blend_enable)
71 continue;
72
73 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
74 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
75 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
76
77 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
78 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
79 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
80 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
81 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
82 }
83
84 rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
85 if (i == 0)
86 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
87 }
88
89 radeon_state_pm4(rstate);
90 }
91
92 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate,
93 const struct pipe_clip_state *state)
94 {
95 struct r600_screen *rscreen = rctx->screen;
96
97 radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
98
99 for (int i = 0; i < state->nr; i++) {
100 rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
101 rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
102 rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
103 rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
104 }
105 radeon_state_pm4(rstate);
106 }
107
108 static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
109 const struct pipe_framebuffer_state *state, int cb)
110 {
111 struct r600_screen *rscreen = rctx->screen;
112 struct r600_resource_texture *rtex;
113 struct r600_resource *rbuffer;
114 unsigned level = state->cbufs[cb]->level;
115 unsigned pitch, slice;
116 unsigned color_info;
117 unsigned format, swap, ntype;
118 const struct util_format_description *desc;
119
120 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
121 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
122 rbuffer = &rtex->resource;
123 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
124 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
125 rstate->nbo = 1;
126 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
127 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
128
129 ntype = 0;
130 desc = util_format_description(rtex->resource.base.b.format);
131 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
132 ntype = V_0280A0_NUMBER_SRGB;
133
134 format = r600_translate_colorformat(rtex->resource.base.b.format);
135 swap = r600_translate_colorswap(rtex->resource.base.b.format);
136
137 color_info = S_0280A0_FORMAT(format) |
138 S_0280A0_COMP_SWAP(swap) |
139 S_0280A0_BLEND_CLAMP(1) |
140 S_0280A0_SOURCE_FORMAT(1) |
141 S_0280A0_NUMBER_TYPE(ntype);
142
143 rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
144 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
145 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
146 S_028060_SLICE_TILE_MAX(slice);
147 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
148 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
149 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
150 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
151 radeon_state_pm4(rstate);
152 }
153
154 static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
155 const struct pipe_framebuffer_state *state)
156 {
157 struct r600_screen *rscreen = rctx->screen;
158 struct r600_resource_texture *rtex;
159 struct r600_resource *rbuffer;
160 unsigned level;
161 unsigned pitch, slice, format;
162
163 radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
164 if (state->zsbuf == NULL)
165 return;
166
167 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
168 rtex->tilled = 1;
169 rtex->array_mode = 2;
170 rtex->tile_type = 1;
171 rtex->depth = 1;
172 rbuffer = &rtex->resource;
173
174 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
175 rstate->nbo = 1;
176 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
177 level = state->zsbuf->level;
178 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
179 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
180 format = r600_translate_dbformat(state->zsbuf->texture->format);
181 rstate->states[R600_DB__DB_DEPTH_BASE] = state->zsbuf->offset >> 8;
182 rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
183 S_028010_FORMAT(format);
184 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
185 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
186 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
187 S_028000_SLICE_TILE_MAX(slice);
188 radeon_state_pm4(rstate);
189 }
190
191 static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
192 {
193 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
194 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
195 const struct pipe_clip_state *clip = NULL;
196 struct r600_screen *rscreen = rctx->screen;
197 float offset_units = 0, offset_scale = 0;
198 char depth = 0;
199 unsigned offset_db_fmt_cntl = 0;
200 unsigned tmp;
201 unsigned prov_vtx = 1;
202
203 if (rctx->clip)
204 clip = &rctx->clip->state.clip;
205 if (fb->zsbuf) {
206 offset_units = state->offset_units;
207 offset_scale = state->offset_scale * 12.0f;
208 switch (fb->zsbuf->texture->format) {
209 case PIPE_FORMAT_Z24X8_UNORM:
210 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
211 depth = -24;
212 offset_units *= 2.0f;
213 break;
214 case PIPE_FORMAT_Z32_FLOAT:
215 depth = -23;
216 offset_units *= 1.0f;
217 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
218 break;
219 case PIPE_FORMAT_Z16_UNORM:
220 depth = -16;
221 offset_units *= 4.0f;
222 break;
223 default:
224 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
225 return;
226 }
227 }
228 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
229
230 if (state->flatshade_first)
231 prov_vtx = 0;
232
233 rctx->flat_shade = state->flatshade;
234 radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
235 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
236 if (state->sprite_coord_enable) {
237 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
238 S_0286D4_PNT_SPRITE_ENA(1) |
239 S_0286D4_PNT_SPRITE_OVRD_X(2) |
240 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
241 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
242 S_0286D4_PNT_SPRITE_OVRD_W(1);
243 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
244 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
245 S_0286D4_PNT_SPRITE_TOP_1(1);
246 }
247 }
248 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
249 if (clip) {
250 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
251 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
252 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
253 }
254 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
255 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
256 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
257 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
258 S_028814_FACE(!state->front_ccw) |
259 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
260 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
261 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
262 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] =
263 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
264 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
265 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
266 /* point size 12.4 fixed point */
267 tmp = (unsigned)(state->point_size * 8.0);
268 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
269 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
270 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
271 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
272 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
273 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
274 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
275 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
276 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
277 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
278 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
279 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
280 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
281 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
282 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
283 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
284 radeon_state_pm4(rstate);
285 }
286
287 static void r600_scissor(struct r600_context *rctx, struct radeon_state *rstate)
288 {
289 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
290 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
291 struct r600_screen *rscreen = rctx->screen;
292 unsigned minx, maxx, miny, maxy;
293 u32 tl, br;
294
295 if (state == NULL) {
296 minx = 0;
297 miny = 0;
298 maxx = fb->cbufs[0]->width;
299 maxy = fb->cbufs[0]->height;
300 } else {
301 minx = state->minx;
302 miny = state->miny;
303 maxx = state->maxx;
304 maxy = state->maxy;
305 }
306 tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
307 br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
308 radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
309 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
310 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
311 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
312 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
313 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
314 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
315 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
316 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
317 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
318 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
319 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
320 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
321 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
322 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
323 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
324 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
325 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
326 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
327 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
328 radeon_state_pm4(rstate);
329 }
330
331 static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
332 {
333 struct r600_screen *rscreen = rctx->screen;
334
335 radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
336 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
337 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
338 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
339 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
340 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
341 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
342 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
343 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
344 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
345 radeon_state_pm4(rstate);
346 }
347
348 static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
349 {
350 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
351 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
352 struct r600_screen *rscreen = rctx->screen;
353 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
354 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
355 struct r600_shader *rshader;
356 struct r600_query *rquery;
357 boolean query_running;
358 int i;
359
360 if (rctx->ps_shader == NULL) {
361 return;
362 }
363 radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
364
365 db_shader_control = 0x210;
366 rshader = &rctx->ps_shader->shader;
367 if (rshader->uses_kill)
368 db_shader_control |= (1 << 6);
369 for (i = 0; i < rshader->noutput; i++) {
370 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
371 db_shader_control |= 1;
372 }
373 stencil_ref_mask = 0;
374 stencil_ref_mask_bf = 0;
375 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
376 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
377 S_028800_ZFUNC(state->depth.func);
378 /* set stencil enable */
379
380 if (state->stencil[0].enabled) {
381 db_depth_control |= S_028800_STENCIL_ENABLE(1);
382 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
383 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
384 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
385 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
386
387 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
388 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
389 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
390 if (state->stencil[1].enabled) {
391 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
392 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
393 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
394 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
395 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
396 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
397 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
398 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
399 }
400 }
401
402 alpha_test_control = 0;
403 alpha_ref = 0;
404 if (state->alpha.enabled) {
405 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
406 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
407 alpha_ref = fui(state->alpha.ref_value);
408 }
409
410 db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) |
411 S_028D0C_DEPTH_COMPRESS_DISABLE(1);
412 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
413 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
414 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
415
416 query_running = false;
417
418 LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
419 if (rquery->state & R600_QUERY_STATE_STARTED) {
420 query_running = true;
421 }
422 }
423
424 if (query_running) {
425 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
426 if (rscreen->chip_class == R700)
427 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
428 }
429
430 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
431 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
432 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
433 rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
434 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
435 rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
436 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
437 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
438 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
439 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
440 rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
441 rstate->states[R600_DSA__DB_RENDER_CONTROL] = db_render_control;
442 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = db_render_override;
443
444 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
445 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
446 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
447 radeon_state_pm4(rstate);
448 }
449
450
451 static INLINE u32 S_FIXED(float value, u32 frac_bits)
452 {
453 return value * (1 << frac_bits);
454 }
455
456 static void r600_sampler_border(struct r600_context *rctx, struct radeon_state *rstate,
457 const struct pipe_sampler_state *state, unsigned id)
458 {
459 struct r600_screen *rscreen = rctx->screen;
460 union util_color uc;
461
462 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
463
464 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER_BORDER, id, R600_SHADER_PS);
465 if (uc.ui) {
466 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED] = fui(state->border_color[0]);
467 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN] = fui(state->border_color[1]);
468 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE] = fui(state->border_color[2]);
469 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA] = fui(state->border_color[3]);
470 }
471 radeon_state_pm4(rstate);
472 }
473
474 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate,
475 const struct pipe_sampler_state *state, unsigned id)
476 {
477 struct r600_screen *rscreen = rctx->screen;
478 union util_color uc;
479
480 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
481
482 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
483 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
484 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
485 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
486 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
487 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
488 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
489 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
490 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
491 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
492 /* FIXME LOD it depends on texture base level ... */
493 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
494 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
495 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
496 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
497 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
498 radeon_state_pm4(rstate);
499
500 }
501
502
503 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
504 const struct pipe_sampler_view *view, unsigned id)
505 {
506 struct r600_context *rctx = r600_context(ctx);
507 struct r600_screen *rscreen = rctx->screen;
508 const struct util_format_description *desc;
509 struct r600_resource_texture *tmp;
510 struct r600_resource *rbuffer;
511 unsigned format;
512 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
513 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
514 int r;
515
516 rstate->cpm4 = 0;
517 swizzle[0] = view->swizzle_r;
518 swizzle[1] = view->swizzle_g;
519 swizzle[2] = view->swizzle_b;
520 swizzle[3] = view->swizzle_a;
521 format = r600_translate_texformat(view->texture->format,
522 swizzle,
523 &word4, &yuv_format);
524 if (format == ~0) {
525 return;
526 }
527 desc = util_format_description(view->texture->format);
528 if (desc == NULL) {
529 R600_ERR("unknow format %d\n", view->texture->format);
530 return;
531 }
532 radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
533 tmp = (struct r600_resource_texture*)view->texture;
534 rbuffer = &tmp->resource;
535 if (tmp->depth) {
536 r = r600_texture_from_depth(ctx, tmp, view->first_level);
537 if (r) {
538 return;
539 }
540 rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
541 rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
542 } else {
543 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
544 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
545 }
546 rstate->nbo = 2;
547 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
548 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
549 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
550 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
551
552 pitch = (tmp->pitch[0] / tmp->bpt);
553 pitch = (pitch + 0x7) & ~0x7;
554
555 /* FIXME properly handle first level != 0 */
556 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
557 S_038000_DIM(r600_tex_dim(view->texture->target)) |
558 S_038000_TILE_MODE(array_mode) |
559 S_038000_TILE_TYPE(tile_type) |
560 S_038000_PITCH((pitch / 8) - 1) |
561 S_038000_TEX_WIDTH(view->texture->width0 - 1);
562 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
563 S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
564 S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
565 S_038004_DATA_FORMAT(format);
566 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
567 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
568 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
569 word4 |
570 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
571 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
572 S_038010_REQUEST_SIZE(1) |
573 S_038010_BASE_LEVEL(view->first_level);
574 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
575 S_038014_LAST_LEVEL(view->last_level) |
576 S_038014_BASE_ARRAY(0) |
577 S_038014_LAST_ARRAY(0);
578 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
579 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
580 radeon_state_pm4(rstate);
581 }
582
583 static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
584 {
585 struct r600_screen *rscreen = rctx->screen;
586 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
587 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
588 uint32_t color_control, target_mask, shader_mask;
589 int i;
590
591 target_mask = 0;
592 shader_mask = 0;
593 color_control = S_028808_PER_MRT_BLEND(1);
594
595 for (i = 0; i < nr_cbufs; i++) {
596 shader_mask |= 0xf << (i * 4);
597 }
598
599 if (pbs->logicop_enable) {
600 color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20);
601 } else {
602 color_control |= (0xcc << 16);
603 }
604
605 if (pbs->independent_blend_enable) {
606 for (i = 0; i < nr_cbufs; i++) {
607 if (pbs->rt[i].blend_enable) {
608 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
609 }
610 target_mask |= (pbs->rt[i].colormask << (4 * i));
611 }
612 } else {
613 for (i = 0; i < nr_cbufs; i++) {
614 if (pbs->rt[0].blend_enable) {
615 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
616 }
617 target_mask |= (pbs->rt[0].colormask << (4 * i));
618 }
619 }
620 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
621 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
622 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
623 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
624 rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
625 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
626 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
627 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
628 rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
629 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
630 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
631 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
632 radeon_state_pm4(rstate);
633 }
634
635 static void r600_init_config(struct r600_context *rctx)
636 {
637 int ps_prio;
638 int vs_prio;
639 int gs_prio;
640 int es_prio;
641 int num_ps_gprs;
642 int num_vs_gprs;
643 int num_gs_gprs;
644 int num_es_gprs;
645 int num_temp_gprs;
646 int num_ps_threads;
647 int num_vs_threads;
648 int num_gs_threads;
649 int num_es_threads;
650 int num_ps_stack_entries;
651 int num_vs_stack_entries;
652 int num_gs_stack_entries;
653 int num_es_stack_entries;
654 enum radeon_family family;
655
656 family = radeon_get_family(rctx->rw);
657 ps_prio = 0;
658 vs_prio = 1;
659 gs_prio = 2;
660 es_prio = 3;
661 switch (family) {
662 case CHIP_R600:
663 num_ps_gprs = 192;
664 num_vs_gprs = 56;
665 num_temp_gprs = 4;
666 num_gs_gprs = 0;
667 num_es_gprs = 0;
668 num_ps_threads = 136;
669 num_vs_threads = 48;
670 num_gs_threads = 4;
671 num_es_threads = 4;
672 num_ps_stack_entries = 128;
673 num_vs_stack_entries = 128;
674 num_gs_stack_entries = 0;
675 num_es_stack_entries = 0;
676 break;
677 case CHIP_RV630:
678 case CHIP_RV635:
679 num_ps_gprs = 84;
680 num_vs_gprs = 36;
681 num_temp_gprs = 4;
682 num_gs_gprs = 0;
683 num_es_gprs = 0;
684 num_ps_threads = 144;
685 num_vs_threads = 40;
686 num_gs_threads = 4;
687 num_es_threads = 4;
688 num_ps_stack_entries = 40;
689 num_vs_stack_entries = 40;
690 num_gs_stack_entries = 32;
691 num_es_stack_entries = 16;
692 break;
693 case CHIP_RV610:
694 case CHIP_RV620:
695 case CHIP_RS780:
696 case CHIP_RS880:
697 default:
698 num_ps_gprs = 84;
699 num_vs_gprs = 36;
700 num_temp_gprs = 4;
701 num_gs_gprs = 0;
702 num_es_gprs = 0;
703 num_ps_threads = 136;
704 num_vs_threads = 48;
705 num_gs_threads = 4;
706 num_es_threads = 4;
707 num_ps_stack_entries = 40;
708 num_vs_stack_entries = 40;
709 num_gs_stack_entries = 32;
710 num_es_stack_entries = 16;
711 break;
712 case CHIP_RV670:
713 num_ps_gprs = 144;
714 num_vs_gprs = 40;
715 num_temp_gprs = 4;
716 num_gs_gprs = 0;
717 num_es_gprs = 0;
718 num_ps_threads = 136;
719 num_vs_threads = 48;
720 num_gs_threads = 4;
721 num_es_threads = 4;
722 num_ps_stack_entries = 40;
723 num_vs_stack_entries = 40;
724 num_gs_stack_entries = 32;
725 num_es_stack_entries = 16;
726 break;
727 case CHIP_RV770:
728 num_ps_gprs = 192;
729 num_vs_gprs = 56;
730 num_temp_gprs = 4;
731 num_gs_gprs = 0;
732 num_es_gprs = 0;
733 num_ps_threads = 188;
734 num_vs_threads = 60;
735 num_gs_threads = 0;
736 num_es_threads = 0;
737 num_ps_stack_entries = 256;
738 num_vs_stack_entries = 256;
739 num_gs_stack_entries = 0;
740 num_es_stack_entries = 0;
741 break;
742 case CHIP_RV730:
743 case CHIP_RV740:
744 num_ps_gprs = 84;
745 num_vs_gprs = 36;
746 num_temp_gprs = 4;
747 num_gs_gprs = 0;
748 num_es_gprs = 0;
749 num_ps_threads = 188;
750 num_vs_threads = 60;
751 num_gs_threads = 0;
752 num_es_threads = 0;
753 num_ps_stack_entries = 128;
754 num_vs_stack_entries = 128;
755 num_gs_stack_entries = 0;
756 num_es_stack_entries = 0;
757 break;
758 case CHIP_RV710:
759 num_ps_gprs = 192;
760 num_vs_gprs = 56;
761 num_temp_gprs = 4;
762 num_gs_gprs = 0;
763 num_es_gprs = 0;
764 num_ps_threads = 144;
765 num_vs_threads = 48;
766 num_gs_threads = 0;
767 num_es_threads = 0;
768 num_ps_stack_entries = 128;
769 num_vs_stack_entries = 128;
770 num_gs_stack_entries = 0;
771 num_es_stack_entries = 0;
772 break;
773 }
774 radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0);
775
776 rctx->config.states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
777 switch (family) {
778 case CHIP_RV610:
779 case CHIP_RV620:
780 case CHIP_RS780:
781 case CHIP_RS880:
782 case CHIP_RV710:
783 break;
784 default:
785 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
786 break;
787 }
788
789 if (!rctx->screen->use_mem_constant)
790 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
791
792 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
793 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
794 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
795 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
796 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
797
798 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
799 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
800 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
801 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
802
803 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
804 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
805 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
806
807 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
808 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
809 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
810 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
811 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
812
813 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
814 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
815 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
816
817 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
818 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
819 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
820
821 rctx->config.states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
822 rctx->config.states[R600_CONFIG__SX_MISC] = 0x00000000;
823
824 if (family >= CHIP_RV770) {
825 rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
826 rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
827 rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x00000000;
828 rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
829 rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000000;
830 rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
831 } else {
832 rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000;
833 rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000003;
834 rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x82000000;
835 rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x01020204;
836 rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
837 rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00004010;
838 }
839 rctx->config.states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
840 rctx->config.states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
841 rctx->config.states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
842 rctx->config.states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
843 rctx->config.states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
844 rctx->config.states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
845 rctx->config.states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
846 rctx->config.states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
847 rctx->config.states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
848 rctx->config.states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
849 rctx->config.states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
850 rctx->config.states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
851 rctx->config.states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
852 rctx->config.states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
853 rctx->config.states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
854 rctx->config.states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
855 rctx->config.states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
856 rctx->config.states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
857 rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
858 rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
859 rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
860 rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
861 rctx->config.states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
862 rctx->config.states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
863 rctx->config.states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
864 rctx->config.states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
865 rctx->config.states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
866 radeon_state_pm4(&rctx->config);
867 }
868
869 static int r600_vs_resource(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset,
870 uint32_t stride, uint32_t format)
871 {
872 struct radeon_state *vs_resource = &rctx->vs_resource[id];
873 struct r600_screen *rscreen = rctx->screen;
874
875 radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS);
876 vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
877 vs_resource->nbo = 1;
878 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
879 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset - 1;
880 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(stride) |
881 S_038008_DATA_FORMAT(format);
882 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
883 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
884 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
885 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
886 vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
887 vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
888 return radeon_state_pm4(vs_resource);
889 }
890
891 static int r600_draw_vgt_init(struct r600_context *rctx, struct radeon_state *draw,
892 struct r600_resource *rbuffer,
893 uint32_t count, int vgt_draw_initiator)
894 {
895 struct r600_screen *rscreen = rctx->screen;
896
897 radeon_state_init(draw, rscreen->rw, R600_STATE_DRAW, 0, 0);
898 draw->states[R600_DRAW__VGT_NUM_INDICES] = count;
899 draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
900 if (rbuffer) {
901 draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
902 draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
903 draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
904 draw->nbo = 1;
905 }
906 return radeon_state_pm4(draw);
907 }
908
909 static int r600_draw_vgt_prim(struct r600_context *rctx, struct radeon_state *vgt,
910 uint32_t prim, uint32_t start, uint32_t vgt_dma_index_type)
911 {
912 struct r600_screen *rscreen = rctx->screen;
913 radeon_state_init(vgt, rscreen->rw, R600_STATE_VGT, 0, 0);
914 vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
915 vgt->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
916 vgt->states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
917 vgt->states[R600_VGT__VGT_INDX_OFFSET] = start;
918 vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
919 vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
920 vgt->states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
921 vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
922 vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
923 vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
924 vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
925 return radeon_state_pm4(vgt);
926 }
927
928 static int r600_ps_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
929 struct radeon_state *state)
930 {
931 struct r600_screen *rscreen = rctx->screen;
932 const struct pipe_rasterizer_state *rasterizer;
933 struct r600_shader *rshader = &rpshader->shader;
934 unsigned i, tmp, exports_ps, num_cout;
935 boolean have_pos = FALSE;
936
937 rasterizer = &rctx->rasterizer->state.rasterizer;
938
939 radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
940 for (i = 0; i < rshader->ninput; i++) {
941 tmp = S_028644_SEMANTIC(i);
942 tmp |= S_028644_SEL_CENTROID(1);
943 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
944 have_pos = TRUE;
945 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
946 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
947 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
948 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
949 }
950 if (rasterizer->sprite_coord_enable & (1 << i)) {
951 tmp |= S_028644_PT_SPRITE_TEX(1);
952 }
953 state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
954 }
955
956 exports_ps = 0;
957 num_cout = 0;
958 for (i = 0; i < rshader->noutput; i++) {
959 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
960 exports_ps |= 1;
961 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
962 exports_ps |= (1 << (num_cout+1));
963 num_cout++;
964 }
965 }
966 if (!exports_ps) {
967 /* always at least export 1 component per pixel */
968 exports_ps = 2;
969 }
970 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
971 S_0286CC_PERSP_GRADIENT_ENA(1);
972 if (have_pos) {
973 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] |= S_0286CC_POSITION_ENA(1) |
974 S_0286CC_BARYC_SAMPLE_CNTL(1);
975 state->states[R600_PS_SHADER__SPI_INPUT_Z] |= 1;
976 }
977 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
978 state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
979 S_028868_STACK_SIZE(rshader->bc.nstack);
980 state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
981 state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
982 state->nbo = 1;
983 state->placement[0] = RADEON_GEM_DOMAIN_GTT;
984 return radeon_state_pm4(state);
985 }
986
987 static int r600_vs_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
988 struct radeon_state *state)
989 {
990 struct r600_screen *rscreen = rctx->screen;
991 struct r600_shader *rshader = &rpshader->shader;
992 unsigned i, tmp;
993
994 radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
995 for (i = 0; i < 10; i++) {
996 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
997 }
998 /* so far never got proper semantic id from tgsi */
999 for (i = 0; i < 32; i++) {
1000 tmp = i << ((i & 3) * 8);
1001 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
1002 }
1003 state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
1004 state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
1005 S_028868_STACK_SIZE(rshader->bc.nstack);
1006 state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
1007 state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
1008 state->nbo = 2;
1009 state->placement[0] = RADEON_GEM_DOMAIN_GTT;
1010 state->placement[2] = RADEON_GEM_DOMAIN_GTT;
1011 return radeon_state_pm4(state);
1012 }
1013
1014 struct r600_context_hw_state_vtbl r600_hw_state_vtbl = {
1015 .blend = r600_blend,
1016 .ucp = r600_ucp,
1017 .cb = r600_cb,
1018 .db = r600_db,
1019 .rasterizer = r600_rasterizer,
1020 .scissor = r600_scissor,
1021 .viewport = r600_viewport,
1022 .dsa = r600_dsa,
1023 .sampler_border = r600_sampler_border,
1024 .sampler = r600_sampler,
1025 .resource = r600_resource,
1026 .cb_cntl = r600_cb_cntl,
1027 .vs_resource = r600_vs_resource,
1028 .vgt_init = r600_draw_vgt_init,
1029 .vgt_prim = r600_draw_vgt_prim,
1030 .vs_shader = r600_vs_shader,
1031 .ps_shader = r600_ps_shader,
1032 .init_config = r600_init_config,
1033 };
1034
1035 void r600_set_constant_buffer_file(struct pipe_context *ctx,
1036 uint shader, uint index,
1037 struct pipe_resource *buffer)
1038 {
1039 struct r600_screen *rscreen = r600_screen(ctx->screen);
1040 struct r600_context *rctx = r600_context(ctx);
1041 unsigned nconstant = 0, i, type, shader_class;
1042 struct radeon_state *rstate, *rstates;
1043 struct pipe_transfer *transfer;
1044 u32 *ptr;
1045
1046 type = R600_STATE_CONSTANT;
1047
1048 switch (shader) {
1049 case PIPE_SHADER_VERTEX:
1050 shader_class = R600_SHADER_VS;
1051 rstates = rctx->vs_constant;
1052 break;
1053 case PIPE_SHADER_FRAGMENT:
1054 shader_class = R600_SHADER_PS;
1055 rstates = rctx->ps_constant;
1056 break;
1057 default:
1058 R600_ERR("unsupported %d\n", shader);
1059 return;
1060 }
1061 if (buffer && buffer->width0 > 0) {
1062 nconstant = buffer->width0 / 16;
1063 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
1064 if (ptr == NULL)
1065 return;
1066 for (i = 0; i < nconstant; i++) {
1067 rstate = &rstates[i];
1068 radeon_state_init(rstate, rscreen->rw, type, i, shader_class);
1069 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
1070 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
1071 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
1072 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
1073 if (radeon_state_pm4(rstate))
1074 return;
1075 radeon_draw_bind(&rctx->draw, rstate);
1076 }
1077 pipe_buffer_unmap(ctx, buffer, transfer);
1078 }
1079 }
1080
1081 void r600_set_constant_buffer_mem(struct pipe_context *ctx,
1082 uint shader, uint index,
1083 struct pipe_resource *buffer)
1084 {
1085 struct r600_screen *rscreen = r600_screen(ctx->screen);
1086 struct r600_context *rctx = r600_context(ctx);
1087 unsigned nconstant = 0, type, shader_class, size;
1088 struct radeon_state *rstate, *rstates;
1089 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1090
1091 type = R600_STATE_CBUF;
1092
1093 switch (shader) {
1094 case PIPE_SHADER_VERTEX:
1095 shader_class = R600_SHADER_VS;
1096 rstates = rctx->vs_constant;
1097 break;
1098 case PIPE_SHADER_FRAGMENT:
1099 shader_class = R600_SHADER_PS;
1100 rstates = rctx->ps_constant;
1101 break;
1102 default:
1103 R600_ERR("unsupported %d\n", shader);
1104 return;
1105 }
1106
1107 rstate = &rstates[0];
1108
1109 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1110
1111 nconstant = buffer->width0 / 16;
1112 size = ALIGN_DIVUP(nconstant, 16);
1113
1114 radeon_state_init(rstate, rscreen->rw, type, 0, shader_class);
1115 rstate->states[R600_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0] = size;
1116 rstate->states[R600_VS_CBUF__ALU_CONST_CACHE_VS_0] = 0;
1117
1118 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1119 rstate->nbo = 1;
1120 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
1121 if (radeon_state_pm4(rstate))
1122 return;
1123 radeon_draw_bind(&rctx->draw, rstate);
1124 }
1125