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r600g: abstract the hw states out behind a vtbl.
[mesa.git] / src / gallium / drivers / r600 / r600_hw_states.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * 2010 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse
26 * Dave Airlie
27 */
28 #include <util/u_inlines.h>
29 #include <util/u_format.h>
30 #include <util/u_memory.h>
31 #include <util/u_blitter.h>
32 #include "util/u_pack_color.h"
33 #include "r600_screen.h"
34 #include "r600_context.h"
35 #include "r600_resource.h"
36 #include "r600_state_inlines.h"
37 #include "r600d.h"
38
39 static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
40 {
41 struct r600_screen *rscreen = rctx->screen;
42 int i;
43
44 radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
45 rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
46 rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
47 rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
48 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
49 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
50 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
51 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
52 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
53 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
54 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
55 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
56 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
57 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
58
59 for (i = 0; i < 8; i++) {
60 unsigned eqRGB = state->rt[i].rgb_func;
61 unsigned srcRGB = state->rt[i].rgb_src_factor;
62 unsigned dstRGB = state->rt[i].rgb_dst_factor;
63
64 unsigned eqA = state->rt[i].alpha_func;
65 unsigned srcA = state->rt[i].alpha_src_factor;
66 unsigned dstA = state->rt[i].alpha_dst_factor;
67 uint32_t bc = 0;
68
69 if (!state->rt[i].blend_enable)
70 continue;
71
72 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
73 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
74 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
75
76 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
77 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
78 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
79 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
80 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
81 }
82
83 rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
84 if (i == 0)
85 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
86 }
87
88 radeon_state_pm4(rstate);
89 }
90
91 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate,
92 const struct pipe_clip_state *state)
93 {
94 struct r600_screen *rscreen = rctx->screen;
95
96 radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
97
98 for (int i = 0; i < state->nr; i++) {
99 rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
100 rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
101 rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
102 rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
103 }
104 radeon_state_pm4(rstate);
105 }
106
107 static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
108 const struct pipe_framebuffer_state *state, int cb)
109 {
110 struct r600_screen *rscreen = rctx->screen;
111 struct r600_resource_texture *rtex;
112 struct r600_resource *rbuffer;
113 unsigned level = state->cbufs[cb]->level;
114 unsigned pitch, slice;
115 unsigned color_info;
116 unsigned format, swap, ntype;
117 const struct util_format_description *desc;
118
119 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
120 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
121 rbuffer = &rtex->resource;
122 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
123 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
124 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
125 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
126 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
127 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
128 rstate->nbo = 3;
129 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
130 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
131
132 ntype = 0;
133 desc = util_format_description(rtex->resource.base.b.format);
134 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
135 ntype = V_0280A0_NUMBER_SRGB;
136
137 format = r600_translate_colorformat(rtex->resource.base.b.format);
138 swap = r600_translate_colorswap(rtex->resource.base.b.format);
139
140 color_info = S_0280A0_FORMAT(format) |
141 S_0280A0_COMP_SWAP(swap) |
142 S_0280A0_BLEND_CLAMP(1) |
143 S_0280A0_SOURCE_FORMAT(1) |
144 S_0280A0_NUMBER_TYPE(ntype);
145
146 rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
147 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
148 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
149 S_028060_SLICE_TILE_MAX(slice);
150 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
151 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
152 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
153 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
154 radeon_state_pm4(rstate);
155 }
156
157 static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
158 const struct pipe_framebuffer_state *state)
159 {
160 struct r600_screen *rscreen = rctx->screen;
161 struct r600_resource_texture *rtex;
162 struct r600_resource *rbuffer;
163 unsigned level;
164 unsigned pitch, slice, format;
165
166 radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
167 if (state->zsbuf == NULL)
168 return;
169
170 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
171 rtex->tilled = 1;
172 rtex->array_mode = 2;
173 rtex->tile_type = 1;
174 rtex->depth = 1;
175 rbuffer = &rtex->resource;
176
177 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
178 rstate->nbo = 1;
179 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
180 level = state->zsbuf->level;
181 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
182 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
183 format = r600_translate_dbformat(state->zsbuf->texture->format);
184 rstate->states[R600_DB__DB_DEPTH_BASE] = state->zsbuf->offset >> 8;
185 rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
186 S_028010_FORMAT(format);
187 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
188 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
189 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
190 S_028000_SLICE_TILE_MAX(slice);
191 radeon_state_pm4(rstate);
192 }
193
194 static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
195 {
196 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
197 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
198 const struct pipe_clip_state *clip = NULL;
199 struct r600_screen *rscreen = rctx->screen;
200 float offset_units = 0, offset_scale = 0;
201 char depth = 0;
202 unsigned offset_db_fmt_cntl = 0;
203 unsigned tmp;
204 unsigned prov_vtx = 1;
205
206 if (rctx->clip)
207 clip = &rctx->clip->state.clip;
208 if (fb->zsbuf) {
209 offset_units = state->offset_units;
210 offset_scale = state->offset_scale * 12.0f;
211 switch (fb->zsbuf->texture->format) {
212 case PIPE_FORMAT_Z24X8_UNORM:
213 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
214 depth = -24;
215 offset_units *= 2.0f;
216 break;
217 case PIPE_FORMAT_Z32_FLOAT:
218 depth = -23;
219 offset_units *= 1.0f;
220 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
221 break;
222 case PIPE_FORMAT_Z16_UNORM:
223 depth = -16;
224 offset_units *= 4.0f;
225 break;
226 default:
227 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
228 return;
229 }
230 }
231 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
232
233 if (state->flatshade_first)
234 prov_vtx = 0;
235
236 rctx->flat_shade = state->flatshade;
237 radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
238 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
239 if (state->sprite_coord_enable) {
240 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
241 S_0286D4_PNT_SPRITE_ENA(1) |
242 S_0286D4_PNT_SPRITE_OVRD_X(2) |
243 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
244 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
245 S_0286D4_PNT_SPRITE_OVRD_W(1);
246 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
247 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
248 S_0286D4_PNT_SPRITE_TOP_1(1);
249 }
250 }
251 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
252 if (clip) {
253 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
254 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
255 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
256 }
257 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
258 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
259 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
260 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
261 S_028814_FACE(!state->front_ccw) |
262 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
263 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
264 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
265 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] =
266 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
267 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
268 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
269 /* point size 12.4 fixed point */
270 tmp = (unsigned)(state->point_size * 8.0);
271 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
272 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
273 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
274 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
275 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
276 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
277 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
278 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
279 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
280 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
281 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
282 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
283 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
284 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
285 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
286 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
287 radeon_state_pm4(rstate);
288 }
289
290 static void r600_scissor(struct r600_context *rctx, struct radeon_state *rstate)
291 {
292 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
293 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
294 struct r600_screen *rscreen = rctx->screen;
295 unsigned minx, maxx, miny, maxy;
296 u32 tl, br;
297
298 if (state == NULL) {
299 minx = 0;
300 miny = 0;
301 maxx = fb->cbufs[0]->width;
302 maxy = fb->cbufs[0]->height;
303 } else {
304 minx = state->minx;
305 miny = state->miny;
306 maxx = state->maxx;
307 maxy = state->maxy;
308 }
309 tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
310 br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
311 radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
312 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
313 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
314 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
315 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
316 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
317 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
318 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
319 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
320 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
321 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
322 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
323 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
324 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
325 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
326 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
327 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
328 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
329 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
330 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
331 radeon_state_pm4(rstate);
332 }
333
334 static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
335 {
336 struct r600_screen *rscreen = rctx->screen;
337
338 radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
339 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
340 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
341 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
342 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
343 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
344 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
345 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
346 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
347 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
348 radeon_state_pm4(rstate);
349 }
350
351 static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
352 {
353 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
354 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
355 struct r600_screen *rscreen = rctx->screen;
356 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
357 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
358 struct r600_shader *rshader;
359 struct r600_query *rquery;
360 boolean query_running;
361 int i;
362
363 if (rctx->ps_shader == NULL) {
364 return;
365 }
366 radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
367
368 db_shader_control = 0x210;
369 rshader = &rctx->ps_shader->shader;
370 if (rshader->uses_kill)
371 db_shader_control |= (1 << 6);
372 for (i = 0; i < rshader->noutput; i++) {
373 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
374 db_shader_control |= 1;
375 }
376 stencil_ref_mask = 0;
377 stencil_ref_mask_bf = 0;
378 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
379 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
380 S_028800_ZFUNC(state->depth.func);
381 /* set stencil enable */
382
383 if (state->stencil[0].enabled) {
384 db_depth_control |= S_028800_STENCIL_ENABLE(1);
385 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
386 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
387 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
388 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
389
390 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
391 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
392 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
393 if (state->stencil[1].enabled) {
394 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
395 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
396 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
397 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
398 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
399 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
400 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
401 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
402 }
403 }
404
405 alpha_test_control = 0;
406 alpha_ref = 0;
407 if (state->alpha.enabled) {
408 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
409 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
410 alpha_ref = fui(state->alpha.ref_value);
411 }
412
413 db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) |
414 S_028D0C_DEPTH_COMPRESS_DISABLE(1);
415 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
416 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
417 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
418
419 query_running = false;
420
421 LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
422 if (rquery->state & R600_QUERY_STATE_STARTED) {
423 query_running = true;
424 }
425 }
426
427 if (query_running) {
428 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
429 if (rscreen->chip_class == R700)
430 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
431 }
432
433 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
434 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
435 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
436 rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
437 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
438 rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
439 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
440 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
441 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
442 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
443 rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
444 rstate->states[R600_DSA__DB_RENDER_CONTROL] = db_render_control;
445 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = db_render_override;
446
447 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
448 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
449 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
450 radeon_state_pm4(rstate);
451 }
452
453
454 static INLINE u32 S_FIXED(float value, u32 frac_bits)
455 {
456 return value * (1 << frac_bits);
457 }
458
459 static void r600_sampler_border(struct r600_context *rctx, struct radeon_state *rstate,
460 const struct pipe_sampler_state *state, unsigned id)
461 {
462 struct r600_screen *rscreen = rctx->screen;
463 union util_color uc;
464
465 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
466
467 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER_BORDER, id, R600_SHADER_PS);
468 if (uc.ui) {
469 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED] = fui(state->border_color[0]);
470 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN] = fui(state->border_color[1]);
471 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE] = fui(state->border_color[2]);
472 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA] = fui(state->border_color[3]);
473 }
474 radeon_state_pm4(rstate);
475 }
476
477 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate,
478 const struct pipe_sampler_state *state, unsigned id)
479 {
480 struct r600_screen *rscreen = rctx->screen;
481 union util_color uc;
482
483 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
484
485 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
486 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
487 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
488 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
489 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
490 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
491 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
492 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
493 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
494 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
495 /* FIXME LOD it depends on texture base level ... */
496 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
497 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
498 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
499 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
500 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
501 radeon_state_pm4(rstate);
502
503 }
504
505
506 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
507 const struct pipe_sampler_view *view, unsigned id)
508 {
509 struct r600_context *rctx = r600_context(ctx);
510 struct r600_screen *rscreen = rctx->screen;
511 const struct util_format_description *desc;
512 struct r600_resource_texture *tmp;
513 struct r600_resource *rbuffer;
514 unsigned format;
515 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
516 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
517 int r;
518
519 rstate->cpm4 = 0;
520 swizzle[0] = view->swizzle_r;
521 swizzle[1] = view->swizzle_g;
522 swizzle[2] = view->swizzle_b;
523 swizzle[3] = view->swizzle_a;
524 format = r600_translate_texformat(view->texture->format,
525 swizzle,
526 &word4, &yuv_format);
527 if (format == ~0) {
528 return;
529 }
530 desc = util_format_description(view->texture->format);
531 if (desc == NULL) {
532 R600_ERR("unknow format %d\n", view->texture->format);
533 return;
534 }
535 radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
536 tmp = (struct r600_resource_texture*)view->texture;
537 rbuffer = &tmp->resource;
538 if (tmp->depth) {
539 r = r600_texture_from_depth(ctx, tmp, view->first_level);
540 if (r) {
541 return;
542 }
543 rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
544 rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
545 } else {
546 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
547 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
548 }
549 rstate->nbo = 2;
550 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
551 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
552 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
553 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
554
555 pitch = (tmp->pitch[0] / tmp->bpt);
556 pitch = (pitch + 0x7) & ~0x7;
557
558 /* FIXME properly handle first level != 0 */
559 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
560 S_038000_DIM(r600_tex_dim(view->texture->target)) |
561 S_038000_TILE_MODE(array_mode) |
562 S_038000_TILE_TYPE(tile_type) |
563 S_038000_PITCH((pitch / 8) - 1) |
564 S_038000_TEX_WIDTH(view->texture->width0 - 1);
565 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
566 S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
567 S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
568 S_038004_DATA_FORMAT(format);
569 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
570 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
571 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
572 word4 |
573 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
574 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
575 S_038010_REQUEST_SIZE(1) |
576 S_038010_BASE_LEVEL(view->first_level);
577 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
578 S_038014_LAST_LEVEL(view->last_level) |
579 S_038014_BASE_ARRAY(0) |
580 S_038014_LAST_ARRAY(0);
581 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
582 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
583 radeon_state_pm4(rstate);
584 }
585
586 static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
587 {
588 struct r600_screen *rscreen = rctx->screen;
589 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
590 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
591 uint32_t color_control, target_mask, shader_mask;
592 int i;
593
594 target_mask = 0;
595 shader_mask = 0;
596 color_control = S_028808_PER_MRT_BLEND(1);
597
598 for (i = 0; i < nr_cbufs; i++) {
599 shader_mask |= 0xf << (i * 4);
600 }
601
602 if (pbs->logicop_enable) {
603 color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20);
604 } else {
605 color_control |= (0xcc << 16);
606 }
607
608 if (pbs->independent_blend_enable) {
609 for (i = 0; i < nr_cbufs; i++) {
610 if (pbs->rt[i].blend_enable) {
611 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
612 }
613 target_mask |= (pbs->rt[i].colormask << (4 * i));
614 }
615 } else {
616 for (i = 0; i < nr_cbufs; i++) {
617 if (pbs->rt[0].blend_enable) {
618 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
619 }
620 target_mask |= (pbs->rt[0].colormask << (4 * i));
621 }
622 }
623 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
624 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
625 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
626 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
627 rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
628 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
629 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
630 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
631 rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
632 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
633 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
634 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
635 radeon_state_pm4(rstate);
636 }
637
638 static void r600_init_config(struct r600_context *rctx)
639 {
640 int ps_prio;
641 int vs_prio;
642 int gs_prio;
643 int es_prio;
644 int num_ps_gprs;
645 int num_vs_gprs;
646 int num_gs_gprs;
647 int num_es_gprs;
648 int num_temp_gprs;
649 int num_ps_threads;
650 int num_vs_threads;
651 int num_gs_threads;
652 int num_es_threads;
653 int num_ps_stack_entries;
654 int num_vs_stack_entries;
655 int num_gs_stack_entries;
656 int num_es_stack_entries;
657 enum radeon_family family;
658
659 family = radeon_get_family(rctx->rw);
660 ps_prio = 0;
661 vs_prio = 1;
662 gs_prio = 2;
663 es_prio = 3;
664 switch (family) {
665 case CHIP_R600:
666 num_ps_gprs = 192;
667 num_vs_gprs = 56;
668 num_temp_gprs = 4;
669 num_gs_gprs = 0;
670 num_es_gprs = 0;
671 num_ps_threads = 136;
672 num_vs_threads = 48;
673 num_gs_threads = 4;
674 num_es_threads = 4;
675 num_ps_stack_entries = 128;
676 num_vs_stack_entries = 128;
677 num_gs_stack_entries = 0;
678 num_es_stack_entries = 0;
679 break;
680 case CHIP_RV630:
681 case CHIP_RV635:
682 num_ps_gprs = 84;
683 num_vs_gprs = 36;
684 num_temp_gprs = 4;
685 num_gs_gprs = 0;
686 num_es_gprs = 0;
687 num_ps_threads = 144;
688 num_vs_threads = 40;
689 num_gs_threads = 4;
690 num_es_threads = 4;
691 num_ps_stack_entries = 40;
692 num_vs_stack_entries = 40;
693 num_gs_stack_entries = 32;
694 num_es_stack_entries = 16;
695 break;
696 case CHIP_RV610:
697 case CHIP_RV620:
698 case CHIP_RS780:
699 case CHIP_RS880:
700 default:
701 num_ps_gprs = 84;
702 num_vs_gprs = 36;
703 num_temp_gprs = 4;
704 num_gs_gprs = 0;
705 num_es_gprs = 0;
706 num_ps_threads = 136;
707 num_vs_threads = 48;
708 num_gs_threads = 4;
709 num_es_threads = 4;
710 num_ps_stack_entries = 40;
711 num_vs_stack_entries = 40;
712 num_gs_stack_entries = 32;
713 num_es_stack_entries = 16;
714 break;
715 case CHIP_RV670:
716 num_ps_gprs = 144;
717 num_vs_gprs = 40;
718 num_temp_gprs = 4;
719 num_gs_gprs = 0;
720 num_es_gprs = 0;
721 num_ps_threads = 136;
722 num_vs_threads = 48;
723 num_gs_threads = 4;
724 num_es_threads = 4;
725 num_ps_stack_entries = 40;
726 num_vs_stack_entries = 40;
727 num_gs_stack_entries = 32;
728 num_es_stack_entries = 16;
729 break;
730 case CHIP_RV770:
731 num_ps_gprs = 192;
732 num_vs_gprs = 56;
733 num_temp_gprs = 4;
734 num_gs_gprs = 0;
735 num_es_gprs = 0;
736 num_ps_threads = 188;
737 num_vs_threads = 60;
738 num_gs_threads = 0;
739 num_es_threads = 0;
740 num_ps_stack_entries = 256;
741 num_vs_stack_entries = 256;
742 num_gs_stack_entries = 0;
743 num_es_stack_entries = 0;
744 break;
745 case CHIP_RV730:
746 case CHIP_RV740:
747 num_ps_gprs = 84;
748 num_vs_gprs = 36;
749 num_temp_gprs = 4;
750 num_gs_gprs = 0;
751 num_es_gprs = 0;
752 num_ps_threads = 188;
753 num_vs_threads = 60;
754 num_gs_threads = 0;
755 num_es_threads = 0;
756 num_ps_stack_entries = 128;
757 num_vs_stack_entries = 128;
758 num_gs_stack_entries = 0;
759 num_es_stack_entries = 0;
760 break;
761 case CHIP_RV710:
762 num_ps_gprs = 192;
763 num_vs_gprs = 56;
764 num_temp_gprs = 4;
765 num_gs_gprs = 0;
766 num_es_gprs = 0;
767 num_ps_threads = 144;
768 num_vs_threads = 48;
769 num_gs_threads = 0;
770 num_es_threads = 0;
771 num_ps_stack_entries = 128;
772 num_vs_stack_entries = 128;
773 num_gs_stack_entries = 0;
774 num_es_stack_entries = 0;
775 break;
776 }
777 radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0);
778
779 rctx->config.states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
780 switch (family) {
781 case CHIP_RV610:
782 case CHIP_RV620:
783 case CHIP_RS780:
784 case CHIP_RS880:
785 case CHIP_RV710:
786 break;
787 default:
788 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
789 break;
790 }
791
792 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
793
794 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
795 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
796 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
797 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
798 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
799
800 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
801 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
802 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
803 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
804
805 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
806 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
807 rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
808
809 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
810 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
811 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
812 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
813 rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
814
815 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
816 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
817 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
818
819 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
820 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
821 rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
822
823 rctx->config.states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
824 rctx->config.states[R600_CONFIG__SX_MISC] = 0x00000000;
825
826 if (family >= CHIP_RV770) {
827 rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
828 rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
829 rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x00000000;
830 rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
831 rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000000;
832 rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
833 } else {
834 rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000;
835 rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000003;
836 rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x82000000;
837 rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x01020204;
838 rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
839 rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00004010;
840 }
841 rctx->config.states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
842 rctx->config.states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
843 rctx->config.states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
844 rctx->config.states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
845 rctx->config.states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
846 rctx->config.states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
847 rctx->config.states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
848 rctx->config.states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
849 rctx->config.states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
850 rctx->config.states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
851 rctx->config.states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
852 rctx->config.states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
853 rctx->config.states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
854 rctx->config.states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
855 rctx->config.states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
856 rctx->config.states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
857 rctx->config.states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
858 rctx->config.states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
859 rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
860 rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
861 rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
862 rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
863 rctx->config.states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
864 rctx->config.states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
865 rctx->config.states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
866 rctx->config.states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
867 rctx->config.states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
868 radeon_state_pm4(&rctx->config);
869 }
870
871 static int r600_vs_resource(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset,
872 uint32_t stride, uint32_t format)
873 {
874 struct radeon_state *vs_resource = &rctx->vs_resource[id];
875 struct r600_screen *rscreen = rctx->screen;
876
877 radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS);
878 vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
879 vs_resource->nbo = 1;
880 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
881 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset - 1;
882 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(stride) |
883 S_038008_DATA_FORMAT(format);
884 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
885 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
886 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
887 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
888 vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
889 vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
890 return radeon_state_pm4(vs_resource);
891 }
892
893 static int r600_draw_vgt_init(struct r600_context *rctx, struct radeon_state *draw,
894 struct r600_resource *rbuffer,
895 uint32_t count, int vgt_draw_initiator)
896 {
897 struct r600_screen *rscreen = rctx->screen;
898
899 radeon_state_init(draw, rscreen->rw, R600_STATE_DRAW, 0, 0);
900 draw->states[R600_DRAW__VGT_NUM_INDICES] = count;
901 draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
902 if (rbuffer) {
903 draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
904 draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
905 draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
906 draw->nbo = 1;
907 }
908 return radeon_state_pm4(draw);
909 }
910
911 static int r600_draw_vgt_prim(struct r600_context *rctx, struct radeon_state *vgt,
912 uint32_t prim, uint32_t start, uint32_t vgt_dma_index_type)
913 {
914 struct r600_screen *rscreen = rctx->screen;
915 radeon_state_init(vgt, rscreen->rw, R600_STATE_VGT, 0, 0);
916 vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
917 vgt->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
918 vgt->states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
919 vgt->states[R600_VGT__VGT_INDX_OFFSET] = start;
920 vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
921 vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
922 vgt->states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
923 vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
924 vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
925 vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
926 vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
927 return radeon_state_pm4(vgt);
928 }
929
930 static int r600_ps_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
931 struct radeon_state *state)
932 {
933 struct r600_screen *rscreen = rctx->screen;
934 const struct pipe_rasterizer_state *rasterizer;
935 struct r600_shader *rshader = &rpshader->shader;
936 unsigned i, tmp, exports_ps, num_cout;
937 boolean have_pos = FALSE;
938
939 rasterizer = &rctx->rasterizer->state.rasterizer;
940
941 radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
942 for (i = 0; i < rshader->ninput; i++) {
943 tmp = S_028644_SEMANTIC(i);
944 tmp |= S_028644_SEL_CENTROID(1);
945 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
946 have_pos = TRUE;
947 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
948 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
949 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
950 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
951 }
952 if (rasterizer->sprite_coord_enable & (1 << i)) {
953 tmp |= S_028644_PT_SPRITE_TEX(1);
954 }
955 state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
956 }
957
958 exports_ps = 0;
959 num_cout = 0;
960 for (i = 0; i < rshader->noutput; i++) {
961 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
962 exports_ps |= 1;
963 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
964 exports_ps |= (1 << (num_cout+1));
965 num_cout++;
966 }
967 }
968 if (!exports_ps) {
969 /* always at least export 1 component per pixel */
970 exports_ps = 2;
971 }
972 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
973 S_0286CC_PERSP_GRADIENT_ENA(1);
974 if (have_pos) {
975 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] |= S_0286CC_POSITION_ENA(1) |
976 S_0286CC_BARYC_SAMPLE_CNTL(1);
977 state->states[R600_PS_SHADER__SPI_INPUT_Z] |= 1;
978 }
979 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
980 state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
981 S_028868_STACK_SIZE(rshader->bc.nstack);
982 state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
983 state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
984 state->nbo = 1;
985 state->placement[0] = RADEON_GEM_DOMAIN_GTT;
986 return radeon_state_pm4(state);
987 }
988
989 static int r600_vs_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
990 struct radeon_state *state)
991 {
992 struct r600_screen *rscreen = rctx->screen;
993 struct r600_shader *rshader = &rpshader->shader;
994 unsigned i, tmp;
995
996 radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
997 for (i = 0; i < 10; i++) {
998 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
999 }
1000 /* so far never got proper semantic id from tgsi */
1001 for (i = 0; i < 32; i++) {
1002 tmp = i << ((i & 3) * 8);
1003 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
1004 }
1005 state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
1006 state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
1007 S_028868_STACK_SIZE(rshader->bc.nstack);
1008 state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
1009 state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
1010 state->nbo = 2;
1011 state->placement[0] = RADEON_GEM_DOMAIN_GTT;
1012 state->placement[2] = RADEON_GEM_DOMAIN_GTT;
1013 return radeon_state_pm4(state);
1014 }
1015
1016 struct r600_context_hw_state_vtbl r600_hw_state_vtbl = {
1017 .blend = r600_blend,
1018 .ucp = r600_ucp,
1019 .cb = r600_cb,
1020 .db = r600_db,
1021 .rasterizer = r600_rasterizer,
1022 .scissor = r600_scissor,
1023 .viewport = r600_viewport,
1024 .dsa = r600_dsa,
1025 .sampler_border = r600_sampler_border,
1026 .sampler = r600_sampler,
1027 .resource = r600_resource,
1028 .cb_cntl = r600_cb_cntl,
1029 .vs_resource = r600_vs_resource,
1030 .vgt_init = r600_draw_vgt_init,
1031 .vgt_prim = r600_draw_vgt_prim,
1032 .vs_shader = r600_vs_shader,
1033 .ps_shader = r600_ps_shader,
1034 .init_config = r600_init_config,
1035 };