2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include <util/u_inlines.h>
30 #include <util/u_format.h>
31 #include <util/u_memory.h>
32 #include <util/u_blitter.h>
33 #include "util/u_pack_color.h"
34 #include "r600_screen.h"
35 #include "r600_context.h"
36 #include "r600_resource.h"
37 #include "r600_state_inlines.h"
40 static void r600_blend(struct r600_context
*rctx
, struct radeon_state
*rstate
, const struct pipe_blend_state
*state
)
42 struct r600_screen
*rscreen
= rctx
->screen
;
45 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_BLEND
, 0, 0);
46 rstate
->states
[R600_BLEND__CB_BLEND_RED
] = fui(rctx
->blend_color
.color
[0]);
47 rstate
->states
[R600_BLEND__CB_BLEND_GREEN
] = fui(rctx
->blend_color
.color
[1]);
48 rstate
->states
[R600_BLEND__CB_BLEND_BLUE
] = fui(rctx
->blend_color
.color
[2]);
49 rstate
->states
[R600_BLEND__CB_BLEND_ALPHA
] = fui(rctx
->blend_color
.color
[3]);
50 rstate
->states
[R600_BLEND__CB_BLEND0_CONTROL
] = 0x00000000;
51 rstate
->states
[R600_BLEND__CB_BLEND1_CONTROL
] = 0x00000000;
52 rstate
->states
[R600_BLEND__CB_BLEND2_CONTROL
] = 0x00000000;
53 rstate
->states
[R600_BLEND__CB_BLEND3_CONTROL
] = 0x00000000;
54 rstate
->states
[R600_BLEND__CB_BLEND4_CONTROL
] = 0x00000000;
55 rstate
->states
[R600_BLEND__CB_BLEND5_CONTROL
] = 0x00000000;
56 rstate
->states
[R600_BLEND__CB_BLEND6_CONTROL
] = 0x00000000;
57 rstate
->states
[R600_BLEND__CB_BLEND7_CONTROL
] = 0x00000000;
58 rstate
->states
[R600_BLEND__CB_BLEND_CONTROL
] = 0x00000000;
60 for (i
= 0; i
< 8; i
++) {
61 unsigned eqRGB
= state
->rt
[i
].rgb_func
;
62 unsigned srcRGB
= state
->rt
[i
].rgb_src_factor
;
63 unsigned dstRGB
= state
->rt
[i
].rgb_dst_factor
;
65 unsigned eqA
= state
->rt
[i
].alpha_func
;
66 unsigned srcA
= state
->rt
[i
].alpha_src_factor
;
67 unsigned dstA
= state
->rt
[i
].alpha_dst_factor
;
70 if (!state
->rt
[i
].blend_enable
)
73 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
74 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
75 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
77 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
78 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
79 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
80 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
81 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
84 rstate
->states
[R600_BLEND__CB_BLEND0_CONTROL
+ i
] = bc
;
86 rstate
->states
[R600_BLEND__CB_BLEND_CONTROL
] = bc
;
89 radeon_state_pm4(rstate
);
92 static void r600_ucp(struct r600_context
*rctx
, struct radeon_state
*rstate
,
93 const struct pipe_clip_state
*state
)
95 struct r600_screen
*rscreen
= rctx
->screen
;
97 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_UCP
, 0, 0);
99 for (int i
= 0; i
< state
->nr
; i
++) {
100 rstate
->states
[i
* 4 + 0] = fui(state
->ucp
[i
][0]);
101 rstate
->states
[i
* 4 + 1] = fui(state
->ucp
[i
][1]);
102 rstate
->states
[i
* 4 + 2] = fui(state
->ucp
[i
][2]);
103 rstate
->states
[i
* 4 + 3] = fui(state
->ucp
[i
][3]);
105 radeon_state_pm4(rstate
);
108 static void r600_cb(struct r600_context
*rctx
, struct radeon_state
*rstate
,
109 const struct pipe_framebuffer_state
*state
, int cb
)
111 struct r600_screen
*rscreen
= rctx
->screen
;
112 struct r600_resource_texture
*rtex
;
113 struct r600_resource
*rbuffer
;
114 unsigned level
= state
->cbufs
[cb
]->level
;
115 unsigned pitch
, slice
;
117 unsigned format
, swap
, ntype
;
118 const struct util_format_description
*desc
;
120 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_CB0
+ cb
, 0, 0);
121 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
122 rbuffer
= &rtex
->resource
;
123 radeon_ws_bo_reference(rscreen
->rw
, &rstate
->bo
[0], rbuffer
->bo
);
124 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
126 pitch
= (rtex
->pitch
[level
] / rtex
->bpt
) / 8 - 1;
127 slice
= (rtex
->pitch
[level
] / rtex
->bpt
) * state
->cbufs
[cb
]->height
/ 64 - 1;
130 desc
= util_format_description(rtex
->resource
.base
.b
.format
);
131 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
132 ntype
= V_0280A0_NUMBER_SRGB
;
134 format
= r600_translate_colorformat(rtex
->resource
.base
.b
.format
);
135 swap
= r600_translate_colorswap(rtex
->resource
.base
.b
.format
);
138 color_info
= S_0280A0_FORMAT(format
) |
139 S_0280A0_COMP_SWAP(swap
) |
140 S_0280A0_BLEND_CLAMP(1) |
141 S_0280A0_NUMBER_TYPE(ntype
);
143 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
144 color_info
|= S_0280A0_SOURCE_FORMAT(1);
145 rstate
->states
[R600_CB0__CB_COLOR0_BASE
] = state
->cbufs
[cb
]->offset
>> 8;
146 rstate
->states
[R600_CB0__CB_COLOR0_INFO
] = color_info
;
147 rstate
->states
[R600_CB0__CB_COLOR0_SIZE
] = S_028060_PITCH_TILE_MAX(pitch
) |
148 S_028060_SLICE_TILE_MAX(slice
);
149 rstate
->states
[R600_CB0__CB_COLOR0_VIEW
] = 0x00000000;
150 rstate
->states
[R600_CB0__CB_COLOR0_FRAG
] = 0x00000000;
151 rstate
->states
[R600_CB0__CB_COLOR0_TILE
] = 0x00000000;
152 rstate
->states
[R600_CB0__CB_COLOR0_MASK
] = 0x00000000;
153 radeon_state_pm4(rstate
);
156 static void r600_db(struct r600_context
*rctx
, struct radeon_state
*rstate
,
157 const struct pipe_framebuffer_state
*state
)
159 struct r600_screen
*rscreen
= rctx
->screen
;
160 struct r600_resource_texture
*rtex
;
161 struct r600_resource
*rbuffer
;
163 unsigned pitch
, slice
, format
;
165 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_DB
, 0, 0);
166 if (state
->zsbuf
== NULL
)
169 rtex
= (struct r600_resource_texture
*)state
->zsbuf
->texture
;
171 rtex
->array_mode
= 2;
174 rbuffer
= &rtex
->resource
;
176 radeon_ws_bo_reference(rscreen
->rw
, &rstate
->bo
[0], rbuffer
->bo
);
178 rstate
->placement
[0] = RADEON_GEM_DOMAIN_VRAM
;
179 level
= state
->zsbuf
->level
;
180 pitch
= (rtex
->pitch
[level
] / rtex
->bpt
) / 8 - 1;
181 slice
= (rtex
->pitch
[level
] / rtex
->bpt
) * state
->zsbuf
->height
/ 64 - 1;
182 format
= r600_translate_dbformat(state
->zsbuf
->texture
->format
);
183 rstate
->states
[R600_DB__DB_DEPTH_BASE
] = state
->zsbuf
->offset
>> 8;
184 rstate
->states
[R600_DB__DB_DEPTH_INFO
] = S_028010_ARRAY_MODE(rtex
->array_mode
) |
185 S_028010_FORMAT(format
);
186 rstate
->states
[R600_DB__DB_DEPTH_VIEW
] = 0x00000000;
187 rstate
->states
[R600_DB__DB_PREFETCH_LIMIT
] = (state
->zsbuf
->height
/ 8) -1;
188 rstate
->states
[R600_DB__DB_DEPTH_SIZE
] = S_028000_PITCH_TILE_MAX(pitch
) |
189 S_028000_SLICE_TILE_MAX(slice
);
190 radeon_state_pm4(rstate
);
193 static void r600_rasterizer(struct r600_context
*rctx
, struct radeon_state
*rstate
)
195 const struct pipe_rasterizer_state
*state
= &rctx
->rasterizer
->state
.rasterizer
;
196 const struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
->state
.framebuffer
;
197 const struct pipe_clip_state
*clip
= NULL
;
198 struct r600_screen
*rscreen
= rctx
->screen
;
199 float offset_units
= 0, offset_scale
= 0;
201 unsigned offset_db_fmt_cntl
= 0;
203 unsigned prov_vtx
= 1;
206 clip
= &rctx
->clip
->state
.clip
;
208 offset_units
= state
->offset_units
;
209 offset_scale
= state
->offset_scale
* 12.0f
;
210 switch (fb
->zsbuf
->texture
->format
) {
211 case PIPE_FORMAT_Z24X8_UNORM
:
212 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
214 offset_units
*= 2.0f
;
216 case PIPE_FORMAT_Z32_FLOAT
:
218 offset_units
*= 1.0f
;
219 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
221 case PIPE_FORMAT_Z16_UNORM
:
223 offset_units
*= 4.0f
;
226 R600_ERR("unsupported %d\n", fb
->zsbuf
->texture
->format
);
230 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
232 if (state
->flatshade_first
)
235 rctx
->flat_shade
= state
->flatshade
;
236 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_RASTERIZER
, 0, 0);
237 rstate
->states
[R600_RASTERIZER__SPI_INTERP_CONTROL_0
] =
238 S_0286D4_FLAT_SHADE_ENA(1);
239 if (state
->sprite_coord_enable
) {
240 rstate
->states
[R600_RASTERIZER__SPI_INTERP_CONTROL_0
] |=
241 S_0286D4_PNT_SPRITE_ENA(1) |
242 S_0286D4_PNT_SPRITE_OVRD_X(2) |
243 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
244 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
245 S_0286D4_PNT_SPRITE_OVRD_W(1);
246 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
247 rstate
->states
[R600_RASTERIZER__SPI_INTERP_CONTROL_0
] |=
248 S_0286D4_PNT_SPRITE_TOP_1(1);
251 rstate
->states
[R600_RASTERIZER__PA_CL_CLIP_CNTL
] = 0;
253 /* Clip plane enable bits are stashed in the lower six bits of
254 * PA_CL_CLIP_CNTL, so just set all of the corresponding bits with a
255 * pinch of bit twiddling.
257 * PS_UCP_MODE 3 is "expand and clip as trifan," which is the same
258 * setting that we use on r300-r500. I believe that fglrx always uses
259 * this mode as well. */
260 rstate
->states
[R600_RASTERIZER__PA_CL_CLIP_CNTL
] =
261 ((1 << clip
->nr
) - 1) |
262 S_028810_PS_UCP_MODE(3) |
263 S_028810_ZCLIP_NEAR_DISABLE(clip
->depth_clamp
) |
264 S_028810_ZCLIP_FAR_DISABLE(clip
->depth_clamp
);
266 rstate
->states
[R600_RASTERIZER__PA_SU_SC_MODE_CNTL
] =
267 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
268 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
269 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
270 S_028814_FACE(!state
->front_ccw
) |
271 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
272 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
273 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
);
274 rstate
->states
[R600_RASTERIZER__PA_CL_VS_OUT_CNTL
] =
275 S_02881C_USE_VTX_POINT_SIZE(state
->point_size_per_vertex
) |
276 S_02881C_VS_OUT_MISC_VEC_ENA(state
->point_size_per_vertex
);
277 rstate
->states
[R600_RASTERIZER__PA_CL_NANINF_CNTL
] = 0x00000000;
278 /* Point size for PA_SU_POINT_SIZE and PA_SU_POINT_MINMAX is fixed-point,
281 * For some reason, maximum point size is set to 0x8000 (2048.0) instead
282 * of the maximum value 0xFFF0 (4095.0). */
283 point_size
= (unsigned)(state
->point_size
* 8.0);
284 rstate
->states
[R600_RASTERIZER__PA_SU_POINT_SIZE
] =
285 S_028A00_HEIGHT(point_size
) | S_028A00_WIDTH(point_size
);
286 rstate
->states
[R600_RASTERIZER__PA_SU_POINT_MINMAX
] =
287 S_028A04_MIN_SIZE(0) | S_028A04_MAX_SIZE(0x8000);
288 rstate
->states
[R600_RASTERIZER__PA_SU_LINE_CNTL
] = S_028A08_WIDTH(8);
289 rstate
->states
[R600_RASTERIZER__PA_SC_LINE_STIPPLE
] = 0x00000005;
290 rstate
->states
[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL
] = 0x00000000;
291 rstate
->states
[R600_RASTERIZER__PA_SC_LINE_CNTL
] = S_028C00_LAST_PIXEL(1);
292 rstate
->states
[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ
] = fui(1);
293 rstate
->states
[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ
] = fui(1);
294 rstate
->states
[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ
] = fui(1);
295 rstate
->states
[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ
] = fui(1);
296 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL
] = offset_db_fmt_cntl
;
297 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP
] = 0x00000000;
298 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE
] = fui(offset_scale
);
299 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET
] = fui(offset_units
);
300 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE
] = fui(offset_scale
);
301 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET
] = fui(offset_units
);
302 radeon_state_pm4(rstate
);
305 static void r600_scissor(struct r600_context
*rctx
, struct radeon_state
*rstate
)
307 const struct pipe_scissor_state
*state
= &rctx
->scissor
->state
.scissor
;
308 const struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
->state
.framebuffer
;
309 struct r600_screen
*rscreen
= rctx
->screen
;
310 enum radeon_family family
;
311 unsigned minx
, maxx
, miny
, maxy
;
314 family
= radeon_get_family(rctx
->rw
);
319 maxx
= fb
->cbufs
[0]->width
;
320 maxy
= fb
->cbufs
[0]->height
;
327 tl
= S_028240_TL_X(minx
) | S_028240_TL_Y(miny
) | S_028240_WINDOW_OFFSET_DISABLE(1);
328 br
= S_028244_BR_X(maxx
) | S_028244_BR_Y(maxy
);
329 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_SCISSOR
, 0, 0);
330 rstate
->states
[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL
] = tl
;
331 rstate
->states
[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR
] = br
;
332 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_OFFSET
] = 0x00000000;
333 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL
] = tl
;
334 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR
] = br
;
335 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_RULE
] =
336 S_02820C_CLIP_RULE(0xFFFF);
337 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_0_TL
] = tl
;
338 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_0_BR
] = br
;
339 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_1_TL
] = tl
;
340 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_1_BR
] = br
;
341 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_2_TL
] = tl
;
342 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_2_BR
] = br
;
343 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_3_TL
] = tl
;
344 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_3_BR
] = br
;
346 if (family
>= CHIP_RV770
)
347 rstate
->states
[R600_SCISSOR__PA_SC_EDGERULE
] = 0xAAAAAAAA;
349 rstate
->states
[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL
] = tl
;
350 rstate
->states
[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR
] = br
;
351 rstate
->states
[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL
] = tl
;
352 rstate
->states
[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR
] = br
;
353 radeon_state_pm4(rstate
);
356 static void r600_viewport(struct r600_context
*rctx
, struct radeon_state
*rstate
, const struct pipe_viewport_state
*state
)
358 struct r600_screen
*rscreen
= rctx
->screen
;
360 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_VIEWPORT
, 0, 0);
361 rstate
->states
[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0
] = fui(0);
362 rstate
->states
[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0
] = fui(1);
363 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0
] = fui(state
->scale
[0]);
364 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0
] = fui(state
->scale
[1]);
365 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0
] = fui(state
->scale
[2]);
366 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0
] = fui(state
->translate
[0]);
367 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0
] = fui(state
->translate
[1]);
368 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0
] = fui(state
->translate
[2]);
369 rstate
->states
[R600_VIEWPORT__PA_CL_VTE_CNTL
] =
370 S_028818_VPORT_X_SCALE_ENA(1) |
371 S_028818_VPORT_X_OFFSET_ENA(1) |
372 S_028818_VPORT_Y_SCALE_ENA(1) |
373 S_028818_VPORT_Y_OFFSET_ENA(1) |
374 S_028818_VPORT_Z_SCALE_ENA(1) |
375 S_028818_VPORT_Z_OFFSET_ENA(1) |
376 S_028818_VTX_W0_FMT(1);
377 radeon_state_pm4(rstate
);
380 static void r600_dsa(struct r600_context
*rctx
, struct radeon_state
*rstate
)
382 const struct pipe_depth_stencil_alpha_state
*state
= &rctx
->dsa
->state
.dsa
;
383 const struct pipe_stencil_ref
*stencil_ref
= &rctx
->stencil_ref
->state
.stencil_ref
;
384 struct r600_screen
*rscreen
= rctx
->screen
;
385 unsigned db_depth_control
, alpha_test_control
, alpha_ref
, db_shader_control
;
386 unsigned stencil_ref_mask
, stencil_ref_mask_bf
, db_render_override
, db_render_control
;
387 struct r600_shader
*rshader
;
388 struct r600_query
*rquery
= NULL
;
389 boolean query_running
;
391 bool flush_db
= FALSE
;
393 if (rctx
->ps_shader
== NULL
) {
396 if (rctx
->dsa
->flags
& R600_STATE_FLAG_DSA_FLUSH
)
399 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_DSA
, 0, 0);
401 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
404 db_shader_control
= S_02880C_DUAL_EXPORT_ENABLE(1);
406 rshader
= &rctx
->ps_shader
->shader
;
407 if (rshader
->uses_kill
)
408 db_shader_control
|= S_02880C_KILL_ENABLE(1);
409 for (i
= 0; i
< rshader
->noutput
; i
++) {
410 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
411 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(1);
413 stencil_ref_mask
= 0;
414 stencil_ref_mask_bf
= 0;
415 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
416 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
417 S_028800_ZFUNC(state
->depth
.func
);
419 /* set stencil enable */
420 if (state
->stencil
[0].enabled
) {
421 db_depth_control
|= S_028800_STENCIL_ENABLE(1) |
422 S_028800_STENCILFUNC(r600_translate_ds_func(state
->stencil
[0].func
)) |
423 S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
)) |
424 S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
)) |
425 S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
427 stencil_ref_mask
= S_028430_STENCILMASK(state
->stencil
[0].valuemask
) |
428 S_028430_STENCILWRITEMASK(state
->stencil
[0].writemask
) |
429 S_028430_STENCILREF(stencil_ref
->ref_value
[0]);
431 if (state
->stencil
[1].enabled
) {
432 db_depth_control
|= S_028800_BACKFACE_ENABLE(1) |
433 S_028800_STENCILFUNC_BF(r600_translate_ds_func(state
->stencil
[1].func
)) |
434 S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
)) |
435 S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
)) |
436 S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
437 stencil_ref_mask_bf
=
438 S_028434_STENCILMASK_BF(state
->stencil
[1].valuemask
) |
439 S_028434_STENCILWRITEMASK_BF(state
->stencil
[1].writemask
) |
440 S_028430_STENCILREF(stencil_ref
->ref_value
[1]);
444 alpha_test_control
= 0;
446 if (state
->alpha
.enabled
) {
447 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
) |
448 S_028410_ALPHA_TEST_ENABLE(1);
449 alpha_ref
= fui(state
->alpha
.ref_value
);
452 db_render_control
= 0;
455 db_render_control
= S_028D0C_DEPTH_COPY_ENABLE(1) |
456 S_028D0C_STENCIL_COPY_ENABLE(1) |
457 S_028D0C_COPY_CENTROID(1);
459 db_render_override
= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
) |
460 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
461 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
463 query_running
= FALSE
;
465 LIST_FOR_EACH_ENTRY(rquery
, &rctx
->query_list
, list
) {
466 if (rquery
->state
& R600_QUERY_STATE_STARTED
) {
467 query_running
= TRUE
;
472 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
473 if (radeon_get_family_class(rscreen
->rw
) == R700
)
474 db_render_control
|= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
477 rstate
->states
[R600_DSA__DB_STENCIL_CLEAR
] = 0x00000000;
478 rstate
->states
[R600_DSA__DB_DEPTH_CLEAR
] = fui(1);
479 rstate
->states
[R600_DSA__SX_ALPHA_TEST_CONTROL
] = alpha_test_control
;
480 rstate
->states
[R600_DSA__DB_STENCILREFMASK
] = stencil_ref_mask
;
481 rstate
->states
[R600_DSA__DB_STENCILREFMASK_BF
] = stencil_ref_mask_bf
;
482 rstate
->states
[R600_DSA__SX_ALPHA_REF
] = alpha_ref
;
483 rstate
->states
[R600_DSA__SPI_FOG_FUNC_SCALE
] = 0x00000000;
484 rstate
->states
[R600_DSA__SPI_FOG_FUNC_BIAS
] = 0x00000000;
485 rstate
->states
[R600_DSA__SPI_FOG_CNTL
] = 0x00000000;
486 rstate
->states
[R600_DSA__DB_DEPTH_CONTROL
] = db_depth_control
;
487 rstate
->states
[R600_DSA__DB_SHADER_CONTROL
] = db_shader_control
;
488 rstate
->states
[R600_DSA__DB_RENDER_CONTROL
] = db_render_control
;
489 rstate
->states
[R600_DSA__DB_RENDER_OVERRIDE
] = db_render_override
;
491 rstate
->states
[R600_DSA__DB_SRESULTS_COMPARE_STATE1
] = 0x00000000;
492 rstate
->states
[R600_DSA__DB_PRELOAD_CONTROL
] = 0x00000000;
493 rstate
->states
[R600_DSA__DB_ALPHA_TO_MASK
] = 0x0000AA00;
494 radeon_state_pm4(rstate
);
498 static INLINE u32
S_FIXED(float value
, u32 frac_bits
)
500 return value
* (1 << frac_bits
);
503 static void r600_sampler_border(struct r600_context
*rctx
, struct radeon_state
*rstate
,
504 const struct pipe_sampler_state
*state
, unsigned id
)
506 struct r600_screen
*rscreen
= rctx
->screen
;
509 util_pack_color(state
->border_color
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
511 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_SAMPLER_BORDER
, id
, R600_SHADER_PS
);
513 rstate
->states
[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED
] = fui(state
->border_color
[0]);
514 rstate
->states
[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN
] = fui(state
->border_color
[1]);
515 rstate
->states
[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE
] = fui(state
->border_color
[2]);
516 rstate
->states
[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA
] = fui(state
->border_color
[3]);
518 radeon_state_pm4(rstate
);
521 static void r600_sampler(struct r600_context
*rctx
, struct radeon_state
*rstate
,
522 const struct pipe_sampler_state
*state
, unsigned id
)
524 struct r600_screen
*rscreen
= rctx
->screen
;
527 util_pack_color(state
->border_color
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
529 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_SAMPLER
, id
, R600_SHADER_PS
);
530 rstate
->states
[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0
] =
531 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
532 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
533 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
534 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
)) |
535 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
)) |
536 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
537 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
538 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
539 /* FIXME LOD it depends on texture base level ... */
540 rstate
->states
[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0
] =
541 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
542 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
543 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6));
544 rstate
->states
[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0
] = S_03C008_TYPE(1);
545 radeon_state_pm4(rstate
);
550 static void r600_resource(struct pipe_context
*ctx
, struct radeon_state
*rstate
,
551 const struct pipe_sampler_view
*view
, unsigned id
)
553 struct r600_context
*rctx
= r600_context(ctx
);
554 struct r600_screen
*rscreen
= rctx
->screen
;
555 const struct util_format_description
*desc
;
556 struct r600_resource_texture
*texture
;
557 struct r600_resource
*rbuffer
;
559 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
560 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
563 swizzle
[0] = view
->swizzle_r
;
564 swizzle
[1] = view
->swizzle_g
;
565 swizzle
[2] = view
->swizzle_b
;
566 swizzle
[3] = view
->swizzle_a
;
567 format
= r600_translate_texformat(view
->texture
->format
,
569 &word4
, &yuv_format
);
573 desc
= util_format_description(view
->texture
->format
);
575 R600_ERR("unknow format %d\n", view
->texture
->format
);
578 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_RESOURCE
, id
, R600_SHADER_PS
);
579 texture
= (struct r600_resource_texture
*)view
->texture
;
580 rbuffer
= &texture
->resource
;
582 if (texture
->depth
) {
583 r600_texture_depth_flush(ctx
, view
->texture
);
584 rbuffer
= &texture
->flushed_depth_texture
->resource
;
587 radeon_ws_bo_reference(rscreen
->rw
, &rstate
->bo
[0], rbuffer
->bo
);
588 radeon_ws_bo_reference(rscreen
->rw
, &rstate
->bo
[1], rbuffer
->bo
);
591 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
592 rstate
->placement
[1] = RADEON_GEM_DOMAIN_GTT
;
593 rstate
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
594 rstate
->placement
[3] = RADEON_GEM_DOMAIN_GTT
;
596 pitch
= align(texture
->pitch
[0] / texture
->bpt
, 8);
598 /* FIXME properly handle first level != 0 */
599 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD0
] =
600 S_038000_DIM(r600_tex_dim(view
->texture
->target
)) |
601 S_038000_TILE_MODE(array_mode
) |
602 S_038000_TILE_TYPE(tile_type
) |
603 S_038000_PITCH((pitch
/ 8) - 1) |
604 S_038000_TEX_WIDTH(view
->texture
->width0
- 1);
605 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD1
] =
606 S_038004_TEX_HEIGHT(view
->texture
->height0
- 1) |
607 S_038004_TEX_DEPTH(view
->texture
->depth0
- 1) |
608 S_038004_DATA_FORMAT(format
);
609 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD2
] = texture
->offset
[0] >> 8;
610 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD3
] = texture
->offset
[1] >> 8;
611 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD4
] =
613 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM
) |
614 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO
) |
615 S_038010_REQUEST_SIZE(1) |
616 S_038010_BASE_LEVEL(view
->first_level
);
617 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD5
] =
618 S_038014_LAST_LEVEL(view
->last_level
) |
619 S_038014_BASE_ARRAY(0) |
620 S_038014_LAST_ARRAY(0);
621 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD6
] =
622 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
);
623 radeon_state_pm4(rstate
);
626 static void r600_cb_cntl(struct r600_context
*rctx
, struct radeon_state
*rstate
)
628 struct r600_screen
*rscreen
= rctx
->screen
;
629 const struct pipe_blend_state
*pbs
= &rctx
->blend
->state
.blend
;
630 int nr_cbufs
= rctx
->framebuffer
->state
.framebuffer
.nr_cbufs
;
631 uint32_t color_control
, target_mask
, shader_mask
, shader_control
;
637 color_control
= S_028808_PER_MRT_BLEND(1);
639 for (i
= 0; i
< nr_cbufs
; i
++) {
640 shader_mask
|= 0xf << (i
* 4);
641 shader_control
|= (1 << i
);
644 if (pbs
->logicop_enable
) {
645 color_control
|= (pbs
->logicop_func
<< 16) | (pbs
->logicop_func
<< 20);
647 color_control
|= (0xcc << 16);
650 if (pbs
->independent_blend_enable
) {
651 for (i
= 0; i
< nr_cbufs
; i
++) {
652 if (pbs
->rt
[i
].blend_enable
) {
653 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
655 target_mask
|= (pbs
->rt
[i
].colormask
<< (4 * i
));
658 for (i
= 0; i
< nr_cbufs
; i
++) {
659 if (pbs
->rt
[0].blend_enable
) {
660 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
662 target_mask
|= (pbs
->rt
[0].colormask
<< (4 * i
));
665 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_CB_CNTL
, 0, 0);
666 rstate
->states
[R600_CB_CNTL__CB_SHADER_MASK
] = shader_mask
;
667 rstate
->states
[R600_CB_CNTL__CB_TARGET_MASK
] = target_mask
;
668 rstate
->states
[R600_CB_CNTL__CB_COLOR_CONTROL
] = color_control
;
669 if (radeon_get_family_class(rscreen
->rw
) == R700
)
670 rstate
->states
[R600_CB_CNTL__CB_SHADER_CONTROL
] = shader_control
;
671 rstate
->states
[R600_CB_CNTL__PA_SC_AA_CONFIG
] = 0x00000000;
672 rstate
->states
[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX
] = 0x00000000;
673 rstate
->states
[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
] = 0x00000000;
674 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_CONTROL
] = 0x01000000;
675 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_SRC
] = 0x00000000;
676 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_DST
] = 0x000000FF;
677 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_MSK
] = 0xFFFFFFFF;
678 rstate
->states
[R600_CB_CNTL__PA_SC_AA_MASK
] = 0xFFFFFFFF;
679 radeon_state_pm4(rstate
);
682 static void r600_init_config(struct r600_context
*rctx
)
697 int num_ps_stack_entries
;
698 int num_vs_stack_entries
;
699 int num_gs_stack_entries
;
700 int num_es_stack_entries
;
701 enum radeon_family family
;
703 family
= radeon_get_family(rctx
->rw
);
715 num_ps_threads
= 136;
719 num_ps_stack_entries
= 128;
720 num_vs_stack_entries
= 128;
721 num_gs_stack_entries
= 0;
722 num_es_stack_entries
= 0;
731 num_ps_threads
= 144;
735 num_ps_stack_entries
= 40;
736 num_vs_stack_entries
= 40;
737 num_gs_stack_entries
= 32;
738 num_es_stack_entries
= 16;
750 num_ps_threads
= 136;
754 num_ps_stack_entries
= 40;
755 num_vs_stack_entries
= 40;
756 num_gs_stack_entries
= 32;
757 num_es_stack_entries
= 16;
765 num_ps_threads
= 136;
769 num_ps_stack_entries
= 40;
770 num_vs_stack_entries
= 40;
771 num_gs_stack_entries
= 32;
772 num_es_stack_entries
= 16;
780 num_ps_threads
= 188;
784 num_ps_stack_entries
= 256;
785 num_vs_stack_entries
= 256;
786 num_gs_stack_entries
= 0;
787 num_es_stack_entries
= 0;
796 num_ps_threads
= 188;
800 num_ps_stack_entries
= 128;
801 num_vs_stack_entries
= 128;
802 num_gs_stack_entries
= 0;
803 num_es_stack_entries
= 0;
811 num_ps_threads
= 144;
815 num_ps_stack_entries
= 128;
816 num_vs_stack_entries
= 128;
817 num_gs_stack_entries
= 0;
818 num_es_stack_entries
= 0;
821 radeon_state_init(&rctx
->config
, rctx
->rw
, R600_STATE_CONFIG
, 0, 0);
823 rctx
->config
.states
[R600_CONFIG__SQ_CONFIG
] = 0x00000000;
832 rctx
->config
.states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_VC_ENABLE(1);
836 if (!rctx
->screen
->use_mem_constant
)
837 rctx
->config
.states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_DX9_CONSTS(1);
839 rctx
->config
.states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
840 rctx
->config
.states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_PS_PRIO(ps_prio
);
841 rctx
->config
.states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_VS_PRIO(vs_prio
);
842 rctx
->config
.states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_GS_PRIO(gs_prio
);
843 rctx
->config
.states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_ES_PRIO(es_prio
);
845 rctx
->config
.states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] = 0;
846 rctx
->config
.states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] |= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
847 rctx
->config
.states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] |= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
848 rctx
->config
.states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
850 rctx
->config
.states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2
] = 0;
851 rctx
->config
.states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2
] |= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
852 rctx
->config
.states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2
] |= S_008C08_NUM_GS_GPRS(num_es_gprs
);
854 rctx
->config
.states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] = 0;
855 rctx
->config
.states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] |= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
856 rctx
->config
.states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] |= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
857 rctx
->config
.states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] |= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
858 rctx
->config
.states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] |= S_008C0C_NUM_ES_THREADS(num_es_threads
);
860 rctx
->config
.states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1
] = 0;
861 rctx
->config
.states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1
] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
862 rctx
->config
.states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1
] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
864 rctx
->config
.states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2
] = 0;
865 rctx
->config
.states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2
] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
866 rctx
->config
.states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2
] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
868 rctx
->config
.states
[R600_CONFIG__VC_ENHANCE
] = 0x00000000;
869 rctx
->config
.states
[R600_CONFIG__SX_MISC
] = 0x00000000;
871 if (family
>= CHIP_RV770
) {
872 rctx
->config
.states
[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
] =
873 S_008D8C_VS_PC_LIMIT_ENABLE(1);
874 rctx
->config
.states
[R600_CONFIG__TA_CNTL_AUX
] = 0x07000002;
875 rctx
->config
.states
[R600_CONFIG__DB_DEBUG
] = 0x00000000;
876 rctx
->config
.states
[R600_CONFIG__DB_WATERMARKS
] =
877 S_009838_DEPTH_FREE(4) |
878 S_009838_DEPTH_FLUSH(16) |
879 S_009838_DEPTH_PENDING_FREE(4) |
880 S_009838_DEPTH_CACHELINE_FREE(4);
881 rctx
->config
.states
[R600_CONFIG__SPI_THREAD_GROUPING
] = 0x00000000;
882 rctx
->config
.states
[R600_CONFIG__PA_SC_MODE_CNTL
] = 0x00500000 |
883 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
884 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
886 rctx
->config
.states
[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
] = 0x00000000;
887 rctx
->config
.states
[R600_CONFIG__TA_CNTL_AUX
] = 0x07000002 |
888 S_009508_DISABLE_CUBE_WRAP(1);
889 rctx
->config
.states
[R600_CONFIG__DB_DEBUG
] = 0x82000000;
890 rctx
->config
.states
[R600_CONFIG__DB_WATERMARKS
] =
891 S_009838_DEPTH_FREE(4) |
892 S_009838_DEPTH_FLUSH(16) |
893 S_009838_DEPTH_PENDING_FREE(4) |
894 S_009838_DEPTH_CACHELINE_FREE(16);
895 rctx
->config
.states
[R600_CONFIG__SPI_THREAD_GROUPING
] =
896 S_0286C8_PS_GROUPING(1);
897 rctx
->config
.states
[R600_CONFIG__PA_SC_MODE_CNTL
] =
898 S_028A4C_WALK_ORDER_ENABLE(1) |
899 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
901 rctx
->config
.states
[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE
] = 0x00000000;
902 rctx
->config
.states
[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE
] = 0x00000000;
903 rctx
->config
.states
[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE
] = 0x00000000;
904 rctx
->config
.states
[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE
] = 0x00000000;
905 rctx
->config
.states
[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE
] = 0x00000000;
906 rctx
->config
.states
[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE
] = 0x00000000;
907 rctx
->config
.states
[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE
] = 0x00000000;
908 rctx
->config
.states
[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE
] = 0x00000000;
909 rctx
->config
.states
[R600_CONFIG__SQ_GS_VERT_ITEMSIZE
] = 0x00000000;
910 rctx
->config
.states
[R600_CONFIG__VGT_OUTPUT_PATH_CNTL
] = 0x00000000;
911 rctx
->config
.states
[R600_CONFIG__VGT_HOS_CNTL
] = 0x00000000;
912 rctx
->config
.states
[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL
] = 0x00000000;
913 rctx
->config
.states
[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL
] = 0x00000000;
914 rctx
->config
.states
[R600_CONFIG__VGT_HOS_REUSE_DEPTH
] = 0x00000000;
915 rctx
->config
.states
[R600_CONFIG__VGT_GROUP_PRIM_TYPE
] = 0x00000000;
916 rctx
->config
.states
[R600_CONFIG__VGT_GROUP_FIRST_DECR
] = 0x00000000;
917 rctx
->config
.states
[R600_CONFIG__VGT_GROUP_DECR
] = 0x00000000;
918 rctx
->config
.states
[R600_CONFIG__VGT_GROUP_VECT_0_CNTL
] = 0x00000000;
919 rctx
->config
.states
[R600_CONFIG__VGT_GROUP_VECT_1_CNTL
] = 0x00000000;
920 rctx
->config
.states
[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL
] = 0x00000000;
921 rctx
->config
.states
[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL
] = 0x00000000;
922 rctx
->config
.states
[R600_CONFIG__VGT_GS_MODE
] = 0x00000000;
923 rctx
->config
.states
[R600_CONFIG__VGT_STRMOUT_EN
] = 0x00000000;
924 rctx
->config
.states
[R600_CONFIG__VGT_REUSE_OFF
] = S_028AB4_REUSE_OFF(1);
925 rctx
->config
.states
[R600_CONFIG__VGT_VTX_CNT_EN
] = 0x00000000;
926 rctx
->config
.states
[R600_CONFIG__VGT_STRMOUT_BUFFER_EN
] = 0x00000000;
927 radeon_state_pm4(&rctx
->config
);
930 static int r600_vs_resource(struct r600_context
*rctx
, int id
, struct r600_resource
*rbuffer
, uint32_t offset
,
931 uint32_t stride
, uint32_t src_format
)
933 struct radeon_state
*vs_resource
= &rctx
->vs_resource
[id
];
934 struct r600_screen
*rscreen
= rctx
->screen
;
935 unsigned format
, num_format
= 0, format_comp
= 0;
937 format
= r600_translate_colorformat(src_format
);
939 r600_translate_vertex_num_format(src_format
, &num_format
, &format_comp
);
941 format
= S_038008_DATA_FORMAT(format
) | S_038008_NUM_FORMAT_ALL(num_format
) | S_038008_FORMAT_COMP_ALL(format_comp
);
943 radeon_state_init(vs_resource
, rscreen
->rw
, R600_STATE_RESOURCE
, id
, R600_SHADER_VS
);
944 radeon_ws_bo_reference(rscreen
->rw
, &vs_resource
->bo
[0], rbuffer
->bo
);
945 vs_resource
->nbo
= 1;
946 vs_resource
->states
[R600_PS_RESOURCE__RESOURCE0_WORD0
] = offset
;
947 vs_resource
->states
[R600_PS_RESOURCE__RESOURCE0_WORD1
] = rbuffer
->size
- offset
- 1;
948 vs_resource
->states
[R600_PS_RESOURCE__RESOURCE0_WORD2
] = S_038008_STRIDE(stride
) | format
;
949 vs_resource
->states
[R600_PS_RESOURCE__RESOURCE0_WORD3
] = 0x00000000;
950 vs_resource
->states
[R600_PS_RESOURCE__RESOURCE0_WORD4
] = 0x00000000;
951 vs_resource
->states
[R600_PS_RESOURCE__RESOURCE0_WORD5
] = 0x00000000;
952 vs_resource
->states
[R600_PS_RESOURCE__RESOURCE0_WORD6
] = 0xC0000000;
953 vs_resource
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
954 vs_resource
->placement
[1] = RADEON_GEM_DOMAIN_GTT
;
955 return radeon_state_pm4(vs_resource
);
958 static int r600_draw_vgt_init(struct r600_draw
*draw
,
959 int vgt_draw_initiator
)
961 struct r600_context
*rctx
= r600_context(draw
->ctx
);
962 struct r600_screen
*rscreen
= rctx
->screen
;
963 struct r600_resource
*rbuffer
= (struct r600_resource
*)draw
->index_buffer
;
964 radeon_state_init(&draw
->draw
, rscreen
->rw
, R600_STATE_DRAW
, 0, 0);
965 draw
->draw
.states
[R600_DRAW__VGT_NUM_INDICES
] = draw
->count
;
966 draw
->draw
.states
[R600_DRAW__VGT_DRAW_INITIATOR
] = vgt_draw_initiator
;
967 draw
->draw
.states
[R600_DRAW__VGT_DMA_BASE
] = draw
->index_buffer_offset
;
969 radeon_ws_bo_reference(rscreen
->rw
, &draw
->draw
.bo
[0], rbuffer
->bo
);
970 draw
->draw
.placement
[0] = RADEON_GEM_DOMAIN_GTT
;
971 draw
->draw
.placement
[1] = RADEON_GEM_DOMAIN_GTT
;
974 return radeon_state_pm4(&draw
->draw
);
977 static int r600_draw_vgt_prim(struct r600_draw
*draw
,
978 uint32_t prim
, uint32_t vgt_dma_index_type
)
980 struct r600_context
*rctx
= r600_context(draw
->ctx
);
981 struct r600_screen
*rscreen
= rctx
->screen
;
982 radeon_state_init(&draw
->vgt
, rscreen
->rw
, R600_STATE_VGT
, 0, 0);
983 draw
->vgt
.states
[R600_VGT__VGT_PRIMITIVE_TYPE
] = prim
;
984 draw
->vgt
.states
[R600_VGT__VGT_MAX_VTX_INDX
] = draw
->max_index
;
985 draw
->vgt
.states
[R600_VGT__VGT_MIN_VTX_INDX
] = draw
->min_index
;
986 draw
->vgt
.states
[R600_VGT__VGT_INDX_OFFSET
] = draw
->start
;
987 draw
->vgt
.states
[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX
] = 0x00000000;
988 draw
->vgt
.states
[R600_VGT__VGT_DMA_INDEX_TYPE
] = vgt_dma_index_type
;
989 draw
->vgt
.states
[R600_VGT__VGT_PRIMITIVEID_EN
] = 0x00000000;
990 draw
->vgt
.states
[R600_VGT__VGT_DMA_NUM_INSTANCES
] = 0x00000001;
991 draw
->vgt
.states
[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN
] = 0x00000000;
992 draw
->vgt
.states
[R600_VGT__VGT_INSTANCE_STEP_RATE_0
] = 0x00000000;
993 draw
->vgt
.states
[R600_VGT__VGT_INSTANCE_STEP_RATE_1
] = 0x00000000;
994 return radeon_state_pm4(&draw
->vgt
);
997 static int r600_ps_shader(struct r600_context
*rctx
, struct r600_context_state
*rpshader
,
998 struct radeon_state
*state
)
1000 struct r600_screen
*rscreen
= rctx
->screen
;
1001 const struct pipe_rasterizer_state
*rasterizer
;
1002 struct r600_shader
*rshader
= &rpshader
->shader
;
1003 unsigned i
, tmp
, exports_ps
, num_cout
;
1004 boolean have_pos
= FALSE
, have_face
= FALSE
;
1006 rasterizer
= &rctx
->rasterizer
->state
.rasterizer
;
1008 radeon_state_init(state
, rscreen
->rw
, R600_STATE_SHADER
, 0, R600_SHADER_PS
);
1009 for (i
= 0; i
< rshader
->ninput
; i
++) {
1010 tmp
= S_028644_SEMANTIC(i
) | S_028644_SEL_CENTROID(1);
1011 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
1013 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
||
1014 rshader
->input
[i
].name
== TGSI_SEMANTIC_BCOLOR
||
1015 rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
) {
1016 tmp
|= S_028644_FLAT_SHADE(rshader
->flat_shade
);
1019 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
1022 if (rasterizer
->sprite_coord_enable
& (1 << i
)) {
1023 tmp
|= S_028644_PT_SPRITE_TEX(1);
1025 state
->states
[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0
+ i
] = tmp
;
1030 for (i
= 0; i
< rshader
->noutput
; i
++) {
1031 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
1032 exports_ps
|= S_028854_EXPORT_Z(1);
1033 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
1037 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
1038 if (exports_ps
== 0) {
1039 /* Always at least export 1 color component per pixel. */
1040 exports_ps
= S_028854_EXPORT_COLORS(1);
1042 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_0
] =
1043 S_0286CC_NUM_INTERP(rshader
->ninput
) |
1044 S_0286CC_PERSP_GRADIENT_ENA(1);
1047 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_0
] |=
1048 S_0286CC_POSITION_ENA(1) |
1049 S_0286CC_BARYC_SAMPLE_CNTL(1);
1050 state
->states
[R600_PS_SHADER__SPI_INPUT_Z
] |=
1051 S_0286D8_PROVIDE_Z_TO_SPI(1);
1054 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_1
] =
1055 S_0286D0_FRONT_FACE_ENA(have_face
);
1057 state
->states
[R600_PS_SHADER__SQ_PGM_RESOURCES_PS
] =
1058 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
1059 S_028868_STACK_SIZE(rshader
->bc
.nstack
);
1060 state
->states
[R600_PS_SHADER__SQ_PGM_EXPORTS_PS
] = exports_ps
;
1061 radeon_ws_bo_reference(rscreen
->rw
, &state
->bo
[0], rpshader
->bo
);
1063 state
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
1064 return radeon_state_pm4(state
);
1067 static int r600_vs_shader(struct r600_context
*rctx
, struct r600_context_state
*rpshader
,
1068 struct radeon_state
*state
)
1070 struct r600_screen
*rscreen
= rctx
->screen
;
1071 struct r600_shader
*rshader
= &rpshader
->shader
;
1074 radeon_state_init(state
, rscreen
->rw
, R600_STATE_SHADER
, 0, R600_SHADER_VS
);
1075 for (i
= 0; i
< 10; i
++) {
1076 state
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
+ i
] = 0;
1078 /* so far never got proper semantic id from tgsi */
1079 for (i
= 0; i
< 32; i
++) {
1080 tmp
= i
<< ((i
& 3) * 8);
1081 state
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
+ i
/ 4] |= tmp
;
1083 state
->states
[R600_VS_SHADER__SPI_VS_OUT_CONFIG
] =
1084 S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2);
1085 state
->states
[R600_VS_SHADER__SQ_PGM_RESOURCES_VS
] =
1086 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
1087 S_028868_STACK_SIZE(rshader
->bc
.nstack
);
1088 radeon_ws_bo_reference(rscreen
->rw
, &state
->bo
[0], rpshader
->bo
);
1089 radeon_ws_bo_reference(rscreen
->rw
, &state
->bo
[1], rpshader
->bo
);
1091 state
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
1092 state
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
1093 return radeon_state_pm4(state
);
1096 struct r600_context_hw_state_vtbl r600_hw_state_vtbl
= {
1097 .blend
= r600_blend
,
1101 .rasterizer
= r600_rasterizer
,
1102 .scissor
= r600_scissor
,
1103 .viewport
= r600_viewport
,
1105 .sampler_border
= r600_sampler_border
,
1106 .sampler
= r600_sampler
,
1107 .resource
= r600_resource
,
1108 .cb_cntl
= r600_cb_cntl
,
1109 .vs_resource
= r600_vs_resource
,
1110 .vgt_init
= r600_draw_vgt_init
,
1111 .vgt_prim
= r600_draw_vgt_prim
,
1112 .vs_shader
= r600_vs_shader
,
1113 .ps_shader
= r600_ps_shader
,
1114 .init_config
= r600_init_config
,
1117 void r600_set_constant_buffer_file(struct pipe_context
*ctx
,
1118 uint shader
, uint index
,
1119 struct pipe_resource
*buffer
)
1121 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
1122 struct r600_context
*rctx
= r600_context(ctx
);
1123 unsigned nconstant
= 0, i
, type
, shader_class
;
1124 struct radeon_state
*rstate
, *rstates
;
1125 struct pipe_transfer
*transfer
;
1128 type
= R600_STATE_CONSTANT
;
1131 case PIPE_SHADER_VERTEX
:
1132 shader_class
= R600_SHADER_VS
;
1133 rstates
= rctx
->vs_constant
;
1135 case PIPE_SHADER_FRAGMENT
:
1136 shader_class
= R600_SHADER_PS
;
1137 rstates
= rctx
->ps_constant
;
1140 R600_ERR("unsupported %d\n", shader
);
1143 if (buffer
&& buffer
->width0
> 0) {
1144 nconstant
= buffer
->width0
/ 16;
1145 ptr
= pipe_buffer_map(ctx
, buffer
, PIPE_TRANSFER_READ
, &transfer
);
1148 for (i
= 0; i
< nconstant
; i
++) {
1149 rstate
= &rstates
[i
];
1150 radeon_state_init(rstate
, rscreen
->rw
, type
, i
, shader_class
);
1151 rstate
->states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0
] = ptr
[i
* 4 + 0];
1152 rstate
->states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0
] = ptr
[i
* 4 + 1];
1153 rstate
->states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0
] = ptr
[i
* 4 + 2];
1154 rstate
->states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0
] = ptr
[i
* 4 + 3];
1155 if (radeon_state_pm4(rstate
))
1157 radeon_draw_bind(&rctx
->draw
, rstate
);
1159 pipe_buffer_unmap(ctx
, buffer
, transfer
);
1163 void r600_set_constant_buffer_mem(struct pipe_context
*ctx
,
1164 uint shader
, uint index
,
1165 struct pipe_resource
*buffer
)
1167 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
1168 struct r600_context
*rctx
= r600_context(ctx
);
1169 unsigned nconstant
= 0, type
, shader_class
, size
;
1170 struct radeon_state
*rstate
, *rstates
;
1171 struct r600_resource
*rbuffer
= (struct r600_resource
*)buffer
;
1173 type
= R600_STATE_CBUF
;
1176 case PIPE_SHADER_VERTEX
:
1177 shader_class
= R600_SHADER_VS
;
1178 rstates
= rctx
->vs_constant
;
1180 case PIPE_SHADER_FRAGMENT
:
1181 shader_class
= R600_SHADER_PS
;
1182 rstates
= rctx
->ps_constant
;
1185 R600_ERR("unsupported %d\n", shader
);
1189 rstate
= &rstates
[0];
1191 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1193 nconstant
= buffer
->width0
/ 16;
1194 size
= ALIGN_DIVUP(nconstant
, 16);
1196 radeon_state_init(rstate
, rscreen
->rw
, type
, 0, shader_class
);
1197 rstate
->states
[R600_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0
] = size
;
1198 rstate
->states
[R600_VS_CBUF__ALU_CONST_CACHE_VS_0
] = 0;
1200 radeon_ws_bo_reference(rscreen
->rw
, &rstate
->bo
[0], rbuffer
->bo
);
1202 rstate
->placement
[0] = RADEON_GEM_DOMAIN_VRAM
;
1203 if (radeon_state_pm4(rstate
))
1205 radeon_draw_bind(&rctx
->draw
, rstate
);