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r600: Make enum alu_op_flags unsigned
[mesa.git] / src / gallium / drivers / r600 / r600_isa.h
1 /*
2 * Copyright 2012 Vadim Girlin <vadimgirlin@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Vadim Girlin
25 */
26
27 #ifndef R600_ISA_H_
28 #define R600_ISA_H_
29
30 #include "util/u_debug.h"
31
32 /* ALU flags */
33 enum alu_op_flags
34 {
35 AF_V = (1<<0), /* allowed in vector slots */
36
37 /* allowed in scalar(trans) slot (slots xyz on cayman, may be replicated
38 * to w) */
39 AF_S = (1<<1),
40
41 AF_4SLOT = (1<<2), /* uses four vector slots (e.g. DOT4) */
42 AF_4V = (AF_V | AF_4SLOT),
43 AF_VS = (AF_V | AF_S), /* allowed in any slot */
44
45 AF_KILL = (1<<4),
46 AF_PRED = (1<<5),
47 AF_SET = (1<<6),
48
49 /* e.g. MUL_PREV instructions, allowed in x/y, depends on z/w */
50 AF_PREV_INTERLEAVE = (1<<7),
51
52 AF_MOVA = (1<<8), /* all MOVA instructions */
53 AF_IEEE = (1<<10),
54
55 AF_DST_TYPE_MASK = (3<<11),
56 AF_FLOAT_DST = 0,
57 AF_INT_DST = (1<<11),
58 AF_UINT_DST = (3<<11),
59
60 /* DP instructions, 2-slot pairs */
61 AF_64 = (1<<13),
62 /* 24 bit instructions */
63 AF_24 = (1<<14),
64 /* DX10 variants */
65 AF_DX10 = (1<<15),
66
67 /* result is replicated to all channels (only if AF_4V is also set -
68 * for special handling of MULLO_INT on CM) */
69 AF_REPL = (1<<16),
70
71 /* interpolation instructions */
72 AF_INTERP = (1<<17),
73
74 /* LDS instructions */
75 AF_LDS = (1<<20),
76
77 /* e.g. DOT - depends on the next slot in the same group (x<=y/y<=z/z<=w) */
78 AF_PREV_NEXT = (1<<21),
79
80 /* int<->flt conversions */
81 AF_CVT = (1<<22),
82
83 /* commutative operation on src0 and src1 ( a op b = b op a),
84 * includes MULADDs (considering the MUL part on src0 and src1 only) */
85 AF_M_COMM = (1 << 23),
86
87 /* associative operation ((a op b) op c) == (a op (b op c)),
88 * includes MULADDs (considering the MUL part on src0 and src1 only) */
89 AF_M_ASSOC = (1 << 24),
90
91 AF_PRED_PUSH = (1 << 25),
92
93 AF_ANY_PRED = (AF_PRED | AF_PRED_PUSH),
94
95 AF_CMOV = (1 << 26),
96
97 // for SETcc, PREDSETcc, ... - type of comparison
98 AF_CMP_TYPE_MASK = (3 << 27),
99 AF_FLOAT_CMP = 0,
100 AF_INT_CMP = (1 << 27),
101 AF_UINT_CMP = (3 << 27),
102
103 /* condition codes - 3 bits */
104 AF_CC_SHIFT = 29,
105 AF_CC_MASK = (7U << AF_CC_SHIFT),
106 AF_CC_E = (0U << AF_CC_SHIFT),
107 AF_CC_GT = (1U << AF_CC_SHIFT),
108 AF_CC_GE = (2U << AF_CC_SHIFT),
109 AF_CC_NE = (3U << AF_CC_SHIFT),
110 AF_CC_LT = (4U << AF_CC_SHIFT),
111 AF_CC_LE = (5U << AF_CC_SHIFT),
112 };
113
114 /* flags for FETCH instructions (TEX/VTX) */
115 enum fetch_op_flags
116 {
117 FF_GDS = (1<<0),
118 FF_TEX = (1<<1),
119
120 FF_SETGRAD = (1<<2),
121 FF_GETGRAD = (1<<3),
122 FF_USEGRAD = (1<<4),
123
124 FF_VTX = (1<<5),
125 FF_MEM = (1<<6),
126
127 FF_SET_TEXTURE_OFFSETS = (1<<7),
128 FF_USE_TEXTURE_OFFSETS = (1<<8),
129 };
130
131 /* flags for CF instructions */
132 enum cf_op_flags
133 {
134 CF_CLAUSE = (1<<0), /* execute clause (alu/fetch ...) */
135 CF_ACK = (1<<1), /* acked versions of some instructions */
136 CF_ALU = (1<<2), /* alu clause execution */
137 CF_ALU_EXT = (1<<3), /* ALU_EXTENDED */
138 CF_EXP = (1<<4), /* export (CF_ALLOC_EXPORT_WORD1_SWIZ) */
139 CF_BRANCH = (1<<5), /* branch instructions */
140 CF_LOOP = (1<<6), /* loop instructions */
141 CF_CALL = (1<<7), /* call instructions */
142 CF_MEM = (1<<8), /* export_mem (CF_ALLOC_EXPORT_WORD1_BUF) */
143 CF_FETCH = (1<<9), /* fetch clause */
144
145 CF_UNCOND = (1<<10), /* COND = ACTIVE required */
146 CF_EMIT = (1<<11),
147 CF_STRM = (1<<12), /* MEM_STREAM* */
148
149 CF_RAT = (1<<13), /* MEM_RAT* */
150
151 CF_LOOP_START = (1<<14)
152 };
153
154 /* ALU instruction info */
155 struct alu_op_info
156 {
157 /* instruction name */
158 const char *name;
159 /* number of source operands */
160 int src_count;
161 /* opcodes, [0] - for r6xx/r7xx, [1] - for evergreen/cayman
162 * (-1) if instruction doesn't exist (more precise info in "slots") */
163 int opcode[2];
164 /* slots for r6xx, r7xx, evergreen, cayman
165 * (0 if instruction doesn't exist for chip class) */
166 int slots[4];
167 /* flags (mostly autogenerated from instruction name) */
168 unsigned int flags;
169 };
170
171 /* FETCH instruction info */
172 struct fetch_op_info
173 {
174 const char * name;
175 /* for every chip class */
176 int opcode[4];
177 int flags;
178 };
179
180 /* CF instruction info */
181 struct cf_op_info
182 {
183 const char * name;
184 /* for every chip class */
185 int opcode[4];
186 int flags;
187 };
188
189 static const struct alu_op_info alu_op_table[] = {
190 {"ADD", 2, { 0x00, 0x00 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC },
191 {"MUL", 2, { 0x01, 0x01 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC },
192 {"MUL_IEEE", 2, { 0x02, 0x02 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_IEEE },
193 {"MAX", 2, { 0x03, 0x03 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC },
194 {"MIN", 2, { 0x04, 0x04 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC },
195 {"MAX_DX10", 2, { 0x05, 0x05 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_DX10 },
196 {"MIN_DX10", 2, { 0x06, 0x06 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_DX10 },
197 {"SETE", 2, { 0x08, 0x08 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_E },
198 {"SETGT", 2, { 0x09, 0x09 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_GT },
199 {"SETGE", 2, { 0x0A, 0x0A },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_GE },
200 {"SETNE", 2, { 0x0B, 0x0B },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_NE },
201 {"SETE_DX10", 2, { 0x0C, 0x0C },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_E | AF_DX10 | AF_INT_DST },
202 {"SETGT_DX10", 2, { 0x0D, 0x0D },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_GT | AF_DX10 | AF_INT_DST },
203 {"SETGE_DX10", 2, { 0x0E, 0x0E },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_GE | AF_DX10 | AF_INT_DST },
204 {"SETNE_DX10", 2, { 0x0F, 0x0F },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_NE | AF_DX10 | AF_INT_DST },
205 {"FRACT", 1, { 0x10, 0x10 },{ AF_VS, AF_VS, AF_VS, AF_VS}, 0 },
206 {"TRUNC", 1, { 0x11, 0x11 },{ AF_VS, AF_VS, AF_VS, AF_VS}, 0 },
207 {"CEIL", 1, { 0x12, 0x12 },{ AF_VS, AF_VS, AF_VS, AF_VS}, 0 },
208 {"RNDNE", 1, { 0x13, 0x13 },{ AF_VS, AF_VS, AF_VS, AF_VS}, 0 },
209 {"FLOOR", 1, { 0x14, 0x14 },{ AF_VS, AF_VS, AF_VS, AF_VS}, 0 },
210 {"ASHR_INT", 2, { 0x70, 0x15 },{ AF_S, AF_VS, AF_VS, AF_VS}, AF_INT_DST },
211 {"LSHR_INT", 2, { 0x71, 0x16 },{ AF_S, AF_VS, AF_VS, AF_VS}, AF_INT_DST },
212 {"LSHL_INT", 2, { 0x72, 0x17 },{ AF_S, AF_VS, AF_VS, AF_VS}, AF_INT_DST },
213 {"MOV", 1, { 0x19, 0x19 },{ AF_VS, AF_VS, AF_VS, AF_VS}, 0 },
214 {"ALU_NOP", 0, { 0x1A, 0x1A },{ AF_VS, AF_VS, AF_VS, AF_VS}, 0 },
215 {"PRED_SETGT_UINT", 2, { 0x1E, 0x1E },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_GT | AF_UINT_CMP },
216 {"PRED_SETGE_UINT", 2, { 0x1F, 0x1F },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_GE | AF_UINT_CMP },
217 {"PRED_SETE", 2, { 0x20, 0x20 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_E },
218 {"PRED_SETGT", 2, { 0x21, 0x21 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_GT },
219 {"PRED_SETGE", 2, { 0x22, 0x22 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_GE },
220 {"PRED_SETNE", 2, { 0x23, 0x23 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_NE },
221 {"PRED_SET_INV", 1, { 0x24, 0x24 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED },
222 {"PRED_SET_POP", 2, { 0x25, 0x25 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED },
223 {"PRED_SET_CLR", 0, { 0x26, 0x26 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED },
224 {"PRED_SET_RESTORE", 1, { 0x27, 0x27 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED },
225 {"PRED_SETE_PUSH", 2, { 0x28, 0x28 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_E },
226 {"PRED_SETGT_PUSH", 2, { 0x29, 0x29 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_GT },
227 {"PRED_SETGE_PUSH", 2, { 0x2A, 0x2A },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_GE },
228 {"PRED_SETNE_PUSH", 2, { 0x2B, 0x2B },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_NE },
229 {"KILLE", 2, { 0x2C, 0x2C },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_E },
230 {"KILLGT", 2, { 0x2D, 0x2D },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_GT },
231 {"KILLGE", 2, { 0x2E, 0x2E },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_GE },
232 {"KILLNE", 2, { 0x2F, 0x2F },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_NE },
233 {"AND_INT", 2, { 0x30, 0x30 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
234 {"OR_INT", 2, { 0x31, 0x31 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
235 {"XOR_INT", 2, { 0x32, 0x32 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
236 {"NOT_INT", 1, { 0x33, 0x33 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_INT_DST },
237 {"ADD_INT", 2, { 0x34, 0x34 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
238 {"SUB_INT", 2, { 0x35, 0x35 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_INT_DST },
239 {"MAX_INT", 2, { 0x36, 0x36 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
240 {"MIN_INT", 2, { 0x37, 0x37 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
241 {"MAX_UINT", 2, { 0x38, 0x38 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_UINT_DST },
242 {"MIN_UINT", 2, { 0x39, 0x39 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_UINT_DST },
243 {"SETE_INT", 2, { 0x3A, 0x3A },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_E | AF_INT_DST | AF_INT_CMP },
244 {"SETGT_INT", 2, { 0x3B, 0x3B },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_GT | AF_INT_DST | AF_INT_CMP },
245 {"SETGE_INT", 2, { 0x3C, 0x3C },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_GE | AF_INT_DST | AF_INT_CMP },
246 {"SETNE_INT", 2, { 0x3D, 0x3D },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_NE | AF_INT_DST | AF_INT_CMP },
247 {"SETGT_UINT", 2, { 0x3E, 0x3E },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_GT | AF_UINT_DST | AF_UINT_CMP },
248 {"SETGE_UINT", 2, { 0x3F, 0x3F },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_GE | AF_UINT_DST | AF_UINT_CMP },
249 {"KILLGT_UINT", 2, { 0x40, 0x40 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_GT | AF_UINT_CMP },
250 {"KILLGE_UINT", 2, { 0x41, 0x41 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_GE | AF_UINT_CMP },
251 {"PRED_SETE_INT", 2, { 0x42, 0x42 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_E | AF_INT_CMP },
252 {"PRED_SETGT_INT", 2, { 0x43, 0x43 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_GT | AF_INT_CMP },
253 {"PRED_SETGE_INT", 2, { 0x44, 0x44 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_GE | AF_INT_CMP },
254 {"PRED_SETNE_INT", 2, { 0x45, 0x45 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_NE | AF_INT_CMP },
255 {"KILLE_INT", 2, { 0x46, 0x46 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_E | AF_INT_CMP },
256 {"KILLGT_INT", 2, { 0x47, 0x47 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_GT | AF_INT_CMP },
257 {"KILLGE_INT", 2, { 0x48, 0x48 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_GE | AF_INT_CMP },
258 {"KILLNE_INT", 2, { 0x49, 0x49 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_NE | AF_INT_CMP },
259 {"PRED_SETE_PUSH_INT", 2, { 0x4A, 0x4A },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_E | AF_INT_CMP },
260 {"PRED_SETGT_PUSH_INT", 2, { 0x4B, 0x4B },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_GT | AF_INT_CMP },
261 {"PRED_SETGE_PUSH_INT", 2, { 0x4C, 0x4C },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_GE | AF_INT_CMP },
262 {"PRED_SETNE_PUSH_INT", 2, { 0x4D, 0x4D },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_NE | AF_INT_CMP },
263 {"PRED_SETLT_PUSH_INT", 2, { 0x4E, 0x4E },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_LT | AF_INT_CMP },
264 {"PRED_SETLE_PUSH_INT", 2, { 0x4F, 0x4F },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_LE | AF_INT_CMP },
265 {"FLT_TO_INT", 1, { 0x6B, 0x50 },{ AF_S, AF_S, AF_V, AF_V}, AF_INT_DST | AF_CVT },
266 {"BFREV_INT", 1, { -1, 0x51 },{ 0, 0, AF_VS, AF_VS}, AF_INT_DST },
267 {"ADDC_UINT", 2, { -1, 0x52 },{ 0, 0, AF_VS, AF_VS}, AF_UINT_DST },
268 {"SUBB_UINT", 2, { -1, 0x53 },{ 0, 0, AF_VS, AF_VS}, AF_UINT_DST },
269 {"GROUP_BARRIER", 0, { -1, 0x54 },{ 0, 0, AF_VS, AF_VS}, 0 },
270 {"GROUP_SEQ_BEGIN", 0, { -1, 0x55 },{ 0, 0, AF_VS, 0}, 0 },
271 {"GROUP_SEQ_END", 0, { -1, 0x56 },{ 0, 0, AF_VS, 0}, 0 },
272 {"SET_MODE", 2, { -1, 0x57 },{ 0, 0, AF_VS, AF_VS}, 0 },
273 {"SET_CF_IDX0", 0, { -1, 0x58 },{ 0, 0, AF_VS, 0}, 0 },
274 {"SET_CF_IDX1", 0, { -1, 0x59 },{ 0, 0, AF_VS, 0}, 0 },
275 {"SET_LDS_SIZE", 2, { -1, 0x5A },{ 0, 0, AF_VS, AF_VS}, 0 },
276 {"MUL_INT24", 2, { -1, 0x5B },{ 0, 0, 0, AF_V}, AF_INT_DST | AF_24 },
277 {"MULHI_INT24", 2, { -1, 0x5C },{ 0, 0, 0, AF_V}, AF_INT_DST | AF_24 },
278 {"FLT_TO_INT_TRUNC", 1, { -1, 0x5D },{ 0, 0, 0, AF_V}, AF_INT_DST | AF_CVT},
279 {"EXP_IEEE", 1, { 0x61, 0x81 },{ AF_S, AF_S, AF_S, AF_S}, AF_IEEE },
280 {"LOG_CLAMPED", 1, { 0x62, 0x82 },{ AF_S, AF_S, AF_S, AF_S}, 0 },
281 {"LOG_IEEE", 1, { 0x63, 0x83 },{ AF_S, AF_S, AF_S, AF_S}, AF_IEEE },
282 {"RECIP_CLAMPED", 1, { 0x64, 0x84 },{ AF_S, AF_S, AF_S, AF_S}, 0 },
283 {"RECIP_FF", 1, { 0x65, 0x85 },{ AF_S, AF_S, AF_S, AF_S}, 0 },
284 {"RECIP_IEEE", 1, { 0x66, 0x86 },{ AF_S, AF_S, AF_S, AF_S}, AF_IEEE },
285 {"RECIPSQRT_CLAMPED", 1, { 0x67, 0x87 },{ AF_S, AF_S, AF_S, AF_S}, 0 },
286 {"RECIPSQRT_FF", 1, { 0x68, 0x88 },{ AF_S, AF_S, AF_S, AF_S}, 0 },
287 {"RECIPSQRT_IEEE", 1, { 0x69, 0x89 },{ AF_S, AF_S, AF_S, AF_S}, AF_IEEE },
288 {"SQRT_IEEE", 1, { 0x6A, 0x8A },{ AF_S, AF_S, AF_S, AF_S}, AF_IEEE },
289 {"SIN", 1, { 0x6E, 0x8D },{ AF_S, AF_S, AF_S, AF_S}, 0 },
290 {"COS", 1, { 0x6F, 0x8E },{ AF_S, AF_S, AF_S, AF_S}, 0 },
291 {"MULLO_INT", 2, { 0x73, 0x8F },{ AF_S, AF_S, AF_S, AF_4V}, AF_M_COMM | AF_INT_DST | AF_REPL},
292 {"MULHI_INT", 2, { 0x74, 0x90 },{ AF_S, AF_S, AF_S, AF_4V}, AF_M_COMM | AF_INT_DST | AF_REPL},
293 {"MULLO_UINT", 2, { 0x75, 0x91 },{ AF_S, AF_S, AF_S, AF_4V}, AF_M_COMM | AF_UINT_DST | AF_REPL},
294 {"MULHI_UINT", 2, { 0x76, 0x92 },{ AF_S, AF_S, AF_S, AF_4V}, AF_M_COMM | AF_UINT_DST | AF_REPL},
295 {"RECIP_INT", 1, { 0x77, 0x93 },{ AF_S, AF_S, AF_S, 0}, AF_INT_DST },
296 {"RECIP_UINT", 1, { 0x78, 0x94 },{ AF_S, AF_S, AF_S, 0}, AF_UINT_DST },
297 {"RECIP_64", 2, { -1, 0x95 },{ 0, 0, AF_S, AF_S}, AF_64 },
298 {"RECIP_CLAMPED_64", 2, { -1, 0x96 },{ 0, 0, AF_S, AF_S}, AF_64 },
299 {"RECIPSQRT_64", 2, { -1, 0x97 },{ 0, 0, AF_S, AF_S}, AF_64 },
300 {"RECIPSQRT_CLAMPED_64", 2, { -1, 0x98 },{ 0, 0, AF_S, AF_S}, AF_64 },
301 {"SQRT_64", 2, { -1, 0x99 },{ 0, 0, AF_S, AF_S}, AF_64 },
302 {"FLT_TO_UINT", 1, { 0x79, 0x9A },{ AF_S, AF_S, AF_S, AF_V}, AF_UINT_DST | AF_CVT},
303 {"INT_TO_FLT", 1, { 0x6C, 0x9B },{ AF_S, AF_S, AF_S, AF_V}, AF_CVT},
304 {"UINT_TO_FLT", 1, { 0x6D, 0x9C },{ AF_S, AF_S, AF_S, AF_V}, AF_CVT },
305 {"BFM_INT", 2, { -1, 0xA0 },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
306 {"FLT32_TO_FLT16", 1, { -1, 0xA2 },{ 0, 0, AF_V, AF_V}, 0 },
307 {"FLT16_TO_FLT32", 1, { -1, 0xA3 },{ 0, 0, AF_V, AF_V}, 0 },
308 {"UBYTE0_FLT", 1, { -1, 0xA4 },{ 0, 0, AF_V, AF_V}, 0 },
309 {"UBYTE1_FLT", 1, { -1, 0xA5 },{ 0, 0, AF_V, AF_V}, 0 },
310 {"UBYTE2_FLT", 1, { -1, 0xA6 },{ 0, 0, AF_V, AF_V}, 0 },
311 {"UBYTE3_FLT", 1, { -1, 0xA7 },{ 0, 0, AF_V, AF_V}, 0 },
312 {"BCNT_INT", 1, { -1, 0xAA },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
313 {"FFBH_UINT", 1, { -1, 0xAB },{ 0, 0, AF_V, AF_V}, AF_UINT_DST },
314 {"FFBL_INT", 1, { -1, 0xAC },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
315 {"FFBH_INT", 1, { -1, 0xAD },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
316 {"FLT_TO_UINT4", 1, { -1, 0xAE },{ 0, 0, AF_V, AF_V}, AF_UINT_DST },
317 {"DOT_IEEE", 2, { -1, 0xAF },{ 0, 0, AF_V, AF_V}, AF_PREV_NEXT | AF_IEEE },
318 {"FLT_TO_INT_RPI", 1, { -1, 0xB0 },{ 0, 0, AF_V, AF_V}, AF_INT_DST | AF_CVT},
319 {"FLT_TO_INT_FLOOR", 1, { -1, 0xB1 },{ 0, 0, AF_V, AF_V}, AF_INT_DST | AF_CVT},
320 {"MULHI_UINT24", 2, { -1, 0xB2 },{ 0, 0, AF_V, AF_V}, AF_UINT_DST | AF_24 },
321 {"MBCNT_32HI_INT", 1, { -1, 0xB3 },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
322 {"OFFSET_TO_FLT", 1, { -1, 0xB4 },{ 0, 0, AF_V, AF_V}, 0 },
323 {"MUL_UINT24", 2, { -1, 0xB5 },{ 0, 0, AF_V, AF_V}, AF_UINT_DST | AF_24 },
324 {"BCNT_ACCUM_PREV_INT", 1, { -1, 0xB6 },{ 0, 0, AF_V, AF_V}, AF_INT_DST | AF_PREV_NEXT },
325 {"MBCNT_32LO_ACCUM_PREV_INT", 1, { -1, 0xB7 },{ 0, 0, AF_V, AF_V}, AF_INT_DST | AF_PREV_NEXT },
326 {"SETE_64", 2, { -1, 0xB8 },{ 0, 0, AF_V, AF_V}, AF_SET | AF_CC_E | AF_64 },
327 {"SETNE_64", 2, { -1, 0xB9 },{ 0, 0, AF_V, AF_V}, AF_SET | AF_CC_NE | AF_64 },
328 {"SETGT_64", 2, { -1, 0xBA },{ 0, 0, AF_V, AF_V}, AF_SET | AF_CC_GT | AF_64 },
329 {"SETGE_64", 2, { -1, 0xBB },{ 0, 0, AF_V, AF_V}, AF_SET | AF_CC_GE | AF_64 },
330 {"MIN_64", 2, { -1, 0xBC },{ 0, 0, AF_V, AF_V}, AF_64 },
331 {"MAX_64", 2, { -1, 0xBD },{ 0, 0, AF_V, AF_V}, AF_64 },
332 {"DOT4", 2, { 0x50, 0xBE },{ AF_4V, AF_4V, AF_4V, AF_4V}, AF_REPL },
333 {"DOT4_IEEE", 2, { 0x51, 0xBF },{ AF_4V, AF_4V, AF_4V, AF_4V}, AF_REPL | AF_IEEE },
334 {"CUBE", 2, { 0x52, 0xC0 },{ AF_4V, AF_4V, AF_4V, AF_4V}, 0 },
335 {"MAX4", 1, { 0x53, 0xC1 },{ AF_4V, AF_4V, AF_4V, AF_4V}, AF_REPL },
336 {"FREXP_64", 1, { 0x07, 0xC4 },{ AF_V, AF_V, AF_V, AF_V}, AF_64 },
337 {"LDEXP_64", 2, { 0x7A, 0xC5 },{ AF_V, AF_V, AF_V, AF_V}, AF_64 },
338 {"FRACT_64", 1, { 0x7B, 0xC6 },{ AF_V, AF_V, AF_V, AF_V}, AF_64 },
339 {"PRED_SETGT_64", 2, { 0x7C, 0xC7 },{ AF_V, AF_V, AF_V, AF_V}, AF_PRED | AF_CC_GT | AF_64 },
340 {"PRED_SETE_64", 2, { 0x7D, 0xC8 },{ AF_V, AF_V, AF_V, AF_V}, AF_PRED | AF_CC_E | AF_64 },
341 {"PRED_SETGE_64", 2, { 0x7E, 0xC9 },{ AF_V, AF_V, AF_V, AF_V}, AF_PRED | AF_CC_GE | AF_64 },
342 {"MUL_64", 2, { 0x1B, 0xCA },{ AF_V, AF_V, AF_V, AF_4V}, AF_64 },
343 {"ADD_64", 2, { 0x17, 0xCB },{ AF_V, AF_V, AF_V, AF_V}, AF_64 },
344 {"MOVA_INT", 1, { 0x18, 0xCC },{ AF_V, AF_V, AF_V, AF_V}, AF_MOVA },
345 {"FLT64_TO_FLT32", 1, { 0x1C, 0xCD },{ AF_V, AF_V, AF_V, AF_V}, AF_64 },
346 {"FLT32_TO_FLT64", 1, { 0x1D, 0xCE },{ AF_V, AF_V, AF_V, AF_V}, AF_64 },
347 {"SAD_ACCUM_PREV_UINT", 2, { -1, 0xCF },{ 0, 0, AF_V, AF_V}, AF_UINT_DST | AF_PREV_NEXT },
348 {"DOT", 2, { -1, 0xD0 },{ 0, 0, AF_V, AF_V}, AF_PREV_NEXT },
349 {"MUL_PREV", 1, { -1, 0xD1 },{ 0, 0, AF_V, AF_V}, AF_PREV_INTERLEAVE },
350 {"MUL_IEEE_PREV", 1, { -1, 0xD2 },{ 0, 0, AF_V, AF_V}, AF_PREV_INTERLEAVE | AF_IEEE },
351 {"ADD_PREV", 1, { -1, 0xD3 },{ 0, 0, AF_V, AF_V}, AF_PREV_INTERLEAVE },
352 {"MULADD_PREV", 2, { -1, 0xD4 },{ 0, 0, AF_V, AF_V}, AF_PREV_INTERLEAVE },
353 {"MULADD_IEEE_PREV", 2, { -1, 0xD5 },{ 0, 0, AF_V, AF_V}, AF_PREV_INTERLEAVE | AF_IEEE },
354 {"INTERP_XY", 2, { -1, 0xD6 },{ 0, 0, AF_4V, AF_4V}, AF_INTERP },
355 {"INTERP_ZW", 2, { -1, 0xD7 },{ 0, 0, AF_4V, AF_4V}, AF_INTERP },
356 {"INTERP_X", 2, { -1, 0xD8 },{ 0, 0, AF_V, AF_V}, AF_INTERP },
357 {"INTERP_Z", 2, { -1, 0xD9 },{ 0, 0, AF_V, AF_V}, AF_INTERP },
358 {"STORE_FLAGS", 1, { -1, 0xDA },{ 0, 0, AF_V, AF_V}, 0 },
359 {"LOAD_STORE_FLAGS", 1, { -1, 0xDB },{ 0, 0, AF_V, AF_V}, 0 },
360 {"LDS_1A", 2, { -1, 0xDC },{ 0, 0, AF_V, AF_V}, 0 },
361 {"LDS_1A1D", 2, { -1, 0xDD },{ 0, 0, AF_V, AF_V}, 0 },
362 {"LDS_2A", 2, { -1, 0xDF },{ 0, 0, AF_V, AF_V}, 0 },
363 {"INTERP_LOAD_P0", 1, { -1, 0xE0 },{ 0, 0, AF_V, AF_V}, AF_INTERP },
364 {"INTERP_LOAD_P10", 1, { -1, 0xE1 },{ 0, 0, AF_V, AF_V}, AF_INTERP },
365 {"INTERP_LOAD_P20", 1, { -1, 0xE2 },{ 0, 0, AF_V, AF_V}, AF_INTERP },
366 {"BFE_UINT", 3, { -1, 0x04 },{ 0, 0, AF_V, AF_V}, AF_UINT_DST },
367 {"BFE_INT", 3, { -1, 0x05 },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
368 {"BFI_INT", 3, { -1, 0x06 },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
369 {"FMA", 3, { -1, 0x07 },{ 0, 0, AF_V, AF_V}, 0 },
370 {"MULADD_INT24", 3, { -1, 0x08 },{ 0, 0, 0, AF_V}, AF_INT_DST | AF_24 },
371 {"CNDNE_64", 3, { -1, 0x09 },{ 0, 0, AF_V, AF_V}, AF_CMOV | AF_64 },
372 {"FMA_64", 3, { -1, 0x0A },{ 0, 0, AF_V, AF_4V}, AF_64 },
373 {"LERP_UINT", 3, { -1, 0x0B },{ 0, 0, AF_V, AF_V}, AF_UINT_DST },
374 {"BIT_ALIGN_INT", 3, { -1, 0x0C },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
375 {"BYTE_ALIGN_INT", 3, { -1, 0x0D },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
376 {"SAD_ACCUM_UINT", 3, { -1, 0x0E },{ 0, 0, AF_V, AF_V}, AF_UINT_DST },
377 {"SAD_ACCUM_HI_UINT", 3, { -1, 0x0F },{ 0, 0, AF_V, AF_V}, AF_UINT_DST },
378 {"MULADD_UINT24", 3, { -1, 0x10 },{ 0, 0, AF_V, AF_V}, AF_UINT_DST | AF_24 },
379 {"LDS_IDX_OP", 3, { -1, 0x11 },{ 0, 0, AF_V, AF_V}, 0 },
380 {"MULADD", 3, { 0x10, 0x14 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC },
381 {"MULADD_M2", 3, { 0x11, 0x15 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC },
382 {"MULADD_M4", 3, { 0x12, 0x16 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC },
383 {"MULADD_D2", 3, { 0x13, 0x17 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC },
384 {"MULADD_IEEE", 3, { 0x14, 0x18 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_IEEE },
385 {"CNDE", 3, { 0x18, 0x19 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_CMOV | AF_CC_E },
386 {"CNDGT", 3, { 0x19, 0x1A },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_CMOV | AF_CC_GT },
387 {"CNDGE", 3, { 0x1A, 0x1B },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_CMOV | AF_CC_GE },
388 {"CNDE_INT", 3, { 0x1C, 0x1C },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_CMOV | AF_CC_E | AF_INT_CMP },
389 {"CNDGT_INT", 3, { 0x1D, 0x1D },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_CMOV | AF_CC_GT | AF_INT_CMP },
390 {"CNDGE_INT", 3, { 0x1E, 0x1E },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_CMOV | AF_CC_GE | AF_INT_CMP },
391 {"MUL_LIT", 3, { 0x0C, 0x1F },{ AF_S, AF_S, AF_S, AF_V}, 0 },
392
393 {"MOVA", 1, { 0x15, -1 },{ AF_V, AF_V, 0, 0}, AF_MOVA },
394 {"MOVA_FLOOR", 1, { 0x16, -1 },{ AF_V, AF_V, 0, 0}, AF_MOVA },
395 {"MOVA_GPR_INT", 1, { 0x60, -1 },{ AF_S, 0, 0, 0}, AF_MOVA },
396
397 {"MULADD_64", 3, { 0x08, -1 },{ AF_V, AF_V, 0, 0}, AF_64 },
398 {"MULADD_64_M2", 3, { 0x09, -1 },{ AF_V, AF_V, 0, 0}, AF_64 },
399 {"MULADD_64_M4", 3, { 0x0A, -1 },{ AF_V, AF_V, 0, 0}, AF_64 },
400 {"MULADD_64_D2", 3, { 0x0B, -1 },{ AF_V, AF_V, 0, 0}, AF_64 },
401 {"MUL_LIT_M2", 3, { 0x0D, -1 },{ AF_VS, AF_VS, 0, 0}, 0 },
402 {"MUL_LIT_M4", 3, { 0x0E, -1 },{ AF_VS, AF_VS, 0, 0}, 0 },
403 {"MUL_LIT_D2", 3, { 0x0F, -1 },{ AF_VS, AF_VS, 0, 0}, 0 },
404 {"MULADD_IEEE_M2", 3, { 0x15, -1 },{ AF_VS, AF_VS, 0, 0}, AF_M_COMM | AF_M_ASSOC | AF_IEEE },
405 {"MULADD_IEEE_M4", 3, { 0x16, -1 },{ AF_VS, AF_VS, 0, 0}, AF_M_COMM | AF_M_ASSOC | AF_IEEE },
406 {"MULADD_IEEE_D2", 3, { 0x17, -1 },{ AF_VS, AF_VS, 0, 0}, AF_M_COMM | AF_M_ASSOC | AF_IEEE },
407
408 {"LDS_ADD", 2, { -1, 0x0011 },{ 0, 0, AF_V, AF_V}, AF_LDS },
409 {"LDS_SUB", 2, { -1, 0x0111 },{ 0, 0, AF_V, AF_V}, AF_LDS },
410 {"LDS_RSUB", 2, { -1, 0x0211 },{ 0, 0, AF_V, AF_V}, AF_LDS },
411 {"LDS_INC", 2, { -1, 0x0311 },{ 0, 0, AF_V, AF_V}, AF_LDS },
412 {"LDS_DEC", 2, { -1, 0x0411 },{ 0, 0, AF_V, AF_V}, AF_LDS },
413 {"LDS_MIN_INT", 2, { -1, 0x0511 },{ 0, 0, AF_V, AF_V}, AF_LDS | AF_INT_DST },
414 {"LDS_MAX_INT", 2, { -1, 0x0611 },{ 0, 0, AF_V, AF_V}, AF_LDS | AF_INT_DST },
415 {"LDS_MIN_UINT", 2, { -1, 0x0711 },{ 0, 0, AF_V, AF_V}, AF_LDS | AF_UINT_DST },
416 {"LDS_MAX_UINT", 2, { -1, 0x0811 },{ 0, 0, AF_V, AF_V}, AF_LDS | AF_UINT_DST },
417 {"LDS_AND", 2, { -1, 0x0911 },{ 0, 0, AF_V, AF_V}, AF_LDS },
418 {"LDS_OR", 2, { -1, 0x0A11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
419 {"LDS_XOR", 2, { -1, 0x0B11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
420 {"LDS_MSKOR", 3, { -1, 0x0C11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
421 {"LDS_WRITE", 2, { -1, 0x0D11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
422 {"LDS_WRITE_REL", 3, { -1, 0x0E11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
423 {"LDS_WRITE2", 3, { -1, 0x0F11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
424 {"LDS_CMP_STORE", 3, { -1, 0x1011 },{ 0, 0, AF_V, AF_V}, AF_LDS },
425 {"LDS_CMP_STORE_SPF", 3, { -1, 0x1111 },{ 0, 0, AF_V, AF_V}, AF_LDS },
426 {"LDS_BYTE_WRITE", 2, { -1, 0x1211 },{ 0, 0, AF_V, AF_V}, AF_LDS },
427 {"LDS_SHORT_WRITE", 2, { -1, 0x1311 },{ 0, 0, AF_V, AF_V}, AF_LDS },
428 {"LDS_ADD_RET", 2, { -1, 0x2011 },{ 0, 0, AF_V, AF_V}, AF_LDS },
429 {"LDS_SUB_RET", 2, { -1, 0x2111 },{ 0, 0, AF_V, AF_V}, AF_LDS },
430 {"LDS_RSUB_RET", 2, { -1, 0x2211 },{ 0, 0, AF_V, AF_V}, AF_LDS },
431 {"LDS_INC_RET", 2, { -1, 0x2311 },{ 0, 0, AF_V, AF_V}, AF_LDS },
432 {"LDS_DEC_RET", 2, { -1, 0x2411 },{ 0, 0, AF_V, AF_V}, AF_LDS },
433 {"LDS_MIN_INT_RET", 2, { -1, 0x2511 },{ 0, 0, AF_V, AF_V}, AF_LDS | AF_INT_DST },
434 {"LDS_MAX_INT_RET", 2, { -1, 0x2611 },{ 0, 0, AF_V, AF_V}, AF_LDS | AF_INT_DST },
435 {"LDS_MIN_UINT_RET", 2, { -1, 0x2711 },{ 0, 0, AF_V, AF_V}, AF_LDS | AF_UINT_DST },
436 {"LDS_MAX_UINT_RET", 2, { -1, 0x2811 },{ 0, 0, AF_V, AF_V}, AF_LDS | AF_UINT_DST },
437 {"LDS_AND_RET", 2, { -1, 0x2911 },{ 0, 0, AF_V, AF_V}, AF_LDS },
438 {"LDS_OR_RET", 2, { -1, 0x2A11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
439 {"LDS_XOR_RET", 2, { -1, 0x2B11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
440 {"LDS_MSKOR_RET", 3, { -1, 0x2C11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
441 {"LDS_XCHG_RET", 2, { -1, 0x2D11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
442 {"LDS_XCHG_REL_RET", 3, { -1, 0x2E11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
443 {"LDS_XCHG2_RET", 3, { -1, 0x2F11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
444 {"LDS_CMP_XCHG_RET", 3, { -1, 0x3011 },{ 0, 0, AF_V, AF_V}, AF_LDS },
445 {"LDS_CMP_XCHG_SPF_RET", 3, { -1, 0x3111 },{ 0, 0, AF_V, AF_V}, AF_LDS },
446 {"LDS_READ_RET", 1, { -1, 0x3211 },{ 0, 0, AF_V, AF_V}, AF_LDS },
447 {"LDS_READ_REL_RET", 1, { -1, 0x3311 },{ 0, 0, AF_V, AF_V}, AF_LDS },
448 {"LDS_READ2_RET", 2, { -1, 0x3411 },{ 0, 0, AF_V, AF_V}, AF_LDS },
449 {"LDS_READWRITE_RET", 3, { -1, 0x3511 },{ 0, 0, AF_V, AF_V}, AF_LDS },
450 {"LDS_BYTE_READ_RET", 1, { -1, 0x3611 },{ 0, 0, AF_V, AF_V}, AF_LDS },
451 {"LDS_UBYTE_READ_RET", 1, { -1, 0x3711 },{ 0, 0, AF_V, AF_V}, AF_LDS },
452 {"LDS_SHORT_READ_RET", 1, { -1, 0x3811 },{ 0, 0, AF_V, AF_V}, AF_LDS },
453 {"LDS_USHORT_READ_RET", 1, { -1, 0x3911 },{ 0, 0, AF_V, AF_V}, AF_LDS },
454 };
455
456 static const struct fetch_op_info fetch_op_table[] = {
457 {"VFETCH", { 0x000000, 0x000000, 0x000000, 0x000000 }, FF_VTX },
458 {"SEMFETCH", { 0x000001, 0x000001, 0x000001, 0x000001 }, FF_VTX },
459
460 {"READ_SCRATCH", { -1, 0x000002, 0x000002, 0x000002 }, FF_VTX | FF_MEM },
461 {"READ_REDUCT", { -1, 0x000102, -1, -1 }, FF_VTX | FF_MEM },
462 {"READ_MEM", { -1, 0x000202, 0x000202, 0x000202 }, FF_VTX | FF_MEM },
463 {"DS_LOCAL_WRITE", { -1, 0x000402, -1, -1 }, FF_VTX | FF_MEM },
464 {"DS_LOCAL_READ", { -1, 0x000502, -1, -1 }, FF_VTX | FF_MEM },
465
466 {"GDS_ADD", { -1, -1, 0x020002, 0x020002 }, FF_GDS },
467 {"GDS_SUB", { -1, -1, 0x020102, 0x020102 }, FF_GDS },
468 {"GDS_RSUB", { -1, -1, 0x020202, 0x020202 }, FF_GDS },
469 {"GDS_INC", { -1, -1, 0x020302, 0x020302 }, FF_GDS },
470 {"GDS_DEC", { -1, -1, 0x020402, 0x020402 }, FF_GDS },
471 {"GDS_MIN_INT", { -1, -1, 0x020502, 0x020502 }, FF_GDS },
472 {"GDS_MAX_INT", { -1, -1, 0x020602, 0x020602 }, FF_GDS },
473 {"GDS_MIN_UINT", { -1, -1, 0x020702, 0x020702 }, FF_GDS },
474 {"GDS_MAX_UINT", { -1, -1, 0x020802, 0x020802 }, FF_GDS },
475 {"GDS_AND", { -1, -1, 0x020902, 0x020902 }, FF_GDS },
476 {"GDS_OR", { -1, -1, 0x020A02, 0x020A02 }, FF_GDS },
477 {"GDS_XOR", { -1, -1, 0x020B02, 0x020B02 }, FF_GDS },
478 {"GDS_MSKOR", { -1, -1, 0x030C02, 0x030C02 }, FF_GDS },
479 {"GDS_WRITE", { -1, -1, 0x020D02, 0x020D02 }, FF_GDS },
480 {"GDS_WRITE_REL", { -1, -1, 0x030E02, 0x030E02 }, FF_GDS },
481 {"GDS_WRITE2", { -1, -1, 0x030F02, 0x030F02 }, FF_GDS },
482 {"GDS_CMP_STORE", { -1, -1, 0x031002, 0x031002 }, FF_GDS },
483 {"GDS_CMP_STORE_SPF", { -1, -1, 0x031102, 0x031102 }, FF_GDS },
484 {"GDS_BYTE_WRITE", { -1, -1, 0x021202, 0x021202 }, FF_GDS },
485 {"GDS_SHORT_WRITE", { -1, -1, 0x021302, 0x021302 }, FF_GDS },
486 {"GDS_ADD_RET", { -1, -1, 0x122002, 0x122002 }, FF_GDS },
487 {"GDS_SUB_RET", { -1, -1, 0x122102, 0x122102 }, FF_GDS },
488 {"GDS_RSUB_RET", { -1, -1, 0x122202, 0x122202 }, FF_GDS },
489 {"GDS_INC_RET", { -1, -1, 0x122302, 0x122302 }, FF_GDS },
490 {"GDS_DEC_RET", { -1, -1, 0x122402, 0x122402 }, FF_GDS },
491 {"GDS_MIN_INT_RET", { -1, -1, 0x122502, 0x122502 }, FF_GDS },
492 {"GDS_MAX_INT_RET", { -1, -1, 0x122602, 0x122602 }, FF_GDS },
493 {"GDS_MIN_UINT_RET", { -1, -1, 0x122702, 0x122702 }, FF_GDS },
494 {"GDS_MAX_UINT_RET", { -1, -1, 0x122802, 0x122802 }, FF_GDS },
495 {"GDS_AND_RET", { -1, -1, 0x122902, 0x122902 }, FF_GDS },
496 {"GDS_OR_RET", { -1, -1, 0x122A02, 0x122A02 }, FF_GDS },
497 {"GDS_XOR_RET", { -1, -1, 0x122B02, 0x122B02 }, FF_GDS },
498 {"GDS_MSKOR_RET", { -1, -1, 0x132C02, 0x132C02 }, FF_GDS },
499 {"GDS_XCHG_RET", { -1, -1, 0x122D02, 0x122D02 }, FF_GDS },
500 {"GDS_XCHG_REL_RET", { -1, -1, 0x232E02, 0x232E02 }, FF_GDS },
501 {"GDS_XCHG2_RET", { -1, -1, 0x232F02, 0x232F02 }, FF_GDS },
502 {"GDS_CMP_XCHG_RET", { -1, -1, 0x133002, 0x133002 }, FF_GDS },
503 {"GDS_CMP_XCHG_SPF_RET", { -1, -1, 0x133102, 0x133102 }, FF_GDS },
504 {"GDS_READ_RET", { -1, -1, 0x113202, 0x113202 }, FF_GDS },
505 {"GDS_READ_REL_RET", { -1, -1, 0x213302, 0x213302 }, FF_GDS },
506 {"GDS_READ2_RET", { -1, -1, 0x223402, 0x223402 }, FF_GDS },
507 {"GDS_READWRITE_RET", { -1, -1, 0x133502, 0x133502 }, FF_GDS },
508 {"GDS_BYTE_READ_RET", { -1, -1, 0x113602, 0x113602 }, FF_GDS },
509 {"GDS_UBYTE_READ_RET", { -1, -1, 0x113702, 0x113702 }, FF_GDS },
510 {"GDS_SHORT_READ_RET", { -1, -1, 0x113802, 0x113802 }, FF_GDS },
511 {"GDS_USHORT_READ_RET", { -1, -1, 0x113902, 0x113902 }, FF_GDS },
512 {"GDS_ATOMIC_ORDERED_ALLOC", { -1, -1, 0x113F02, 0x113F02 }, FF_GDS },
513
514 {"TF_WRITE", { -1, -1, 0x020502, 0x020502 }, FF_GDS },
515
516 {"DS_GLOBAL_WRITE", { -1, 0x000602, -1, -1 }, 0 },
517 {"DS_GLOBAL_READ", { -1, 0x000702, -1, -1 }, 0 },
518
519 {"LD", { 0x000003, 0x000003, 0x000003, 0x000003 }, 0 },
520 {"LDFPTR", { -1, -1, 0x000103, 0x000103 }, 0 },
521 {"GET_TEXTURE_RESINFO", { 0x000004, 0x000004, 0x000004, 0x000004 }, 0 },
522 {"GET_NUMBER_OF_SAMPLES", { 0x000005, 0x000005, 0x000005, 0x000005 }, 0 },
523 {"GET_LOD", { 0x000006, 0x000006, 0x000006, 0x000006 }, 0 },
524 {"GET_GRADIENTS_H", { 0x000007, 0x000007, 0x000007, 0x000007 }, FF_GETGRAD },
525 {"GET_GRADIENTS_V", { 0x000008, 0x000008, 0x000008, 0x000008 }, FF_GETGRAD },
526 {"GET_GRADIENTS_H_FINE", { -1, -1, 0x000107, 0x000107 }, FF_GETGRAD },
527 {"GET_GRADIENTS_V_FINE", { -1, -1, 0x000108, 0x000108 }, FF_GETGRAD },
528 {"GET_LERP", { 0x000009, 0x000009, -1, -1 }, 0 },
529 {"SET_TEXTURE_OFFSETS", { -1, -1, 0x000009, 0x000009 }, FF_SET_TEXTURE_OFFSETS },
530 {"KEEP_GRADIENTS", { -1, 0x00000A, 0x00000A, 0x00000A }, 0 },
531 {"SET_GRADIENTS_H", { 0x00000B, 0x00000B, 0x00000B, 0x00000B }, FF_SETGRAD },
532 {"SET_GRADIENTS_V", { 0x00000C, 0x00000C, 0x00000C, 0x00000C }, FF_SETGRAD },
533 {"SET_GRADIENTS_H_COARSE", { -1, -1, -1, 0x00010B }, FF_SETGRAD },
534 {"SET_GRADIENTS_V_COARSE", { -1, -1, -1, 0x00010C }, FF_SETGRAD },
535 {"SET_GRADIENTS_H_PACKED_FINE", { -1, -1, -1, 0x00020B }, FF_SETGRAD },
536 {"SET_GRADIENTS_V_PACKED_FINE", { -1, -1, -1, 0x00020C }, FF_SETGRAD },
537 {"SET_GRADIENTS_H_PACKED_COARSE", { -1, -1, -1, 0x00030B }, FF_SETGRAD },
538 {"SET_GRADIENTS_V_PACKED_COARSE", { -1, -1, -1, 0x00030C }, FF_SETGRAD },
539 {"PASS", { 0x00000D, 0x00000D, 0x00000D, 0x00000D }, 0 }, /* ???? 700, eg, cm docs - marked as reserved */
540 {"PASS1", { -1, -1, 0x00010D, 0x00010D }, 0 },
541 {"PASS2", { -1, -1, 0x00020D, 0x00020D }, 0 },
542 {"PASS3", { -1, -1, 0x00030D, 0x00030D }, 0 },
543 {"SET_CUBEMAP_INDEX", { 0x00000E, 0x00000E, -1, -1 }, 0 },
544 {"GET_BUFFER_RESINFO", { -1, -1, 0x00000E, 0x00000E }, FF_VTX },
545 {"FETCH4", { 0x00000F, 0x00000F, -1, -1 }, 0 },
546
547 {"SAMPLE", { 0x000010, 0x000010, 0x000010, 0x000010 }, FF_TEX },
548 {"SAMPLE_L", { 0x000011, 0x000011, 0x000011, 0x000011 }, FF_TEX },
549 {"SAMPLE_LB", { 0x000012, 0x000012, 0x000012, 0x000012 }, FF_TEX },
550 {"SAMPLE_LZ", { 0x000013, 0x000013, 0x000013, 0x000013 }, FF_TEX },
551 {"SAMPLE_G", { 0x000014, 0x000014, 0x000014, 0x000014 }, FF_TEX | FF_USEGRAD },
552 {"SAMPLE_G_L", { 0x000015, 0x000015, -1, -1 }, FF_TEX | FF_USEGRAD},
553 {"GATHER4", { -1, -1, 0x000015, 0x000015 }, FF_TEX },
554 {"SAMPLE_G_LB", { 0x000016, 0x000016, 0x000016, 0x000016 }, FF_TEX | FF_USEGRAD},
555 {"SAMPLE_G_LZ", { 0x000017, 0x000017, -1, -1 }, FF_TEX | FF_USEGRAD},
556 {"GATHER4_O", { -1, -1, 0x000017, 0x000017 }, FF_TEX | FF_USE_TEXTURE_OFFSETS},
557 {"SAMPLE_C", { 0x000018, 0x000018, 0x000018, 0x000018 }, FF_TEX },
558 {"SAMPLE_C_L", { 0x000019, 0x000019, 0x000019, 0x000019 }, FF_TEX },
559 {"SAMPLE_C_LB", { 0x00001A, 0x00001A, 0x00001A, 0x00001A }, FF_TEX },
560 {"SAMPLE_C_LZ", { 0x00001B, 0x00001B, 0x00001B, 0x00001B }, FF_TEX },
561 {"SAMPLE_C_G", { 0x00001C, 0x00001C, 0x00001C, 0x00001C }, FF_TEX | FF_USEGRAD},
562 {"SAMPLE_C_G_L", { 0x00001D, 0x00001D, -1, -1 }, FF_TEX | FF_USEGRAD},
563 {"GATHER4_C", { -1, -1, 0x00001D, 0x00001D }, FF_TEX },
564 {"SAMPLE_C_G_LB", { 0x00001E, 0x00001E, 0x00001E, 0x00001E }, FF_TEX | FF_USEGRAD},
565 {"SAMPLE_C_G_LZ", { 0x00001F, 0x00001F, -1, -1 }, FF_TEX | FF_USEGRAD},
566 {"GATHER4_C_O", { -1, -1, 0x00001F, 0x00001F }, FF_TEX | FF_USE_TEXTURE_OFFSETS}
567 };
568
569 static const struct cf_op_info cf_op_table[] = {
570 {"NOP", { 0x00, 0x00, 0x00, 0x00 }, 0 },
571
572 {"TEX", { 0x01, 0x01, 0x01, 0x01 }, CF_CLAUSE | CF_FETCH | CF_UNCOND }, /* merged with "TC" entry */
573 {"VTX", { 0x02, 0x02, 0x02, -1 }, CF_CLAUSE | CF_FETCH | CF_UNCOND }, /* merged with "VC" entry */
574 {"VTX_TC", { 0x03, 0x03, -1, -1 }, CF_CLAUSE | CF_FETCH | CF_UNCOND },
575 {"GDS", { -1, -1, 0x03, 0x03 }, CF_CLAUSE | CF_FETCH | CF_UNCOND },
576
577 {"LOOP_START", { 0x04, 0x04, 0x04, 0x04 }, CF_LOOP | CF_LOOP_START },
578 {"LOOP_END", { 0x05, 0x05, 0x05, 0x05 }, CF_LOOP },
579 {"LOOP_START_DX10", { 0x06, 0x06, 0x06, 0x06 }, CF_LOOP | CF_LOOP_START },
580 {"LOOP_START_NO_AL", { 0x07, 0x07, 0x07, 0x07 }, CF_LOOP | CF_LOOP_START },
581 {"LOOP_CONTINUE", { 0x08, 0x08, 0x08, 0x08 }, CF_LOOP },
582 {"LOOP_BREAK", { 0x09, 0x09, 0x09, 0x09 }, CF_LOOP },
583 {"JUMP", { 0x0A, 0x0A, 0x0A, 0x0A }, CF_BRANCH },
584 {"PUSH", { 0x0B, 0x0B, 0x0B, 0x0B }, CF_BRANCH },
585 {"PUSH_ELSE", { 0x0C, 0x0C, -1, -1 }, CF_BRANCH },
586 {"ELSE", { 0x0D, 0x0D, 0x0D, 0x0D }, CF_BRANCH },
587 {"POP", { 0x0E, 0x0E, 0x0E, 0x0E }, CF_BRANCH },
588 {"POP_JUMP", { 0x0F, 0x0F, -1, -1 }, CF_BRANCH },
589 {"POP_PUSH", { 0x10, 0x10, -1, -1 }, CF_BRANCH },
590 {"POP_PUSH_ELSE", { 0x11, 0x11, -1, -1 }, CF_BRANCH },
591 {"CALL", { 0x12, 0x12, 0x12, 0x12 }, CF_CALL },
592 {"CALL_FS", { 0x13, 0x13, 0x13, 0x13 }, CF_CALL },
593 {"RET", { 0x14, 0x14, 0x14, 0x14 }, 0 },
594 {"EMIT_VERTEX", { 0x15, 0x15, 0x15, 0x15 }, CF_EMIT | CF_UNCOND },
595 {"EMIT_CUT_VERTEX", { 0x16, 0x16, 0x16, 0x16 }, CF_EMIT | CF_UNCOND },
596 {"CUT_VERTEX", { 0x17, 0x17, 0x17, 0x17 }, CF_EMIT | CF_UNCOND },
597 {"KILL", { 0x18, 0x18, 0x18, 0x18 }, CF_UNCOND },
598 {"END_PROGRAM", { 0x19, 0x19, 0x19, 0x19 }, 0 }, /* ??? "reserved" in isa docs */
599 {"WAIT_ACK", { -1, 0x1A, 0x1A, 0x1A }, 0 },
600 {"TEX_ACK", { -1, 0x1B, 0x1B, 0x1B }, CF_CLAUSE | CF_FETCH | CF_ACK | CF_UNCOND },
601 {"VTX_ACK", { -1, 0x1C, 0x1C, -1 }, CF_CLAUSE | CF_FETCH | CF_ACK | CF_UNCOND },
602 {"VTX_TC_ACK", { -1, 0x1D, -1, -1 }, CF_CLAUSE | CF_FETCH | CF_ACK | CF_UNCOND },
603 {"JUMPTABLE", { -1, -1, 0x1D, 0x1D }, CF_BRANCH },
604 {"WAVE_SYNC", { -1, -1, 0x1E, 0x1E }, 0 },
605 {"HALT", { -1, -1, 0x1F, 0x1F }, 0 },
606 {"CF_END", { -1, -1, -1, 0x20 }, 0 },
607 {"LDS_DEALLOC", { -1, -1, -1, 0x21 }, 0 },
608 {"PUSH_WQM", { -1, -1, -1, 0x22 }, CF_BRANCH },
609 {"POP_WQM", { -1, -1, -1, 0x23 }, CF_BRANCH },
610 {"ELSE_WQM", { -1, -1, -1, 0x24 }, CF_BRANCH },
611 {"JUMP_ANY", { -1, -1, -1, 0x25 }, CF_BRANCH },
612
613 /* ??? next 5 added from CAYMAN ISA doc, not in the original table */
614 {"REACTIVATE", { -1, -1, -1, 0x26 }, 0 },
615 {"REACTIVATE_WQM", { -1, -1, -1, 0x27 }, 0 },
616 {"INTERRUPT", { -1, -1, -1, 0x28 }, 0 },
617 {"INTERRUPT_AND_SLEEP", { -1, -1, -1, 0x29 }, 0 },
618 {"SET_PRIORITY", { -1, -1, -1, 0x2A }, 0 },
619
620 {"MEM_STREAM0_BUF0", { -1, -1, 0x40, 0x40 }, CF_MEM | CF_STRM },
621 {"MEM_STREAM0_BUF1", { -1, -1, 0x41, 0x41 }, CF_MEM | CF_STRM },
622 {"MEM_STREAM0_BUF2", { -1, -1, 0x42, 0x42 }, CF_MEM | CF_STRM },
623 {"MEM_STREAM0_BUF3", { -1, -1, 0x43, 0x43 }, CF_MEM | CF_STRM },
624 {"MEM_STREAM1_BUF0", { -1, -1, 0x44, 0x44 }, CF_MEM | CF_STRM },
625 {"MEM_STREAM1_BUF1", { -1, -1, 0x45, 0x45 }, CF_MEM | CF_STRM },
626 {"MEM_STREAM1_BUF2", { -1, -1, 0x46, 0x46 }, CF_MEM | CF_STRM },
627 {"MEM_STREAM1_BUF3", { -1, -1, 0x47, 0x47 }, CF_MEM | CF_STRM },
628 {"MEM_STREAM2_BUF0", { -1, -1, 0x48, 0x48 }, CF_MEM | CF_STRM },
629 {"MEM_STREAM2_BUF1", { -1, -1, 0x49, 0x49 }, CF_MEM | CF_STRM },
630 {"MEM_STREAM2_BUF2", { -1, -1, 0x4A, 0x4A }, CF_MEM | CF_STRM },
631 {"MEM_STREAM2_BUF3", { -1, -1, 0x4B, 0x4B }, CF_MEM | CF_STRM },
632 {"MEM_STREAM3_BUF0", { -1, -1, 0x4C, 0x4C }, CF_MEM | CF_STRM },
633 {"MEM_STREAM3_BUF1", { -1, -1, 0x4D, 0x4D }, CF_MEM | CF_STRM },
634 {"MEM_STREAM3_BUF2", { -1, -1, 0x4E, 0x4E }, CF_MEM | CF_STRM },
635 {"MEM_STREAM3_BUF3", { -1, -1, 0x4F, 0x4F }, CF_MEM | CF_STRM },
636
637 {"MEM_STREAM0", { 0x20, 0x20, -1, -1 }, CF_MEM | CF_STRM },
638 {"MEM_STREAM1", { 0x21, 0x21, -1, -1 }, CF_MEM | CF_STRM },
639 {"MEM_STREAM2", { 0x22, 0x22, -1, -1 }, CF_MEM | CF_STRM },
640 {"MEM_STREAM3", { 0x23, 0x23, -1, -1 }, CF_MEM | CF_STRM },
641
642 {"MEM_SCRATCH", { 0x24, 0x24, 0x50, 0x50 }, CF_MEM },
643 {"MEM_REDUCT", { 0x25, 0x25, -1, -1 }, CF_MEM },
644 {"MEM_RING", { 0x26, 0x26, 0x52, 0x52 }, CF_MEM | CF_EMIT },
645
646 {"EXPORT", { 0x27, 0x27, 0x53, 0x53 }, CF_EXP },
647 {"EXPORT_DONE", { 0x28, 0x28, 0x54, 0x54 }, CF_EXP },
648
649 {"MEM_EXPORT", { -1, 0x3A, 0x55, 0x55 }, CF_MEM },
650 {"MEM_RAT", { -1, -1, 0x56, 0x56 }, CF_MEM | CF_RAT },
651 {"MEM_RAT_NOCACHE", { -1, -1, 0x57, 0x57 }, CF_MEM | CF_RAT },
652 {"MEM_RING1", { -1, -1, 0x58, 0x58 }, CF_MEM | CF_EMIT },
653 {"MEM_RING2", { -1, -1, 0x59, 0x59 }, CF_MEM | CF_EMIT },
654 {"MEM_RING3", { -1, -1, 0x5A, 0x5A }, CF_MEM | CF_EMIT },
655 {"MEM_MEM_COMBINED", { -1, -1, 0x5B, 0x5B }, CF_MEM },
656 {"MEM_RAT_COMBINED_NOCACHE", { -1, -1, 0x5C, 0x5C }, CF_MEM | CF_RAT },
657 {"MEM_RAT_COMBINED", { -1, -1, -1, 0x5D }, CF_MEM | CF_RAT }, /* ??? not in cayman isa doc */
658
659 {"EXPORT_DONE_END", { -1, -1, -1, 0x5E }, CF_EXP }, /* ??? not in cayman isa doc */
660
661 {"ALU", { 0x08, 0x08, 0x08, 0x08 }, CF_CLAUSE | CF_ALU },
662 {"ALU_PUSH_BEFORE", { 0x09, 0x09, 0x09, 0x09 }, CF_CLAUSE | CF_ALU },
663 {"ALU_POP_AFTER", { 0x0A, 0x0A, 0x0A, 0x0A }, CF_CLAUSE | CF_ALU },
664 {"ALU_POP2_AFTER", { 0x0B, 0x0B, 0x0B, 0x0B }, CF_CLAUSE | CF_ALU },
665 {"ALU_EXT", { -1, -1, 0x0C, 0x0C }, CF_CLAUSE | CF_ALU | CF_ALU_EXT },
666 {"ALU_CONTINUE", { 0x0D, 0x0D, 0x0D, -1 }, CF_CLAUSE | CF_ALU },
667 {"ALU_BREAK", { 0x0E, 0x0E, 0x0E, -1 }, CF_CLAUSE | CF_ALU },
668 {"ALU_ELSE_AFTER", { 0x0F, 0x0F, 0x0F, 0x0F }, CF_CLAUSE | CF_ALU },
669 {"CF_NATIVE", { 0x00, 0x00, 0x00, 0x00 }, 0 }
670 };
671
672
673 #define ALU_OP2_ADD 0
674 #define ALU_OP2_MUL 1
675 #define ALU_OP2_MUL_IEEE 2
676 #define ALU_OP2_MAX 3
677 #define ALU_OP2_MIN 4
678 #define ALU_OP2_MAX_DX10 5
679 #define ALU_OP2_MIN_DX10 6
680 #define ALU_OP2_SETE 7
681 #define ALU_OP2_SETGT 8
682 #define ALU_OP2_SETGE 9
683 #define ALU_OP2_SETNE 10
684 #define ALU_OP2_SETE_DX10 11
685 #define ALU_OP2_SETGT_DX10 12
686 #define ALU_OP2_SETGE_DX10 13
687 #define ALU_OP2_SETNE_DX10 14
688 #define ALU_OP1_FRACT 15
689 #define ALU_OP1_TRUNC 16
690 #define ALU_OP1_CEIL 17
691 #define ALU_OP1_RNDNE 18
692 #define ALU_OP1_FLOOR 19
693 #define ALU_OP2_ASHR_INT 20
694 #define ALU_OP2_LSHR_INT 21
695 #define ALU_OP2_LSHL_INT 22
696 #define ALU_OP1_MOV 23
697 #define ALU_OP0_NOP 24
698 #define ALU_OP2_PRED_SETGT_UINT 25
699 #define ALU_OP2_PRED_SETGE_UINT 26
700 #define ALU_OP2_PRED_SETE 27
701 #define ALU_OP2_PRED_SETGT 28
702 #define ALU_OP2_PRED_SETGE 29
703 #define ALU_OP2_PRED_SETNE 30
704 #define ALU_OP1_PRED_SET_INV 31
705 #define ALU_OP2_PRED_SET_POP 32
706 #define ALU_OP0_PRED_SET_CLR 33
707 #define ALU_OP1_PRED_SET_RESTORE 34
708 #define ALU_OP2_PRED_SETE_PUSH 35
709 #define ALU_OP2_PRED_SETGT_PUSH 36
710 #define ALU_OP2_PRED_SETGE_PUSH 37
711 #define ALU_OP2_PRED_SETNE_PUSH 38
712 #define ALU_OP2_KILLE 39
713 #define ALU_OP2_KILLGT 40
714 #define ALU_OP2_KILLGE 41
715 #define ALU_OP2_KILLNE 42
716 #define ALU_OP2_AND_INT 43
717 #define ALU_OP2_OR_INT 44
718 #define ALU_OP2_XOR_INT 45
719 #define ALU_OP1_NOT_INT 46
720 #define ALU_OP2_ADD_INT 47
721 #define ALU_OP2_SUB_INT 48
722 #define ALU_OP2_MAX_INT 49
723 #define ALU_OP2_MIN_INT 50
724 #define ALU_OP2_MAX_UINT 51
725 #define ALU_OP2_MIN_UINT 52
726 #define ALU_OP2_SETE_INT 53
727 #define ALU_OP2_SETGT_INT 54
728 #define ALU_OP2_SETGE_INT 55
729 #define ALU_OP2_SETNE_INT 56
730 #define ALU_OP2_SETGT_UINT 57
731 #define ALU_OP2_SETGE_UINT 58
732 #define ALU_OP2_KILLGT_UINT 59
733 #define ALU_OP2_KILLGE_UINT 60
734 #define ALU_OP2_PRED_SETE_INT 61
735 #define ALU_OP2_PRED_SETGT_INT 62
736 #define ALU_OP2_PRED_SETGE_INT 63
737 #define ALU_OP2_PRED_SETNE_INT 64
738 #define ALU_OP2_KILLE_INT 65
739 #define ALU_OP2_KILLGT_INT 66
740 #define ALU_OP2_KILLGE_INT 67
741 #define ALU_OP2_KILLNE_INT 68
742 #define ALU_OP2_PRED_SETE_PUSH_INT 69
743 #define ALU_OP2_PRED_SETGT_PUSH_INT 70
744 #define ALU_OP2_PRED_SETGE_PUSH_INT 71
745 #define ALU_OP2_PRED_SETNE_PUSH_INT 72
746 #define ALU_OP2_PRED_SETLT_PUSH_INT 73
747 #define ALU_OP2_PRED_SETLE_PUSH_INT 74
748 #define ALU_OP1_FLT_TO_INT 75
749 #define ALU_OP1_BFREV_INT 76
750 #define ALU_OP2_ADDC_UINT 77
751 #define ALU_OP2_SUBB_UINT 78
752 #define ALU_OP0_GROUP_BARRIER 79
753 #define ALU_OP0_GROUP_SEQ_BEGIN 80
754 #define ALU_OP0_GROUP_SEQ_END 81
755 #define ALU_OP2_SET_MODE 82
756 #define ALU_OP0_SET_CF_IDX0 83
757 #define ALU_OP0_SET_CF_IDX1 84
758 #define ALU_OP2_SET_LDS_SIZE 85
759 #define ALU_OP2_MUL_INT24 86
760 #define ALU_OP2_MULHI_INT24 87
761 #define ALU_OP1_FLT_TO_INT_TRUNC 88
762 #define ALU_OP1_EXP_IEEE 89
763 #define ALU_OP1_LOG_CLAMPED 90
764 #define ALU_OP1_LOG_IEEE 91
765 #define ALU_OP1_RECIP_CLAMPED 92
766 #define ALU_OP1_RECIP_FF 93
767 #define ALU_OP1_RECIP_IEEE 94
768 #define ALU_OP1_RECIPSQRT_CLAMPED 95
769 #define ALU_OP1_RECIPSQRT_FF 96
770 #define ALU_OP1_RECIPSQRT_IEEE 97
771 #define ALU_OP1_SQRT_IEEE 98
772 #define ALU_OP1_SIN 99
773 #define ALU_OP1_COS 100
774 #define ALU_OP2_MULLO_INT 101
775 #define ALU_OP2_MULHI_INT 102
776 #define ALU_OP2_MULLO_UINT 103
777 #define ALU_OP2_MULHI_UINT 104
778 #define ALU_OP1_RECIP_INT 105
779 #define ALU_OP1_RECIP_UINT 106
780 #define ALU_OP2_RECIP_64 107
781 #define ALU_OP2_RECIP_CLAMPED_64 108
782 #define ALU_OP2_RECIPSQRT_64 109
783 #define ALU_OP2_RECIPSQRT_CLAMPED_64 110
784 #define ALU_OP2_SQRT_64 111
785 #define ALU_OP1_FLT_TO_UINT 112
786 #define ALU_OP1_INT_TO_FLT 113
787 #define ALU_OP1_UINT_TO_FLT 114
788 #define ALU_OP2_BFM_INT 115
789 #define ALU_OP1_FLT32_TO_FLT16 116
790 #define ALU_OP1_FLT16_TO_FLT32 117
791 #define ALU_OP1_UBYTE0_FLT 118
792 #define ALU_OP1_UBYTE1_FLT 119
793 #define ALU_OP1_UBYTE2_FLT 120
794 #define ALU_OP1_UBYTE3_FLT 121
795 #define ALU_OP1_BCNT_INT 122
796 #define ALU_OP1_FFBH_UINT 123
797 #define ALU_OP1_FFBL_INT 124
798 #define ALU_OP1_FFBH_INT 125
799 #define ALU_OP1_FLT_TO_UINT4 126
800 #define ALU_OP2_DOT_IEEE 127
801 #define ALU_OP1_FLT_TO_INT_RPI 128
802 #define ALU_OP1_FLT_TO_INT_FLOOR 129
803 #define ALU_OP2_MULHI_UINT24 130
804 #define ALU_OP1_MBCNT_32HI_INT 131
805 #define ALU_OP1_OFFSET_TO_FLT 132
806 #define ALU_OP2_MUL_UINT24 133
807 #define ALU_OP1_BCNT_ACCUM_PREV_INT 134
808 #define ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT 135
809 #define ALU_OP2_SETE_64 136
810 #define ALU_OP2_SETNE_64 137
811 #define ALU_OP2_SETGT_64 138
812 #define ALU_OP2_SETGE_64 139
813 #define ALU_OP2_MIN_64 140
814 #define ALU_OP2_MAX_64 141
815 #define ALU_OP2_DOT4 142
816 #define ALU_OP2_DOT4_IEEE 143
817 #define ALU_OP2_CUBE 144
818 #define ALU_OP1_MAX4 145
819 #define ALU_OP1_FREXP_64 146
820 #define ALU_OP2_LDEXP_64 147
821 #define ALU_OP1_FRACT_64 148
822 #define ALU_OP2_PRED_SETGT_64 149
823 #define ALU_OP2_PRED_SETE_64 150
824 #define ALU_OP2_PRED_SETGE_64 151
825 #define ALU_OP2_MUL_64 152
826 #define ALU_OP2_ADD_64 153
827 #define ALU_OP1_MOVA_INT 154
828 #define ALU_OP1_FLT64_TO_FLT32 155
829 #define ALU_OP1_FLT32_TO_FLT64 156
830 #define ALU_OP2_SAD_ACCUM_PREV_UINT 157
831 #define ALU_OP2_DOT 158
832 #define ALU_OP1_MUL_PREV 159
833 #define ALU_OP1_MUL_IEEE_PREV 160
834 #define ALU_OP1_ADD_PREV 161
835 #define ALU_OP2_MULADD_PREV 162
836 #define ALU_OP2_MULADD_IEEE_PREV 163
837 #define ALU_OP2_INTERP_XY 164
838 #define ALU_OP2_INTERP_ZW 165
839 #define ALU_OP2_INTERP_X 166
840 #define ALU_OP2_INTERP_Z 167
841 #define ALU_OP1_STORE_FLAGS 168
842 #define ALU_OP1_LOAD_STORE_FLAGS 169
843 #define ALU_OP2_LDS_1A 170
844 #define ALU_OP2_LDS_1A1D 171
845 #define ALU_OP2_LDS_2A 172
846 #define ALU_OP1_INTERP_LOAD_P0 173
847 #define ALU_OP1_INTERP_LOAD_P10 174
848 #define ALU_OP1_INTERP_LOAD_P20 175
849 #define ALU_OP3_BFE_UINT 176
850 #define ALU_OP3_BFE_INT 177
851 #define ALU_OP3_BFI_INT 178
852 #define ALU_OP3_FMA 179
853 #define ALU_OP3_MULADD_INT24 180
854 #define ALU_OP3_CNDNE_64 181
855 #define ALU_OP3_FMA_64 182
856 #define ALU_OP3_LERP_UINT 183
857 #define ALU_OP3_BIT_ALIGN_INT 184
858 #define ALU_OP3_BYTE_ALIGN_INT 185
859 #define ALU_OP3_SAD_ACCUM_UINT 186
860 #define ALU_OP3_SAD_ACCUM_HI_UINT 187
861 #define ALU_OP3_MULADD_UINT24 188
862 #define ALU_OP3_LDS_IDX_OP 189
863 #define ALU_OP3_MULADD 190
864 #define ALU_OP3_MULADD_M2 191
865 #define ALU_OP3_MULADD_M4 192
866 #define ALU_OP3_MULADD_D2 193
867 #define ALU_OP3_MULADD_IEEE 194
868 #define ALU_OP3_CNDE 195
869 #define ALU_OP3_CNDGT 196
870 #define ALU_OP3_CNDGE 197
871 #define ALU_OP3_CNDE_INT 198
872 #define ALU_OP3_CNDGT_INT 199
873 #define ALU_OP3_CNDGE_INT 200
874 #define ALU_OP3_MUL_LIT 201
875 #define ALU_OP1_MOVA 202
876 #define ALU_OP1_MOVA_FLOOR 203
877 #define ALU_OP1_MOVA_GPR_INT 204
878 #define ALU_OP3_MULADD_64 205
879 #define ALU_OP3_MULADD_64_M2 206
880 #define ALU_OP3_MULADD_64_M4 207
881 #define ALU_OP3_MULADD_64_D2 208
882 #define ALU_OP3_MUL_LIT_M2 209
883 #define ALU_OP3_MUL_LIT_M4 210
884 #define ALU_OP3_MUL_LIT_D2 211
885 #define ALU_OP3_MULADD_IEEE_M2 212
886 #define ALU_OP3_MULADD_IEEE_M4 213
887 #define ALU_OP3_MULADD_IEEE_D2 214
888
889 #define LDS_OP2_LDS_ADD 215
890 #define LDS_OP2_LDS_SUB 216
891 #define LDS_OP2_LDS_RSUB 217
892 #define LDS_OP2_LDS_INC 218
893 #define LDS_OP2_LDS_DEC 219
894 #define LDS_OP2_LDS_MIN_INT 220
895 #define LDS_OP2_LDS_MAX_INT 221
896 #define LDS_OP2_LDS_MIN_UINT 222
897 #define LDS_OP2_LDS_MAX_UINT 223
898 #define LDS_OP2_LDS_AND 224
899 #define LDS_OP2_LDS_OR 225
900 #define LDS_OP2_LDS_XOR 226
901 #define LDS_OP3_LDS_MSKOR 227
902 #define LDS_OP2_LDS_WRITE 228
903 #define LDS_OP3_LDS_WRITE_REL 229
904 #define LDS_OP3_LDS_WRITE2 230
905 #define LDS_OP3_LDS_CMP_STORE 231
906 #define LDS_OP3_LDS_CMP_STORE_SPF 232
907 #define LDS_OP2_LDS_BYTE_WRITE 233
908 #define LDS_OP2_LDS_SHORT_WRITE 234
909 #define LDS_OP2_LDS_ADD_RET 235
910 #define LDS_OP2_LDS_SUB_RET 236
911 #define LDS_OP2_LDS_RSUB_RET 237
912 #define LDS_OP2_LDS_INC_RET 238
913 #define LDS_OP2_LDS_DEC_RET 239
914 #define LDS_OP2_LDS_MIN_INT_RET 240
915 #define LDS_OP2_LDS_MAX_INT_RET 241
916 #define LDS_OP2_LDS_MIN_UINT_RET 242
917 #define LDS_OP2_LDS_MAX_UINT_RET 243
918 #define LDS_OP2_LDS_AND_RET 244
919 #define LDS_OP2_LDS_OR_RET 245
920 #define LDS_OP2_LDS_XOR_RET 246
921 #define LDS_OP3_LDS_MSKOR_RET 247
922 #define LDS_OP2_LDS_XCHG_RET 248
923 #define LDS_OP3_LDS_XCHG_REL_RET 249
924 #define LDS_OP3_LDS_XCHG2_RET 250
925 #define LDS_OP3_LDS_CMP_XCHG_RET 251
926 #define LDS_OP3_LDS_CMP_XCHG_SPF_RET 252
927 #define LDS_OP1_LDS_READ_RET 253
928 #define LDS_OP1_LDS_READ_REL_RET 254
929 #define LDS_OP2_LDS_READ2_RET 255
930 #define LDS_OP3_LDS_READWRITE_RET 256
931 #define LDS_OP1_LDS_BYTE_READ_RET 257
932 #define LDS_OP1_LDS_UBYTE_READ_RET 258
933 #define LDS_OP1_LDS_SHORT_READ_RET 259
934 #define LDS_OP1_LDS_USHORT_READ_RET 260
935
936 #define FETCH_OP_VFETCH 0
937 #define FETCH_OP_SEMFETCH 1
938 #define FETCH_OP_READ_SCRATCH 2
939 #define FETCH_OP_READ_REDUCT 3
940 #define FETCH_OP_READ_MEM 4
941 #define FETCH_OP_DS_LOCAL_WRITE 5
942 #define FETCH_OP_DS_LOCAL_READ 6
943 #define FETCH_OP_GDS_ADD 7
944 #define FETCH_OP_GDS_SUB 8
945 #define FETCH_OP_GDS_RSUB 9
946 #define FETCH_OP_GDS_INC 10
947 #define FETCH_OP_GDS_DEC 11
948 #define FETCH_OP_GDS_MIN_INT 12
949 #define FETCH_OP_GDS_MAX_INT 13
950 #define FETCH_OP_GDS_MIN_UINT 14
951 #define FETCH_OP_GDS_MAX_UINT 15
952 #define FETCH_OP_GDS_AND 16
953 #define FETCH_OP_GDS_OR 17
954 #define FETCH_OP_GDS_XOR 18
955 #define FETCH_OP_GDS_MSKOR 19
956 #define FETCH_OP_GDS_WRITE 20
957 #define FETCH_OP_GDS_WRITE_REL 21
958 #define FETCH_OP_GDS_WRITE2 22
959 #define FETCH_OP_GDS_CMP_STORE 23
960 #define FETCH_OP_GDS_CMP_STORE_SPF 24
961 #define FETCH_OP_GDS_BYTE_WRITE 25
962 #define FETCH_OP_GDS_SHORT_WRITE 26
963 #define FETCH_OP_GDS_ADD_RET 27
964 #define FETCH_OP_GDS_SUB_RET 28
965 #define FETCH_OP_GDS_RSUB_RET 29
966 #define FETCH_OP_GDS_INC_RET 30
967 #define FETCH_OP_GDS_DEC_RET 31
968 #define FETCH_OP_GDS_MIN_INT_RET 32
969 #define FETCH_OP_GDS_MAX_INT_RET 33
970 #define FETCH_OP_GDS_MIN_UINT_RET 34
971 #define FETCH_OP_GDS_MAX_UINT_RET 35
972 #define FETCH_OP_GDS_AND_RET 36
973 #define FETCH_OP_GDS_OR_RET 37
974 #define FETCH_OP_GDS_XOR_RET 38
975 #define FETCH_OP_GDS_MSKOR_RET 39
976 #define FETCH_OP_GDS_XCHG_RET 40
977 #define FETCH_OP_GDS_XCHG_REL_RET 41
978 #define FETCH_OP_GDS_XCHG2_RET 42
979 #define FETCH_OP_GDS_CMP_XCHG_RET 43
980 #define FETCH_OP_GDS_CMP_XCHG_SPF_RET 44
981 #define FETCH_OP_GDS_READ_RET 45
982 #define FETCH_OP_GDS_READ_REL_RET 46
983 #define FETCH_OP_GDS_READ2_RET 47
984 #define FETCH_OP_GDS_READWRITE_RET 48
985 #define FETCH_OP_GDS_BYTE_READ_RET 49
986 #define FETCH_OP_GDS_UBYTE_READ_RET 50
987 #define FETCH_OP_GDS_SHORT_READ_RET 51
988 #define FETCH_OP_GDS_USHORT_READ_RET 52
989 #define FETCH_OP_GDS_ATOMIC_ORDERED_ALLOC 53
990 #define FETCH_OP_TF_WRITE 54
991 #define FETCH_OP_DS_GLOBAL_WRITE 55
992 #define FETCH_OP_DS_GLOBAL_READ 56
993 #define FETCH_OP_LD 57
994 #define FETCH_OP_LDFPTR 58
995 #define FETCH_OP_GET_TEXTURE_RESINFO 59
996 #define FETCH_OP_GET_NUMBER_OF_SAMPLES 60
997 #define FETCH_OP_GET_LOD 61
998 #define FETCH_OP_GET_GRADIENTS_H 62
999 #define FETCH_OP_GET_GRADIENTS_V 63
1000 #define FETCH_OP_GET_GRADIENTS_H_FINE 64
1001 #define FETCH_OP_GET_GRADIENTS_V_FINE 65
1002 #define FETCH_OP_GET_LERP 66
1003 #define FETCH_OP_SET_TEXTURE_OFFSETS 67
1004 #define FETCH_OP_KEEP_GRADIENTS 68
1005 #define FETCH_OP_SET_GRADIENTS_H 69
1006 #define FETCH_OP_SET_GRADIENTS_V 70
1007 #define FETCH_OP_SET_GRADIENTS_H_COARSE 71
1008 #define FETCH_OP_SET_GRADIENTS_V_COARSE 72
1009 #define FETCH_OP_SET_GRADIENTS_H_PACKED_FINE 73
1010 #define FETCH_OP_SET_GRADIENTS_V_PACKED_FINE 74
1011 #define FETCH_OP_SET_GRADIENTS_H_PACKED_COARSE 75
1012 #define FETCH_OP_SET_GRADIENTS_V_PACKED_COARSE 76
1013 #define FETCH_OP_PASS 77
1014 #define FETCH_OP_PASS1 78
1015 #define FETCH_OP_PASS2 79
1016 #define FETCH_OP_PASS3 80
1017 #define FETCH_OP_SET_CUBEMAP_INDEX 81
1018 #define FETCH_OP_GET_BUFFER_RESINFO 82
1019 #define FETCH_OP_FETCH4 83
1020 #define FETCH_OP_SAMPLE 84
1021 #define FETCH_OP_SAMPLE_L 85
1022 #define FETCH_OP_SAMPLE_LB 86
1023 #define FETCH_OP_SAMPLE_LZ 87
1024 #define FETCH_OP_SAMPLE_G 88
1025 #define FETCH_OP_SAMPLE_G_L 89
1026 #define FETCH_OP_GATHER4 90
1027 #define FETCH_OP_SAMPLE_G_LB 91
1028 #define FETCH_OP_SAMPLE_G_LZ 92
1029 #define FETCH_OP_GATHER4_O 93
1030 #define FETCH_OP_SAMPLE_C 94
1031 #define FETCH_OP_SAMPLE_C_L 95
1032 #define FETCH_OP_SAMPLE_C_LB 96
1033 #define FETCH_OP_SAMPLE_C_LZ 97
1034 #define FETCH_OP_SAMPLE_C_G 98
1035 #define FETCH_OP_SAMPLE_C_G_L 99
1036 #define FETCH_OP_GATHER4_C 100
1037 #define FETCH_OP_SAMPLE_C_G_LB 101
1038 #define FETCH_OP_SAMPLE_C_G_LZ 102
1039 #define FETCH_OP_GATHER4_C_O 103
1040
1041 #define CF_OP_NOP 0
1042 #define CF_OP_TEX 1
1043 #define CF_OP_VTX 2
1044 #define CF_OP_VTX_TC 3
1045 #define CF_OP_GDS 4
1046 #define CF_OP_LOOP_START 5
1047 #define CF_OP_LOOP_END 6
1048 #define CF_OP_LOOP_START_DX10 7
1049 #define CF_OP_LOOP_START_NO_AL 8
1050 #define CF_OP_LOOP_CONTINUE 9
1051 #define CF_OP_LOOP_BREAK 10
1052 #define CF_OP_JUMP 11
1053 #define CF_OP_PUSH 12
1054 #define CF_OP_PUSH_ELSE 13
1055 #define CF_OP_ELSE 14
1056 #define CF_OP_POP 15
1057 #define CF_OP_POP_JUMP 16
1058 #define CF_OP_POP_PUSH 17
1059 #define CF_OP_POP_PUSH_ELSE 18
1060 #define CF_OP_CALL 19
1061 #define CF_OP_CALL_FS 20
1062 #define CF_OP_RET 21
1063 #define CF_OP_EMIT_VERTEX 22
1064 #define CF_OP_EMIT_CUT_VERTEX 23
1065 #define CF_OP_CUT_VERTEX 24
1066 #define CF_OP_KILL 25
1067 #define CF_OP_END_PROGRAM 26
1068 #define CF_OP_WAIT_ACK 27
1069 #define CF_OP_TEX_ACK 28
1070 #define CF_OP_VTX_ACK 29
1071 #define CF_OP_VTX_TC_ACK 30
1072 #define CF_OP_JUMPTABLE 31
1073 #define CF_OP_WAVE_SYNC 32
1074 #define CF_OP_HALT 33
1075 #define CF_OP_CF_END 34
1076 #define CF_OP_LDS_DEALLOC 35
1077 #define CF_OP_PUSH_WQM 36
1078 #define CF_OP_POP_WQM 37
1079 #define CF_OP_ELSE_WQM 38
1080 #define CF_OP_JUMP_ANY 39
1081 #define CF_OP_REACTIVATE 40
1082 #define CF_OP_REACTIVATE_WQM 41
1083 #define CF_OP_INTERRUPT 42
1084 #define CF_OP_INTERRUPT_AND_SLEEP 43
1085 #define CF_OP_SET_PRIORITY 44
1086 #define CF_OP_MEM_STREAM0_BUF0 45
1087 #define CF_OP_MEM_STREAM0_BUF1 46
1088 #define CF_OP_MEM_STREAM0_BUF2 47
1089 #define CF_OP_MEM_STREAM0_BUF3 48
1090 #define CF_OP_MEM_STREAM1_BUF0 49
1091 #define CF_OP_MEM_STREAM1_BUF1 50
1092 #define CF_OP_MEM_STREAM1_BUF2 51
1093 #define CF_OP_MEM_STREAM1_BUF3 52
1094 #define CF_OP_MEM_STREAM2_BUF0 53
1095 #define CF_OP_MEM_STREAM2_BUF1 54
1096 #define CF_OP_MEM_STREAM2_BUF2 55
1097 #define CF_OP_MEM_STREAM2_BUF3 56
1098 #define CF_OP_MEM_STREAM3_BUF0 57
1099 #define CF_OP_MEM_STREAM3_BUF1 58
1100 #define CF_OP_MEM_STREAM3_BUF2 59
1101 #define CF_OP_MEM_STREAM3_BUF3 60
1102 #define CF_OP_MEM_STREAM0 61
1103 #define CF_OP_MEM_STREAM1 62
1104 #define CF_OP_MEM_STREAM2 63
1105 #define CF_OP_MEM_STREAM3 64
1106 #define CF_OP_MEM_SCRATCH 65
1107 #define CF_OP_MEM_REDUCT 66
1108 #define CF_OP_MEM_RING 67
1109 #define CF_OP_EXPORT 68
1110 #define CF_OP_EXPORT_DONE 69
1111 #define CF_OP_MEM_EXPORT 70
1112 #define CF_OP_MEM_RAT 71
1113 #define CF_OP_MEM_RAT_NOCACHE 72
1114 #define CF_OP_MEM_RING1 73
1115 #define CF_OP_MEM_RING2 74
1116 #define CF_OP_MEM_RING3 75
1117 #define CF_OP_MEM_MEM_COMBINED 76
1118 #define CF_OP_MEM_RAT_COMBINED_NOCACHE 77
1119 #define CF_OP_MEM_RAT_COMBINED 78
1120 #define CF_OP_EXPORT_DONE_END 79
1121 #define CF_OP_ALU 80
1122 #define CF_OP_ALU_PUSH_BEFORE 81
1123 #define CF_OP_ALU_POP_AFTER 82
1124 #define CF_OP_ALU_POP2_AFTER 83
1125 #define CF_OP_ALU_EXT 84
1126 #define CF_OP_ALU_CONTINUE 85
1127 #define CF_OP_ALU_BREAK 86
1128 #define CF_OP_ALU_ELSE_AFTER 87
1129
1130 /* CF_NATIVE means that r600_bytecode_cf contains pre-encoded native data */
1131 #define CF_NATIVE 88
1132
1133 enum r600_chip_class {
1134 ISA_CC_R600,
1135 ISA_CC_R700,
1136 ISA_CC_EVERGREEN,
1137 ISA_CC_CAYMAN
1138 };
1139
1140 struct r600_isa {
1141 enum r600_chip_class hw_class;
1142
1143 /* these arrays provide reverse mapping - opcode => table_index,
1144 * typically we don't need such lookup, unless we are decoding the native
1145 * bytecode (e.g. when reading the bytestream from llvm backend) */
1146 unsigned *alu_op2_map;
1147 unsigned *alu_op3_map;
1148 unsigned *fetch_map;
1149 unsigned *cf_map;
1150 };
1151
1152 struct r600_context;
1153
1154 int r600_isa_init(struct r600_context *ctx, struct r600_isa *isa);
1155 int r600_isa_destroy(struct r600_isa *isa);
1156
1157 #define TABLE_SIZE(t) (sizeof(t)/sizeof(t[0]))
1158
1159 static inline const struct alu_op_info *
1160 r600_isa_alu(unsigned op) {
1161 assert (op < TABLE_SIZE(alu_op_table));
1162 return &alu_op_table[op];
1163 }
1164
1165 static inline const struct fetch_op_info *
1166 r600_isa_fetch(unsigned op) {
1167 assert (op < TABLE_SIZE(fetch_op_table));
1168 return &fetch_op_table[op];
1169 }
1170
1171 static inline const struct cf_op_info *
1172 r600_isa_cf(unsigned op) {
1173 assert (op < TABLE_SIZE(cf_op_table));
1174 return &cf_op_table[op];
1175 }
1176
1177 static inline unsigned
1178 r600_isa_alu_opcode(enum r600_chip_class chip_class, unsigned op) {
1179 int opc = r600_isa_alu(op)->opcode[chip_class >> 1];
1180 assert(opc != -1);
1181 return opc;
1182 }
1183
1184 static inline unsigned
1185 r600_isa_alu_slots(enum r600_chip_class chip_class, unsigned op) {
1186 unsigned slots = r600_isa_alu(op)->slots[chip_class];
1187 assert(slots != 0);
1188 return slots;
1189 }
1190
1191 static inline unsigned
1192 r600_isa_fetch_opcode(enum r600_chip_class chip_class, unsigned op) {
1193 int opc = r600_isa_fetch(op)->opcode[chip_class];
1194 assert(opc != -1);
1195 return opc;
1196 }
1197
1198 static inline unsigned
1199 r600_isa_cf_opcode(enum r600_chip_class chip_class, unsigned op) {
1200 int opc = r600_isa_cf(op)->opcode[chip_class];
1201 assert(opc != -1);
1202 return opc;
1203 }
1204
1205 static inline unsigned
1206 r600_isa_alu_by_opcode(struct r600_isa* isa, unsigned opcode, unsigned is_op3) {
1207 unsigned op;
1208 if (is_op3) {
1209 assert(isa->alu_op3_map);
1210 op = isa->alu_op3_map[opcode];
1211 } else {
1212 assert(isa->alu_op2_map);
1213 op = isa->alu_op2_map[opcode];
1214 }
1215 assert(op);
1216 return op - 1;
1217 }
1218
1219 static inline unsigned
1220 r600_isa_fetch_by_opcode(struct r600_isa* isa, unsigned opcode) {
1221 unsigned op;
1222 assert(isa->fetch_map);
1223 op = isa->fetch_map[opcode];
1224 assert(op);
1225 return op - 1;
1226 }
1227
1228 static inline unsigned
1229 r600_isa_cf_by_opcode(struct r600_isa* isa, unsigned opcode, unsigned is_alu) {
1230 unsigned op;
1231 assert(isa->cf_map);
1232 /* using offset for CF_ALU_xxx opcodes because they overlap with other
1233 * CF opcodes (they use different encoding in hw) */
1234 op = isa->cf_map[is_alu ? opcode + 0x80 : opcode];
1235 assert(op);
1236 return op - 1;
1237 }
1238
1239 #endif /* R600_ISA_H_ */