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r600g: add new flags to isa instruction tables
[mesa.git] / src / gallium / drivers / r600 / r600_isa.h
1 /*
2 * Copyright 2012 Vadim Girlin <vadimgirlin@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Vadim Girlin
25 */
26
27 #ifndef R600_ISA_H_
28 #define R600_ISA_H_
29
30 #include "util/u_debug.h"
31
32 /* ALU flags */
33 enum alu_op_flags
34 {
35 AF_V = (1<<0), /* allowed in vector slots */
36
37 /* allowed in scalar(trans) slot (slots xyz on cayman, may be replicated
38 * to w) */
39 AF_S = (1<<1),
40
41 AF_4SLOT = (1<<2), /* uses four vector slots (e.g. DOT4) */
42 AF_4V = (AF_V | AF_4SLOT),
43 AF_VS = (AF_V | AF_S), /* allowed in any slot */
44
45 AF_KILL = (1<<4),
46 AF_PRED = (1<<5),
47 AF_SET = (1<<6),
48
49 /* e.g. MUL_PREV instructions, allowed in x/y, depends on z/w */
50 AF_PREV_INTERLEAVE = (1<<7),
51
52 AF_MOVA = (1<<8), /* all MOVA instructions */
53 AF_IEEE = (1<<10),
54
55 AF_DST_TYPE_MASK = (3<<11),
56 AF_FLOAT_DST = 0,
57 AF_INT_DST = (1<<11),
58 AF_UINT_DST = (3<<11),
59
60 /* DP instructions, 2-slot pairs */
61 AF_64 = (1<<13),
62 /* 24 bit instructions */
63 AF_24 = (1<<14),
64 /* DX10 variants */
65 AF_DX10 = (1<<15),
66
67 /* result is replicated to all channels (only if AF_4V is also set -
68 * for special handling of MULLO_INT on CM) */
69 AF_REPL = (1<<16),
70
71 /* interpolation instructions */
72 AF_INTERP = (1<<17),
73
74 /* LDS instructions */
75 AF_LDS = (1<<20),
76
77 /* e.g. DOT - depends on the next slot in the same group (x<=y/y<=z/z<=w) */
78 AF_PREV_NEXT = (1<<21),
79
80 /* int<->flt conversions */
81 AF_CVT = (1<<22),
82
83 /* commutative operation on src0 and src1 ( a op b = b op a),
84 * includes MULADDs (considering the MUL part on src0 and src1 only) */
85 AF_M_COMM = (1 << 23),
86
87 /* associative operation ((a op b) op c) == (a op (b op c)) */
88 AF_M_ASSOC = (1 << 24),
89
90 AF_PRED_PUSH = (1 << 25),
91
92 AF_ANY_PRED = (AF_PRED | AF_PRED_PUSH),
93
94 AF_CMOV = (1 << 26),
95
96 // for SETcc, PREDSETcc, ... - type of comparison
97 AF_CMP_TYPE_MASK = (3 << 27),
98 AF_FLOAT_CMP = 0,
99 AF_INT_CMP = (1 << 27),
100 AF_UINT_CMP = (3 << 27),
101
102 /* condition codes - 3 bits */
103 AF_CC_SHIFT = 29,
104 AF_CC_MASK = (7 << AF_CC_SHIFT),
105 AF_CC_E = (0 << AF_CC_SHIFT),
106 AF_CC_GT = (1 << AF_CC_SHIFT),
107 AF_CC_GE = (2 << AF_CC_SHIFT),
108 AF_CC_NE = (3 << AF_CC_SHIFT),
109 AF_CC_LT = (4 << AF_CC_SHIFT),
110 AF_CC_LE = (5 << AF_CC_SHIFT),
111 };
112
113 /* flags for FETCH instructions (TEX/VTX) */
114 enum fetch_op_flags
115 {
116 FF_GDS = (1<<0),
117 FF_TEX = (1<<1),
118
119 FF_SETGRAD = (1<<2),
120 FF_GETGRAD = (1<<3),
121 FF_USEGRAD = (1<<4),
122
123 FF_VTX = (1<<5),
124 FF_MEM = (1<<6),
125 };
126
127 /* flags for CF instructions */
128 enum cf_op_flags
129 {
130 CF_CLAUSE = (1<<0), /* execute clause (alu/fetch ...) */
131 CF_ACK = (1<<1), /* acked versions of some instructions */
132 CF_ALU = (1<<2), /* alu clause execution */
133 CF_ALU_EXT = (1<<3), /* ALU_EXTENDED */
134 CF_EXP = (1<<4), /* export (CF_ALLOC_EXPORT_WORD1_SWIZ) */
135 CF_BRANCH = (1<<5), /* branch instructions */
136 CF_LOOP = (1<<6), /* loop instructions */
137 CF_CALL = (1<<7), /* call instructions */
138 CF_MEM = (1<<8), /* export_mem (CF_ALLOC_EXPORT_WORD1_BUF) */
139 CF_FETCH = (1<<9), /* fetch clause */
140
141 CF_UNCOND = (1<<10), /* COND = ACTIVE required */
142 CF_EMIT = (1<<11),
143 CF_STRM = (1<<12), /* MEM_STREAM* */
144
145 CF_RAT = (1<<13), /* MEM_RAT* */
146
147 CF_LOOP_START = (1<<14)
148 };
149
150 /* ALU instruction info */
151 struct alu_op_info
152 {
153 /* instruction name */
154 const char *name;
155 /* number of source operands */
156 int src_count;
157 /* opcodes, [0] - for r6xx/r7xx, [1] - for evergreen/cayman
158 * (-1) if instruction doesn't exist (more precise info in "slots") */
159 int opcode[2];
160 /* slots for r6xx, r7xx, evergreen, cayman
161 * (0 if instruction doesn't exist for chip class) */
162 int slots[4];
163 /* flags (mostly autogenerated from instruction name) */
164 int flags;
165 };
166
167 /* FETCH instruction info */
168 struct fetch_op_info
169 {
170 const char * name;
171 /* for every chip class */
172 int opcode[4];
173 int flags;
174 };
175
176 /* CF instruction info */
177 struct cf_op_info
178 {
179 const char * name;
180 /* for every chip class */
181 int opcode[4];
182 int flags;
183 };
184
185 static const struct alu_op_info alu_op_table[] = {
186 {"ADD", 2, { 0x00, 0x00 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC },
187 {"MUL", 2, { 0x01, 0x01 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC },
188 {"MUL_IEEE", 2, { 0x02, 0x02 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_IEEE },
189 {"MAX", 2, { 0x03, 0x03 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC },
190 {"MIN", 2, { 0x04, 0x04 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC },
191 {"MAX_DX10", 2, { 0x05, 0x05 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_DX10 },
192 {"MIN_DX10", 2, { 0x06, 0x06 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_DX10 },
193 {"SETE", 2, { 0x08, 0x08 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_E },
194 {"SETGT", 2, { 0x09, 0x09 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_GT },
195 {"SETGE", 2, { 0x0A, 0x0A },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_GE },
196 {"SETNE", 2, { 0x0B, 0x0B },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_NE },
197 {"SETE_DX10", 2, { 0x0C, 0x0C },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_E | AF_DX10 | AF_INT_DST },
198 {"SETGT_DX10", 2, { 0x0D, 0x0D },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_GT | AF_DX10 | AF_INT_DST },
199 {"SETGE_DX10", 2, { 0x0E, 0x0E },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_GE | AF_DX10 | AF_INT_DST },
200 {"SETNE_DX10", 2, { 0x0F, 0x0F },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_NE | AF_DX10 | AF_INT_DST },
201 {"FRACT", 1, { 0x10, 0x10 },{ AF_VS, AF_VS, AF_VS, AF_VS}, 0 },
202 {"TRUNC", 1, { 0x11, 0x11 },{ AF_VS, AF_VS, AF_VS, AF_VS}, 0 },
203 {"CEIL", 1, { 0x12, 0x12 },{ AF_VS, AF_VS, AF_VS, AF_VS}, 0 },
204 {"RNDNE", 1, { 0x13, 0x13 },{ AF_VS, AF_VS, AF_VS, AF_VS}, 0 },
205 {"FLOOR", 1, { 0x14, 0x14 },{ AF_VS, AF_VS, AF_VS, AF_VS}, 0 },
206 {"ASHR_INT", 2, { 0x70, 0x15 },{ AF_S, AF_VS, AF_VS, AF_VS}, AF_INT_DST },
207 {"LSHR_INT", 2, { 0x71, 0x16 },{ AF_S, AF_VS, AF_VS, AF_VS}, AF_INT_DST },
208 {"LSHL_INT", 2, { 0x72, 0x17 },{ AF_S, AF_VS, AF_VS, AF_VS}, AF_INT_DST },
209 {"MOV", 1, { 0x19, 0x19 },{ AF_VS, AF_VS, AF_VS, AF_VS}, 0 },
210 {"ALU_NOP", 0, { 0x1A, 0x1A },{ AF_VS, AF_VS, AF_VS, AF_VS}, 0 },
211 {"PRED_SETGT_UINT", 2, { 0x1E, 0x1E },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_GT | AF_UINT_CMP },
212 {"PRED_SETGE_UINT", 2, { 0x1F, 0x1F },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_GE | AF_UINT_CMP },
213 {"PRED_SETE", 2, { 0x20, 0x20 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_E },
214 {"PRED_SETGT", 2, { 0x21, 0x21 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_GT },
215 {"PRED_SETGE", 2, { 0x22, 0x22 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_GE },
216 {"PRED_SETNE", 2, { 0x23, 0x23 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_NE },
217 {"PRED_SET_INV", 1, { 0x24, 0x24 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED },
218 {"PRED_SET_POP", 2, { 0x25, 0x25 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED },
219 {"PRED_SET_CLR", 0, { 0x26, 0x26 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED },
220 {"PRED_SET_RESTORE", 1, { 0x27, 0x27 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED },
221 {"PRED_SETE_PUSH", 2, { 0x28, 0x28 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_E },
222 {"PRED_SETGT_PUSH", 2, { 0x29, 0x29 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_GT },
223 {"PRED_SETGE_PUSH", 2, { 0x2A, 0x2A },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_GE },
224 {"PRED_SETNE_PUSH", 2, { 0x2B, 0x2B },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_NE },
225 {"KILLE", 2, { 0x2C, 0x2C },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_E },
226 {"KILLGT", 2, { 0x2D, 0x2D },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_GT },
227 {"KILLGE", 2, { 0x2E, 0x2E },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_GE },
228 {"KILLNE", 2, { 0x2F, 0x2F },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_NE },
229 {"AND_INT", 2, { 0x30, 0x30 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
230 {"OR_INT", 2, { 0x31, 0x31 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
231 {"XOR_INT", 2, { 0x32, 0x32 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
232 {"NOT_INT", 1, { 0x33, 0x33 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_INT_DST },
233 {"ADD_INT", 2, { 0x34, 0x34 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
234 {"SUB_INT", 2, { 0x35, 0x35 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_INT_DST },
235 {"MAX_INT", 2, { 0x36, 0x36 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
236 {"MIN_INT", 2, { 0x37, 0x37 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
237 {"MAX_UINT", 2, { 0x38, 0x38 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_UINT_DST },
238 {"MIN_UINT", 2, { 0x39, 0x39 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC | AF_UINT_DST },
239 {"SETE_INT", 2, { 0x3A, 0x3A },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_E | AF_INT_DST | AF_INT_CMP },
240 {"SETGT_INT", 2, { 0x3B, 0x3B },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_GT | AF_INT_DST | AF_INT_CMP },
241 {"SETGE_INT", 2, { 0x3C, 0x3C },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_GE | AF_INT_DST | AF_INT_CMP },
242 {"SETNE_INT", 2, { 0x3D, 0x3D },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_NE | AF_INT_DST | AF_INT_CMP },
243 {"SETGT_UINT", 2, { 0x3E, 0x3E },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_GT | AF_UINT_DST | AF_UINT_CMP },
244 {"SETGE_UINT", 2, { 0x3F, 0x3F },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_SET | AF_CC_GE | AF_UINT_DST | AF_UINT_CMP },
245 {"KILLGT_UINT", 2, { 0x40, 0x40 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_GT | AF_UINT_CMP },
246 {"KILLGE_UINT", 2, { 0x41, 0x41 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_GE | AF_UINT_CMP },
247 {"PRED_SETE_INT", 2, { 0x42, 0x42 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_E | AF_INT_CMP },
248 {"PRED_SETGT_INT", 2, { 0x43, 0x43 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_GT | AF_INT_CMP },
249 {"PRED_SETGE_INT", 2, { 0x44, 0x44 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_GE | AF_INT_CMP },
250 {"PRED_SETNE_INT", 2, { 0x45, 0x45 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED | AF_CC_NE | AF_INT_CMP },
251 {"KILLE_INT", 2, { 0x46, 0x46 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_E | AF_INT_CMP },
252 {"KILLGT_INT", 2, { 0x47, 0x47 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_GT | AF_INT_CMP },
253 {"KILLGE_INT", 2, { 0x48, 0x48 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_GE | AF_INT_CMP },
254 {"KILLNE_INT", 2, { 0x49, 0x49 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_KILL | AF_CC_NE | AF_INT_CMP },
255 {"PRED_SETE_PUSH_INT", 2, { 0x4A, 0x4A },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_E | AF_INT_CMP },
256 {"PRED_SETGT_PUSH_INT", 2, { 0x4B, 0x4B },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_GT | AF_INT_CMP },
257 {"PRED_SETGE_PUSH_INT", 2, { 0x4C, 0x4C },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_GE | AF_INT_CMP },
258 {"PRED_SETNE_PUSH_INT", 2, { 0x4D, 0x4D },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_NE | AF_INT_CMP },
259 {"PRED_SETLT_PUSH_INT", 2, { 0x4E, 0x4E },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_LT | AF_INT_CMP },
260 {"PRED_SETLE_PUSH_INT", 2, { 0x4F, 0x4F },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_LE | AF_INT_CMP },
261 {"FLT_TO_INT", 1, { 0x6B, 0x50 },{ AF_S, AF_S, AF_VS, AF_VS}, AF_INT_DST | AF_CVT },
262 {"BFREV_INT", 1, { -1, 0x51 },{ 0, 0, AF_VS, AF_VS}, AF_INT_DST },
263 {"ADDC_UINT", 2, { -1, 0x52 },{ 0, 0, AF_VS, AF_VS}, AF_UINT_DST },
264 {"SUBB_UINT", 2, { -1, 0x53 },{ 0, 0, AF_VS, AF_VS}, AF_UINT_DST },
265 {"GROUP_BARRIER", 0, { -1, 0x54 },{ 0, 0, AF_VS, AF_VS}, 0 },
266 {"GROUP_SEQ_BEGIN", 0, { -1, 0x55 },{ 0, 0, AF_VS, 0}, 0 },
267 {"GROUP_SEQ_END", 0, { -1, 0x56 },{ 0, 0, AF_VS, 0}, 0 },
268 {"SET_MODE", 2, { -1, 0x57 },{ 0, 0, AF_VS, AF_VS}, 0 },
269 {"SET_CF_IDX0", 0, { -1, 0x58 },{ 0, 0, AF_VS, 0}, 0 },
270 {"SET_CF_IDX1", 0, { -1, 0x59 },{ 0, 0, AF_VS, 0}, 0 },
271 {"SET_LDS_SIZE", 2, { -1, 0x5A },{ 0, 0, AF_VS, AF_VS}, 0 },
272 {"MUL_INT24", 2, { -1, 0x5B },{ 0, 0, 0, AF_V}, AF_INT_DST | AF_24 },
273 {"MULHI_INT24", 2, { -1, 0x5C },{ 0, 0, 0, AF_V}, AF_INT_DST | AF_24 },
274 {"FLT_TO_INT_TRUNC", 1, { -1, 0x5D },{ 0, 0, 0, AF_V}, AF_INT_DST | AF_CVT},
275 {"EXP_IEEE", 1, { 0x61, 0x81 },{ AF_S, AF_S, AF_S, AF_S}, AF_IEEE },
276 {"LOG_CLAMPED", 1, { 0x62, 0x82 },{ AF_S, AF_S, AF_S, AF_S}, 0 },
277 {"LOG_IEEE", 1, { 0x63, 0x83 },{ AF_S, AF_S, AF_S, AF_S}, AF_IEEE },
278 {"RECIP_CLAMPED", 1, { 0x64, 0x84 },{ AF_S, AF_S, AF_S, AF_S}, 0 },
279 {"RECIP_FF", 1, { 0x65, 0x85 },{ AF_S, AF_S, AF_S, AF_S}, 0 },
280 {"RECIP_IEEE", 1, { 0x66, 0x86 },{ AF_S, AF_S, AF_S, AF_S}, AF_IEEE },
281 {"RECIPSQRT_CLAMPED", 1, { 0x67, 0x87 },{ AF_S, AF_S, AF_S, AF_S}, 0 },
282 {"RECIPSQRT_FF", 1, { 0x68, 0x88 },{ AF_S, AF_S, AF_S, AF_S}, 0 },
283 {"RECIPSQRT_IEEE", 1, { 0x69, 0x89 },{ AF_S, AF_S, AF_S, AF_S}, AF_IEEE },
284 {"SQRT_IEEE", 1, { 0x6A, 0x8A },{ AF_S, AF_S, AF_S, AF_S}, AF_IEEE },
285 {"SIN", 1, { 0x6E, 0x8D },{ AF_S, AF_S, AF_S, AF_S}, 0 },
286 {"COS", 1, { 0x6F, 0x8E },{ AF_S, AF_S, AF_S, AF_S}, 0 },
287 {"MULLO_INT", 2, { 0x73, 0x8F },{ AF_S, AF_S, AF_S, AF_4V}, AF_M_COMM | AF_INT_DST | AF_REPL},
288 {"MULHI_INT", 2, { 0x74, 0x90 },{ AF_S, AF_S, AF_S, AF_4V}, AF_M_COMM | AF_INT_DST | AF_REPL},
289 {"MULLO_UINT", 2, { 0x75, 0x91 },{ AF_S, AF_S, AF_S, AF_4V}, AF_M_COMM | AF_UINT_DST | AF_REPL},
290 {"MULHI_UINT", 2, { 0x76, 0x92 },{ AF_S, AF_S, AF_S, AF_4V}, AF_M_COMM | AF_UINT_DST | AF_REPL},
291 {"RECIP_INT", 1, { 0x77, 0x93 },{ AF_S, AF_S, AF_S, 0}, AF_INT_DST },
292 {"RECIP_UINT", 1, { 0x78, 0x94 },{ AF_S, AF_S, AF_S, 0}, AF_UINT_DST },
293 {"RECIP_64", 2, { -1, 0x95 },{ 0, 0, AF_S, AF_S}, AF_64 },
294 {"RECIP_CLAMPED_64", 2, { -1, 0x96 },{ 0, 0, AF_S, AF_S}, AF_64 },
295 {"RECIPSQRT_64", 2, { -1, 0x97 },{ 0, 0, AF_S, AF_S}, AF_64 },
296 {"RECIPSQRT_CLAMPED_64", 2, { -1, 0x98 },{ 0, 0, AF_S, AF_S}, AF_64 },
297 {"SQRT_64", 2, { -1, 0x99 },{ 0, 0, AF_S, AF_S}, AF_64 },
298 {"FLT_TO_UINT", 1, { 0x79, 0x9A },{ AF_S, AF_S, AF_S, AF_V}, AF_UINT_DST | AF_CVT},
299 {"INT_TO_FLT", 1, { 0x6C, 0x9B },{ AF_S, AF_S, AF_S, AF_V}, AF_CVT},
300 {"UINT_TO_FLT", 1, { 0x6D, 0x9C },{ AF_S, AF_S, AF_S, AF_V}, AF_CVT },
301 {"BFM_INT", 2, { -1, 0xA0 },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
302 {"FLT32_TO_FLT16", 1, { -1, 0xA2 },{ 0, 0, AF_V, AF_V}, 0 },
303 {"FLT16_TO_FLT32", 1, { -1, 0xA3 },{ 0, 0, AF_V, AF_V}, 0 },
304 {"UBYTE0_FLT", 1, { -1, 0xA4 },{ 0, 0, AF_V, AF_V}, 0 },
305 {"UBYTE1_FLT", 1, { -1, 0xA5 },{ 0, 0, AF_V, AF_V}, 0 },
306 {"UBYTE2_FLT", 1, { -1, 0xA6 },{ 0, 0, AF_V, AF_V}, 0 },
307 {"UBYTE3_FLT", 1, { -1, 0xA7 },{ 0, 0, AF_V, AF_V}, 0 },
308 {"BCNT_INT", 1, { -1, 0xAA },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
309 {"FFBH_UINT", 1, { -1, 0xAB },{ 0, 0, AF_V, AF_V}, AF_UINT_DST },
310 {"FFBL_INT", 1, { -1, 0xAC },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
311 {"FFBH_INT", 1, { -1, 0xAD },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
312 {"FLT_TO_UINT4", 1, { -1, 0xAE },{ 0, 0, AF_V, AF_V}, AF_UINT_DST },
313 {"DOT_IEEE", 2, { -1, 0xAF },{ 0, 0, AF_V, AF_V}, AF_PREV_NEXT | AF_IEEE },
314 {"FLT_TO_INT_RPI", 1, { -1, 0xB0 },{ 0, 0, AF_V, AF_V}, AF_INT_DST | AF_CVT},
315 {"FLT_TO_INT_FLOOR", 1, { -1, 0xB1 },{ 0, 0, AF_V, AF_V}, AF_INT_DST | AF_CVT},
316 {"MULHI_UINT24", 2, { -1, 0xB2 },{ 0, 0, AF_V, AF_V}, AF_UINT_DST | AF_24 },
317 {"MBCNT_32HI_INT", 1, { -1, 0xB3 },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
318 {"OFFSET_TO_FLT", 1, { -1, 0xB4 },{ 0, 0, AF_V, AF_V}, 0 },
319 {"MUL_UINT24", 2, { -1, 0xB5 },{ 0, 0, AF_V, AF_V}, AF_UINT_DST | AF_24 },
320 {"BCNT_ACCUM_PREV_INT", 1, { -1, 0xB6 },{ 0, 0, AF_V, AF_V}, AF_INT_DST | AF_PREV_NEXT },
321 {"MBCNT_32LO_ACCUM_PREV_INT", 1, { -1, 0xB7 },{ 0, 0, AF_V, AF_V}, AF_INT_DST | AF_PREV_NEXT },
322 {"SETE_64", 2, { -1, 0xB8 },{ 0, 0, AF_V, AF_V}, AF_SET | AF_CC_E | AF_64 },
323 {"SETNE_64", 2, { -1, 0xB9 },{ 0, 0, AF_V, AF_V}, AF_SET | AF_CC_NE | AF_64 },
324 {"SETGT_64", 2, { -1, 0xBA },{ 0, 0, AF_V, AF_V}, AF_SET | AF_CC_GT | AF_64 },
325 {"SETGE_64", 2, { -1, 0xBB },{ 0, 0, AF_V, AF_V}, AF_SET | AF_CC_GE | AF_64 },
326 {"MIN_64", 2, { -1, 0xBC },{ 0, 0, AF_V, AF_V}, AF_64 },
327 {"MAX_64", 2, { -1, 0xBD },{ 0, 0, AF_V, AF_V}, AF_64 },
328 {"DOT4", 2, { 0x50, 0xBE },{ AF_4V, AF_4V, AF_4V, AF_4V}, AF_REPL },
329 {"DOT4_IEEE", 2, { 0x51, 0xBF },{ AF_4V, AF_4V, AF_4V, AF_4V}, AF_REPL | AF_IEEE },
330 {"CUBE", 2, { 0x52, 0xC0 },{ AF_4V, AF_4V, AF_4V, AF_4V}, 0 },
331 {"MAX4", 1, { 0x53, 0xC1 },{ AF_4V, AF_4V, AF_4V, AF_4V}, AF_REPL },
332 {"FREXP_64", 1, { 0x07, 0xC4 },{ AF_V, AF_V, AF_V, AF_V}, AF_64 },
333 {"LDEXP_64", 2, { 0x7A, 0xC5 },{ AF_V, AF_V, AF_V, AF_V}, AF_64 },
334 {"FRACT_64", 1, { 0x7B, 0xC6 },{ AF_V, AF_V, AF_V, AF_V}, AF_64 },
335 {"PRED_SETGT_64", 2, { 0x7C, 0xC7 },{ AF_V, AF_V, AF_V, AF_V}, AF_PRED | AF_CC_GT | AF_64 },
336 {"PRED_SETE_64", 2, { 0x7D, 0xC8 },{ AF_V, AF_V, AF_V, AF_V}, AF_PRED | AF_CC_E | AF_64 },
337 {"PRED_SETGE_64", 2, { 0x7E, 0xC9 },{ AF_V, AF_V, AF_V, AF_V}, AF_PRED | AF_CC_GE | AF_64 },
338 {"MUL_64", 2, { 0x1B, 0xCA },{ AF_V, AF_V, AF_V, AF_V}, AF_64 },
339 {"ADD_64", 2, { 0x17, 0xCB },{ AF_V, AF_V, AF_V, AF_V}, AF_64 },
340 {"MOVA_INT", 1, { 0x18, 0xCC },{ AF_V, AF_V, AF_V, AF_V}, AF_MOVA },
341 {"FLT64_TO_FLT32", 1, { 0x1C, 0xCD },{ AF_V, AF_V, AF_V, AF_V}, 0 },
342 {"FLT32_TO_FLT64", 1, { 0x1D, 0xCE },{ AF_V, AF_V, AF_V, AF_V}, 0 },
343 {"SAD_ACCUM_PREV_UINT", 2, { -1, 0xCF },{ 0, 0, AF_V, AF_V}, AF_UINT_DST | AF_PREV_NEXT },
344 {"DOT", 2, { -1, 0xD0 },{ 0, 0, AF_V, AF_V}, AF_PREV_NEXT },
345 {"MUL_PREV", 1, { -1, 0xD1 },{ 0, 0, AF_V, AF_V}, AF_PREV_INTERLEAVE },
346 {"MUL_IEEE_PREV", 1, { -1, 0xD2 },{ 0, 0, AF_V, AF_V}, AF_PREV_INTERLEAVE | AF_IEEE },
347 {"ADD_PREV", 1, { -1, 0xD3 },{ 0, 0, AF_V, AF_V}, AF_PREV_INTERLEAVE },
348 {"MULADD_PREV", 2, { -1, 0xD4 },{ 0, 0, AF_V, AF_V}, AF_PREV_INTERLEAVE },
349 {"MULADD_IEEE_PREV", 2, { -1, 0xD5 },{ 0, 0, AF_V, AF_V}, AF_PREV_INTERLEAVE | AF_IEEE },
350 {"INTERP_XY", 2, { -1, 0xD6 },{ 0, 0, AF_4V, AF_4V}, AF_INTERP },
351 {"INTERP_ZW", 2, { -1, 0xD7 },{ 0, 0, AF_4V, AF_4V}, AF_INTERP },
352 {"INTERP_X", 2, { -1, 0xD8 },{ 0, 0, AF_V, AF_V}, AF_INTERP },
353 {"INTERP_Z", 2, { -1, 0xD9 },{ 0, 0, AF_V, AF_V}, AF_INTERP },
354 {"STORE_FLAGS", 1, { -1, 0xDA },{ 0, 0, AF_V, AF_V}, 0 },
355 {"LOAD_STORE_FLAGS", 1, { -1, 0xDB },{ 0, 0, AF_V, AF_V}, 0 },
356 {"LDS_1A", 2, { -1, 0xDC },{ 0, 0, AF_V, AF_V}, 0 },
357 {"LDS_1A1D", 2, { -1, 0xDD },{ 0, 0, AF_V, AF_V}, 0 },
358 {"LDS_2A", 2, { -1, 0xDF },{ 0, 0, AF_V, AF_V}, 0 },
359 {"INTERP_LOAD_P0", 1, { -1, 0xE0 },{ 0, 0, AF_V, AF_V}, AF_INTERP },
360 {"INTERP_LOAD_P10", 1, { -1, 0xE1 },{ 0, 0, AF_V, AF_V}, AF_INTERP },
361 {"INTERP_LOAD_P20", 1, { -1, 0xE2 },{ 0, 0, AF_V, AF_V}, AF_INTERP },
362 {"BFE_UINT", 3, { -1, 0x04 },{ 0, 0, AF_V, AF_V}, AF_UINT_DST },
363 {"BFE_INT", 3, { -1, 0x05 },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
364 {"BFI_INT", 3, { -1, 0x06 },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
365 {"FMA", 3, { -1, 0x07 },{ 0, 0, AF_V, AF_V}, 0 },
366 {"MULADD_INT24", 3, { -1, 0x08 },{ 0, 0, 0, AF_V}, AF_INT_DST | AF_24 },
367 {"CNDNE_64", 3, { -1, 0x09 },{ 0, 0, AF_V, AF_V}, AF_CMOV | AF_64 },
368 {"FMA_64", 3, { -1, 0x0A },{ 0, 0, AF_V, AF_V}, AF_64 },
369 {"LERP_UINT", 3, { -1, 0x0B },{ 0, 0, AF_V, AF_V}, AF_UINT_DST },
370 {"BIT_ALIGN_INT", 3, { -1, 0x0C },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
371 {"BYTE_ALIGN_INT", 3, { -1, 0x0D },{ 0, 0, AF_V, AF_V}, AF_INT_DST },
372 {"SAD_ACCUM_UINT", 3, { -1, 0x0E },{ 0, 0, AF_V, AF_V}, AF_UINT_DST },
373 {"SAD_ACCUM_HI_UINT", 3, { -1, 0x0F },{ 0, 0, AF_V, AF_V}, AF_UINT_DST },
374 {"MULADD_UINT24", 3, { -1, 0x10 },{ 0, 0, AF_V, AF_V}, AF_UINT_DST | AF_24 },
375 {"LDS_IDX_OP", 3, { -1, 0x11 },{ 0, 0, AF_V, AF_V}, 0 },
376 {"MULADD", 3, { 0x10, 0x14 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM },
377 {"MULADD_M2", 3, { 0x11, 0x15 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM },
378 {"MULADD_M4", 3, { 0x12, 0x16 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM },
379 {"MULADD_D2", 3, { 0x13, 0x17 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM },
380 {"MULADD_IEEE", 3, { 0x14, 0x18 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_IEEE },
381 {"CNDE", 3, { 0x18, 0x19 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_CMOV | AF_CC_E },
382 {"CNDGT", 3, { 0x19, 0x1A },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_CMOV | AF_CC_GT },
383 {"CNDGE", 3, { 0x1A, 0x1B },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_CMOV | AF_CC_GE },
384 {"CNDE_INT", 3, { 0x1C, 0x1C },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_CMOV | AF_CC_E | AF_INT_CMP },
385 {"CNDGT_INT", 3, { 0x1D, 0x1D },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_CMOV | AF_CC_GT | AF_INT_CMP },
386 {"CNDGE_INT", 3, { 0x1E, 0x1E },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_CMOV | AF_CC_GE | AF_INT_CMP },
387 {"MUL_LIT", 3, { 0x0C, 0x1F },{ AF_S, AF_S, AF_S, AF_V}, 0 },
388
389 {"MOVA", 1, { 0x15, -1 },{ AF_V, AF_V, 0, 0}, AF_MOVA },
390 {"MOVA_FLOOR", 1, { 0x16, -1 },{ AF_V, AF_V, 0, 0}, AF_MOVA },
391 {"MOVA_GPR_INT", 1, { 0x60, -1 },{ AF_S, 0, 0, 0}, AF_MOVA },
392
393 {"MULADD_64", 3, { 0x08, -1 },{ AF_V, AF_V, 0, 0}, AF_64 },
394 {"MULADD_64_M2", 3, { 0x09, -1 },{ AF_V, AF_V, 0, 0}, AF_64 },
395 {"MULADD_64_M4", 3, { 0x0A, -1 },{ AF_V, AF_V, 0, 0}, AF_64 },
396 {"MULADD_64_D2", 3, { 0x0B, -1 },{ AF_V, AF_V, 0, 0}, AF_64 },
397 {"MUL_LIT_M2", 3, { 0x0D, -1 },{ AF_VS, AF_VS, 0, 0}, 0 },
398 {"MUL_LIT_M4", 3, { 0x0E, -1 },{ AF_VS, AF_VS, 0, 0}, 0 },
399 {"MUL_LIT_D2", 3, { 0x0F, -1 },{ AF_VS, AF_VS, 0, 0}, 0 },
400 {"MULADD_IEEE_M2", 3, { 0x15, -1 },{ AF_VS, AF_VS, 0, 0}, AF_IEEE },
401 {"MULADD_IEEE_M4", 3, { 0x16, -1 },{ AF_VS, AF_VS, 0, 0}, AF_IEEE },
402 {"MULADD_IEEE_D2", 3, { 0x17, -1 },{ AF_VS, AF_VS, 0, 0}, AF_IEEE },
403
404 {"LDS_ADD", 2, { -1, 0x0011 },{ 0, 0, AF_V, AF_V}, AF_LDS },
405 {"LDS_SUB", 2, { -1, 0x0111 },{ 0, 0, AF_V, AF_V}, AF_LDS },
406 {"LDS_RSUB", 2, { -1, 0x0211 },{ 0, 0, AF_V, AF_V}, AF_LDS },
407 {"LDS_INC", 2, { -1, 0x0311 },{ 0, 0, AF_V, AF_V}, AF_LDS },
408 {"LDS_DEC", 2, { -1, 0x0411 },{ 0, 0, AF_V, AF_V}, AF_LDS },
409 {"LDS_MIN_INT", 2, { -1, 0x0511 },{ 0, 0, AF_V, AF_V}, AF_LDS | AF_INT_DST },
410 {"LDS_MAX_INT", 2, { -1, 0x0611 },{ 0, 0, AF_V, AF_V}, AF_LDS | AF_INT_DST },
411 {"LDS_MIN_UINT", 2, { -1, 0x0711 },{ 0, 0, AF_V, AF_V}, AF_LDS | AF_UINT_DST },
412 {"LDS_MAX_UINT", 2, { -1, 0x0811 },{ 0, 0, AF_V, AF_V}, AF_LDS | AF_UINT_DST },
413 {"LDS_AND", 2, { -1, 0x0911 },{ 0, 0, AF_V, AF_V}, AF_LDS },
414 {"LDS_OR", 2, { -1, 0x0A11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
415 {"LDS_XOR", 2, { -1, 0x0B11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
416 {"LDS_MSKOR", 3, { -1, 0x0C11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
417 {"LDS_WRITE", 2, { -1, 0x0D11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
418 {"LDS_WRITE_REL", 3, { -1, 0x0E11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
419 {"LDS_WRITE2", 3, { -1, 0x0F11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
420 {"LDS_CMP_STORE", 3, { -1, 0x1011 },{ 0, 0, AF_V, AF_V}, AF_LDS },
421 {"LDS_CMP_STORE_SPF", 3, { -1, 0x1111 },{ 0, 0, AF_V, AF_V}, AF_LDS },
422 {"LDS_BYTE_WRITE", 2, { -1, 0x1211 },{ 0, 0, AF_V, AF_V}, AF_LDS },
423 {"LDS_SHORT_WRITE", 2, { -1, 0x1311 },{ 0, 0, AF_V, AF_V}, AF_LDS },
424 {"LDS_ADD_RET", 2, { -1, 0x2011 },{ 0, 0, AF_V, AF_V}, AF_LDS },
425 {"LDS_SUB_RET", 2, { -1, 0x2111 },{ 0, 0, AF_V, AF_V}, AF_LDS },
426 {"LDS_RSUB_RET", 2, { -1, 0x2211 },{ 0, 0, AF_V, AF_V}, AF_LDS },
427 {"LDS_INC_RET", 2, { -1, 0x2311 },{ 0, 0, AF_V, AF_V}, AF_LDS },
428 {"LDS_DEC_RET", 2, { -1, 0x2411 },{ 0, 0, AF_V, AF_V}, AF_LDS },
429 {"LDS_MIN_INT_RET", 2, { -1, 0x2511 },{ 0, 0, AF_V, AF_V}, AF_LDS | AF_INT_DST },
430 {"LDS_MAX_INT_RET", 2, { -1, 0x2611 },{ 0, 0, AF_V, AF_V}, AF_LDS | AF_INT_DST },
431 {"LDS_MIN_UINT_RET", 2, { -1, 0x2711 },{ 0, 0, AF_V, AF_V}, AF_LDS | AF_UINT_DST },
432 {"LDS_MAX_UINT_RET", 2, { -1, 0x2811 },{ 0, 0, AF_V, AF_V}, AF_LDS | AF_UINT_DST },
433 {"LDS_AND_RET", 2, { -1, 0x2911 },{ 0, 0, AF_V, AF_V}, AF_LDS },
434 {"LDS_OR_RET", 2, { -1, 0x2A11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
435 {"LDS_XOR_RET", 2, { -1, 0x2B11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
436 {"LDS_MSKOR_RET", 3, { -1, 0x2C11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
437 {"LDS_XCHG_RET", 2, { -1, 0x2D11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
438 {"LDS_XCHG_REL_RET", 3, { -1, 0x2E11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
439 {"LDS_XCHG2_RET", 3, { -1, 0x2F11 },{ 0, 0, AF_V, AF_V}, AF_LDS },
440 {"LDS_CMP_XCHG_RET", 3, { -1, 0x3011 },{ 0, 0, AF_V, AF_V}, AF_LDS },
441 {"LDS_CMP_XCHG_SPF_RET", 3, { -1, 0x3111 },{ 0, 0, AF_V, AF_V}, AF_LDS },
442 {"LDS_READ_RET", 1, { -1, 0x3211 },{ 0, 0, AF_V, AF_V}, AF_LDS },
443 {"LDS_READ_REL_RET", 1, { -1, 0x3311 },{ 0, 0, AF_V, AF_V}, AF_LDS },
444 {"LDS_READ2_RET", 2, { -1, 0x3411 },{ 0, 0, AF_V, AF_V}, AF_LDS },
445 {"LDS_READWRITE_RET", 3, { -1, 0x3511 },{ 0, 0, AF_V, AF_V}, AF_LDS },
446 {"LDS_BYTE_READ_RET", 1, { -1, 0x3611 },{ 0, 0, AF_V, AF_V}, AF_LDS },
447 {"LDS_UBYTE_READ_RET", 1, { -1, 0x3711 },{ 0, 0, AF_V, AF_V}, AF_LDS },
448 {"LDS_SHORT_READ_RET", 1, { -1, 0x3811 },{ 0, 0, AF_V, AF_V}, AF_LDS },
449 {"LDS_USHORT_READ_RET", 1, { -1, 0x3911 },{ 0, 0, AF_V, AF_V}, AF_LDS },
450 };
451
452 static const struct fetch_op_info fetch_op_table[] = {
453 {"VFETCH", { 0x000000, 0x000000, 0x000000, 0x000000 }, FF_VTX },
454 {"SEMFETCH", { 0x000001, 0x000001, 0x000001, 0x000001 }, FF_VTX },
455
456 {"READ_SCRATCH", { -1, 0x000002, 0x000002, 0x000002 }, FF_VTX | FF_MEM },
457 {"READ_REDUCT", { -1, 0x000102, -1, -1 }, FF_VTX | FF_MEM },
458 {"READ_MEM", { -1, 0x000202, 0x000202, 0x000202 }, FF_VTX | FF_MEM },
459 {"DS_LOCAL_WRITE", { -1, 0x000402, -1, -1 }, FF_VTX | FF_MEM },
460 {"DS_LOCAL_READ", { -1, 0x000502, -1, -1 }, FF_VTX | FF_MEM },
461
462 {"GDS_ADD", { -1, -1, 0x020002, 0x020002 }, FF_GDS },
463 {"GDS_SUB", { -1, -1, 0x020102, 0x020102 }, FF_GDS },
464 {"GDS_RSUB", { -1, -1, 0x020202, 0x020202 }, FF_GDS },
465 {"GDS_INC", { -1, -1, 0x020302, 0x020302 }, FF_GDS },
466 {"GDS_DEC", { -1, -1, 0x020402, 0x020402 }, FF_GDS },
467 {"GDS_MIN_INT", { -1, -1, 0x020502, 0x020502 }, FF_GDS },
468 {"GDS_MAX_INT", { -1, -1, 0x020602, 0x020602 }, FF_GDS },
469 {"GDS_MIN_UINT", { -1, -1, 0x020702, 0x020702 }, FF_GDS },
470 {"GDS_MAX_UINT", { -1, -1, 0x020802, 0x020802 }, FF_GDS },
471 {"GDS_AND", { -1, -1, 0x020902, 0x020902 }, FF_GDS },
472 {"GDS_OR", { -1, -1, 0x020A02, 0x020A02 }, FF_GDS },
473 {"GDS_XOR", { -1, -1, 0x020B02, 0x020B02 }, FF_GDS },
474 {"GDS_MSKOR", { -1, -1, 0x030C02, 0x030C02 }, FF_GDS },
475 {"GDS_WRITE", { -1, -1, 0x020D02, 0x020D02 }, FF_GDS },
476 {"GDS_WRITE_REL", { -1, -1, 0x030E02, 0x030E02 }, FF_GDS },
477 {"GDS_WRITE2", { -1, -1, 0x030F02, 0x030F02 }, FF_GDS },
478 {"GDS_CMP_STORE", { -1, -1, 0x031002, 0x031002 }, FF_GDS },
479 {"GDS_CMP_STORE_SPF", { -1, -1, 0x031102, 0x031102 }, FF_GDS },
480 {"GDS_BYTE_WRITE", { -1, -1, 0x021202, 0x021202 }, FF_GDS },
481 {"GDS_SHORT_WRITE", { -1, -1, 0x021302, 0x021302 }, FF_GDS },
482 {"GDS_ADD_RET", { -1, -1, 0x122002, 0x122002 }, FF_GDS },
483 {"GDS_SUB_RET", { -1, -1, 0x122102, 0x122102 }, FF_GDS },
484 {"GDS_RSUB_RET", { -1, -1, 0x122202, 0x122202 }, FF_GDS },
485 {"GDS_INC_RET", { -1, -1, 0x122302, 0x122302 }, FF_GDS },
486 {"GDS_DEC_RET", { -1, -1, 0x122402, 0x122402 }, FF_GDS },
487 {"GDS_MIN_INT_RET", { -1, -1, 0x122502, 0x122502 }, FF_GDS },
488 {"GDS_MAX_INT_RET", { -1, -1, 0x122602, 0x122602 }, FF_GDS },
489 {"GDS_MIN_UINT_RET", { -1, -1, 0x122702, 0x122702 }, FF_GDS },
490 {"GDS_MAX_UINT_RET", { -1, -1, 0x122802, 0x122802 }, FF_GDS },
491 {"GDS_AND_RET", { -1, -1, 0x122902, 0x122902 }, FF_GDS },
492 {"GDS_OR_RET", { -1, -1, 0x122A02, 0x122A02 }, FF_GDS },
493 {"GDS_XOR_RET", { -1, -1, 0x122B02, 0x122B02 }, FF_GDS },
494 {"GDS_MSKOR_RET", { -1, -1, 0x132C02, 0x132C02 }, FF_GDS },
495 {"GDS_XCHG_RET", { -1, -1, 0x122D02, 0x122D02 }, FF_GDS },
496 {"GDS_XCHG_REL_RET", { -1, -1, 0x232E02, 0x232E02 }, FF_GDS },
497 {"GDS_XCHG2_RET", { -1, -1, 0x232F02, 0x232F02 }, FF_GDS },
498 {"GDS_CMP_XCHG_RET", { -1, -1, 0x133002, 0x133002 }, FF_GDS },
499 {"GDS_CMP_XCHG_SPF_RET", { -1, -1, 0x133102, 0x133102 }, FF_GDS },
500 {"GDS_READ_RET", { -1, -1, 0x113202, 0x113202 }, FF_GDS },
501 {"GDS_READ_REL_RET", { -1, -1, 0x213302, 0x213302 }, FF_GDS },
502 {"GDS_READ2_RET", { -1, -1, 0x223402, 0x223402 }, FF_GDS },
503 {"GDS_READWRITE_RET", { -1, -1, 0x133502, 0x133502 }, FF_GDS },
504 {"GDS_BYTE_READ_RET", { -1, -1, 0x113602, 0x113602 }, FF_GDS },
505 {"GDS_UBYTE_READ_RET", { -1, -1, 0x113702, 0x113702 }, FF_GDS },
506 {"GDS_SHORT_READ_RET", { -1, -1, 0x113802, 0x113802 }, FF_GDS },
507 {"GDS_USHORT_READ_RET", { -1, -1, 0x113902, 0x113902 }, FF_GDS },
508 {"GDS_ATOMIC_ORDERED_ALLOC", { -1, -1, 0x113F02, 0x113F02 }, FF_GDS },
509
510 {"TF_WRITE", { -1, -1, 0x020502, 0x020502 }, FF_GDS },
511
512 {"DS_GLOBAL_WRITE", { -1, 0x000602, -1, -1 }, 0 },
513 {"DS_GLOBAL_READ", { -1, 0x000702, -1, -1 }, 0 },
514
515 {"LD", { 0x000003, 0x000003, 0x000003, 0x000003 }, 0 },
516 {"LDFPTR", { -1, -1, 0x000103, 0x000103 }, 0 },
517 {"GET_TEXTURE_RESINFO", { 0x000004, 0x000004, 0x000004, 0x000004 }, 0 },
518 {"GET_NUMBER_OF_SAMPLES", { 0x000005, 0x000005, 0x000005, 0x000005 }, 0 },
519 {"GET_LOD", { 0x000006, 0x000006, 0x000006, 0x000006 }, 0 },
520 {"GET_GRADIENTS_H", { 0x000007, 0x000007, 0x000007, 0x000007 }, FF_GETGRAD },
521 {"GET_GRADIENTS_V", { 0x000008, 0x000008, 0x000008, 0x000008 }, FF_GETGRAD },
522 {"GET_GRADIENTS_H_FINE", { -1, -1, 0x000107, 0x000107 }, FF_GETGRAD },
523 {"GET_GRADIENTS_V_FINE", { -1, -1, 0x000108, 0x000108 }, FF_GETGRAD },
524 {"GET_LERP", { 0x000009, 0x000009, -1, -1 }, 0 },
525 {"SET_TEXTURE_OFFSETS", { -1, -1, 0x000009, 0x000009 }, 0 },
526 {"KEEP_GRADIENTS", { -1, 0x00000A, 0x00000A, 0x00000A }, 0 },
527 {"SET_GRADIENTS_H", { 0x00000B, 0x00000B, 0x00000B, 0x00000B }, FF_SETGRAD },
528 {"SET_GRADIENTS_V", { 0x00000C, 0x00000C, 0x00000C, 0x00000C }, FF_SETGRAD },
529 {"SET_GRADIENTS_H_COARSE", { -1, -1, -1, 0x00010B }, FF_SETGRAD },
530 {"SET_GRADIENTS_V_COARSE", { -1, -1, -1, 0x00010C }, FF_SETGRAD },
531 {"SET_GRADIENTS_H_PACKED_FINE", { -1, -1, -1, 0x00020B }, FF_SETGRAD },
532 {"SET_GRADIENTS_V_PACKED_FINE", { -1, -1, -1, 0x00020C }, FF_SETGRAD },
533 {"SET_GRADIENTS_H_PACKED_COARSE", { -1, -1, -1, 0x00030B }, FF_SETGRAD },
534 {"SET_GRADIENTS_V_PACKED_COARSE", { -1, -1, -1, 0x00030C }, FF_SETGRAD },
535 {"PASS", { 0x00000D, 0x00000D, 0x00000D, 0x00000D }, 0 }, /* ???? 700, eg, cm docs - marked as reserved */
536 {"PASS1", { -1, -1, 0x00010D, 0x00010D }, 0 },
537 {"PASS2", { -1, -1, 0x00020D, 0x00020D }, 0 },
538 {"PASS3", { -1, -1, 0x00030D, 0x00030D }, 0 },
539 {"SET_CUBEMAP_INDEX", { 0x00000E, 0x00000E, -1, -1 }, 0 },
540 {"GET_BUFFER_RESINFO", { -1, -1, 0x00000E, 0x00000E }, FF_VTX },
541 {"FETCH4", { 0x00000F, 0x00000F, -1, -1 }, 0 },
542
543 {"SAMPLE", { 0x000010, 0x000010, 0x000010, 0x000010 }, FF_TEX },
544 {"SAMPLE_L", { 0x000011, 0x000011, 0x000011, 0x000011 }, FF_TEX },
545 {"SAMPLE_LB", { 0x000012, 0x000012, 0x000012, 0x000012 }, FF_TEX },
546 {"SAMPLE_LZ", { 0x000013, 0x000013, 0x000013, 0x000013 }, FF_TEX },
547 {"SAMPLE_G", { 0x000014, 0x000014, 0x000014, 0x000014 }, FF_TEX | FF_USEGRAD },
548 {"SAMPLE_G_L", { 0x000015, 0x000015, -1, -1 }, FF_TEX | FF_USEGRAD},
549 {"GATHER4", { -1, -1, 0x000015, 0x000015 }, FF_TEX },
550 {"SAMPLE_G_LB", { 0x000016, 0x000016, 0x000016, 0x000016 }, FF_TEX | FF_USEGRAD},
551 {"SAMPLE_G_LZ", { 0x000017, 0x000017, -1, -1 }, FF_TEX | FF_USEGRAD},
552 {"GATHER4_O", { -1, -1, 0x000017, 0x000017 }, FF_TEX },
553 {"SAMPLE_C", { 0x000018, 0x000018, 0x000018, 0x000018 }, FF_TEX },
554 {"SAMPLE_C_L", { 0x000019, 0x000019, 0x000019, 0x000019 }, FF_TEX },
555 {"SAMPLE_C_LB", { 0x00001A, 0x00001A, 0x00001A, 0x00001A }, FF_TEX },
556 {"SAMPLE_C_LZ", { 0x00001B, 0x00001B, 0x00001B, 0x00001B }, FF_TEX },
557 {"SAMPLE_C_G", { 0x00001C, 0x00001C, 0x00001C, 0x00001C }, FF_TEX | FF_USEGRAD},
558 {"SAMPLE_C_G_L", { 0x00001D, 0x00001D, -1, -1 }, FF_TEX | FF_USEGRAD},
559 {"GATHER4_C", { -1, -1, 0x00001D, 0x00001D }, FF_TEX },
560 {"SAMPLE_C_G_LB", { 0x00001E, 0x00001E, 0x00001E, 0x00001E }, FF_TEX | FF_USEGRAD},
561 {"SAMPLE_C_G_LZ", { 0x00001F, 0x00001F, -1, -1 }, FF_TEX | FF_USEGRAD},
562 {"GATHER4_C_O", { -1, -1, 0x00001F, 0x00001F }, FF_TEX }
563 };
564
565 static const struct cf_op_info cf_op_table[] = {
566 {"NOP", { 0x00, 0x00, 0x00, 0x00 }, 0 },
567
568 {"TEX", { 0x01, 0x01, 0x01, 0x01 }, CF_CLAUSE | CF_FETCH | CF_UNCOND }, /* merged with "TC" entry */
569 {"VTX", { 0x02, 0x02, 0x02, -1 }, CF_CLAUSE | CF_FETCH | CF_UNCOND }, /* merged with "VC" entry */
570 {"VTX_TC", { 0x03, 0x03, -1, -1 }, CF_CLAUSE | CF_FETCH | CF_UNCOND },
571 {"GDS", { -1, -1, 0x03, 0x03 }, CF_CLAUSE | CF_FETCH | CF_UNCOND },
572
573 {"LOOP_START", { 0x04, 0x04, 0x04, 0x04 }, CF_LOOP | CF_LOOP_START },
574 {"LOOP_END", { 0x05, 0x05, 0x05, 0x05 }, CF_LOOP },
575 {"LOOP_START_DX10", { 0x06, 0x06, 0x06, 0x06 }, CF_LOOP | CF_LOOP_START },
576 {"LOOP_START_NO_AL", { 0x07, 0x07, 0x07, 0x07 }, CF_LOOP | CF_LOOP_START },
577 {"LOOP_CONTINUE", { 0x08, 0x08, 0x08, 0x08 }, CF_LOOP },
578 {"LOOP_BREAK", { 0x09, 0x09, 0x09, 0x09 }, CF_LOOP },
579 {"JUMP", { 0x0A, 0x0A, 0x0A, 0x0A }, CF_BRANCH },
580 {"PUSH", { 0x0B, 0x0B, 0x0B, 0x0B }, CF_BRANCH },
581 {"PUSH_ELSE", { 0x0C, 0x0C, -1, -1 }, CF_BRANCH },
582 {"ELSE", { 0x0D, 0x0D, 0x0D, 0x0D }, CF_BRANCH },
583 {"POP", { 0x0E, 0x0E, 0x0E, 0x0E }, CF_BRANCH },
584 {"POP_JUMP", { 0x0F, 0x0F, -1, -1 }, CF_BRANCH },
585 {"POP_PUSH", { 0x10, 0x10, -1, -1 }, CF_BRANCH },
586 {"POP_PUSH_ELSE", { 0x11, 0x11, -1, -1 }, CF_BRANCH },
587 {"CALL", { 0x12, 0x12, 0x12, 0x12 }, CF_CALL },
588 {"CALL_FS", { 0x13, 0x13, 0x13, 0x13 }, CF_CALL },
589 {"RET", { 0x14, 0x14, 0x14, 0x14 }, 0 },
590 {"EMIT_VERTEX", { 0x15, 0x15, 0x15, 0x15 }, CF_EMIT | CF_UNCOND },
591 {"EMIT_CUT_VERTEX", { 0x16, 0x16, 0x16, 0x16 }, CF_EMIT | CF_UNCOND },
592 {"CUT_VERTEX", { 0x17, 0x17, 0x17, 0x17 }, CF_EMIT | CF_UNCOND },
593 {"KILL", { 0x18, 0x18, 0x18, 0x18 }, CF_UNCOND },
594 {"END_PROGRAM", { 0x19, 0x19, 0x19, 0x19 }, 0 }, /* ??? "reserved" in isa docs */
595 {"WAIT_ACK", { -1, 0x1A, 0x1A, 0x1A }, 0 },
596 {"TEX_ACK", { -1, 0x1B, 0x1B, 0x1B }, CF_CLAUSE | CF_FETCH | CF_ACK | CF_UNCOND },
597 {"VTX_ACK", { -1, 0x1C, 0x1C, -1 }, CF_CLAUSE | CF_FETCH | CF_ACK | CF_UNCOND },
598 {"VTX_TC_ACK", { -1, 0x1D, -1, -1 }, CF_CLAUSE | CF_FETCH | CF_ACK | CF_UNCOND },
599 {"JUMPTABLE", { -1, -1, 0x1D, 0x1D }, CF_BRANCH },
600 {"WAVE_SYNC", { -1, -1, 0x1E, 0x1E }, 0 },
601 {"HALT", { -1, -1, 0x1F, 0x1F }, 0 },
602 {"CF_END", { -1, -1, -1, 0x20 }, 0 },
603 {"LDS_DEALLOC", { -1, -1, -1, 0x21 }, 0 },
604 {"PUSH_WQM", { -1, -1, -1, 0x22 }, CF_BRANCH },
605 {"POP_WQM", { -1, -1, -1, 0x23 }, CF_BRANCH },
606 {"ELSE_WQM", { -1, -1, -1, 0x24 }, CF_BRANCH },
607 {"JUMP_ANY", { -1, -1, -1, 0x25 }, CF_BRANCH },
608
609 /* ??? next 5 added from CAYMAN ISA doc, not in the original table */
610 {"REACTIVATE", { -1, -1, -1, 0x26 }, 0 },
611 {"REACTIVATE_WQM", { -1, -1, -1, 0x27 }, 0 },
612 {"INTERRUPT", { -1, -1, -1, 0x28 }, 0 },
613 {"INTERRUPT_AND_SLEEP", { -1, -1, -1, 0x29 }, 0 },
614 {"SET_PRIORITY", { -1, -1, -1, 0x2A }, 0 },
615
616 {"MEM_STREAM0_BUF0", { -1, -1, 0x40, 0x40 }, CF_MEM | CF_STRM },
617 {"MEM_STREAM0_BUF1", { -1, -1, 0x41, 0x41 }, CF_MEM | CF_STRM },
618 {"MEM_STREAM0_BUF2", { -1, -1, 0x42, 0x42 }, CF_MEM | CF_STRM },
619 {"MEM_STREAM0_BUF3", { -1, -1, 0x43, 0x43 }, CF_MEM | CF_STRM },
620 {"MEM_STREAM1_BUF0", { -1, -1, 0x44, 0x44 }, CF_MEM | CF_STRM },
621 {"MEM_STREAM1_BUF1", { -1, -1, 0x45, 0x45 }, CF_MEM | CF_STRM },
622 {"MEM_STREAM1_BUF2", { -1, -1, 0x46, 0x46 }, CF_MEM | CF_STRM },
623 {"MEM_STREAM1_BUF3", { -1, -1, 0x47, 0x47 }, CF_MEM | CF_STRM },
624 {"MEM_STREAM2_BUF0", { -1, -1, 0x48, 0x48 }, CF_MEM | CF_STRM },
625 {"MEM_STREAM2_BUF1", { -1, -1, 0x49, 0x49 }, CF_MEM | CF_STRM },
626 {"MEM_STREAM2_BUF2", { -1, -1, 0x4A, 0x4A }, CF_MEM | CF_STRM },
627 {"MEM_STREAM2_BUF3", { -1, -1, 0x4B, 0x4B }, CF_MEM | CF_STRM },
628 {"MEM_STREAM3_BUF0", { -1, -1, 0x4C, 0x4C }, CF_MEM | CF_STRM },
629 {"MEM_STREAM3_BUF1", { -1, -1, 0x4D, 0x4D }, CF_MEM | CF_STRM },
630 {"MEM_STREAM3_BUF2", { -1, -1, 0x4E, 0x4E }, CF_MEM | CF_STRM },
631 {"MEM_STREAM3_BUF3", { -1, -1, 0x4F, 0x4F }, CF_MEM | CF_STRM },
632
633 {"MEM_STREAM0", { 0x20, 0x20, -1, -1 }, CF_MEM | CF_STRM },
634 {"MEM_STREAM1", { 0x21, 0x21, -1, -1 }, CF_MEM | CF_STRM },
635 {"MEM_STREAM2", { 0x22, 0x22, -1, -1 }, CF_MEM | CF_STRM },
636 {"MEM_STREAM3", { 0x23, 0x23, -1, -1 }, CF_MEM | CF_STRM },
637
638 {"MEM_SCRATCH", { 0x24, 0x24, 0x50, 0x50 }, CF_MEM },
639 {"MEM_REDUCT", { 0x25, 0x25, -1, -1 }, CF_MEM },
640 {"MEM_RING", { 0x26, 0x26, 0x52, 0x52 }, CF_MEM },
641
642 {"EXPORT", { 0x27, 0x27, 0x53, 0x53 }, CF_EXP },
643 {"EXPORT_DONE", { 0x28, 0x28, 0x54, 0x54 }, CF_EXP },
644
645 {"MEM_EXPORT", { -1, 0x3A, 0x55, 0x55 }, CF_MEM },
646 {"MEM_RAT", { -1, -1, 0x56, 0x56 }, CF_MEM | CF_RAT },
647 {"MEM_RAT_NOCACHE", { -1, -1, 0x57, 0x57 }, CF_MEM | CF_RAT },
648 {"MEM_RING1", { -1, -1, 0x58, 0x58 }, CF_MEM },
649 {"MEM_RING2", { -1, -1, 0x59, 0x59 }, CF_MEM },
650 {"MEM_RING3", { -1, -1, 0x5A, 0x5A }, CF_MEM },
651 {"MEM_MEM_COMBINED", { -1, -1, 0x5B, 0x5B }, CF_MEM },
652 {"MEM_RAT_COMBINED_NOCACHE", { -1, -1, 0x5C, 0x5C }, CF_MEM | CF_RAT },
653 {"MEM_RAT_COMBINED", { -1, -1, -1, 0x5D }, CF_MEM | CF_RAT }, /* ??? not in cayman isa doc */
654
655 {"EXPORT_DONE_END", { -1, -1, -1, 0x5E }, CF_EXP }, /* ??? not in cayman isa doc */
656
657 {"ALU", { 0x08, 0x08, 0x08, 0x08 }, CF_CLAUSE | CF_ALU },
658 {"ALU_PUSH_BEFORE", { 0x09, 0x09, 0x09, 0x09 }, CF_CLAUSE | CF_ALU },
659 {"ALU_POP_AFTER", { 0x0A, 0x0A, 0x0A, 0x0A }, CF_CLAUSE | CF_ALU },
660 {"ALU_POP2_AFTER", { 0x0B, 0x0B, 0x0B, 0x0B }, CF_CLAUSE | CF_ALU },
661 {"ALU_EXT", { -1, -1, 0x0C, 0x0C }, CF_CLAUSE | CF_ALU | CF_ALU_EXT },
662 {"ALU_CONTINUE", { 0x0D, 0x0D, 0x0D, -1 }, CF_CLAUSE | CF_ALU },
663 {"ALU_BREAK", { 0x0E, 0x0E, 0x0E, -1 }, CF_CLAUSE | CF_ALU },
664 {"ALU_ELSE_AFTER", { 0x0F, 0x0F, 0x0F, 0x0F }, CF_CLAUSE | CF_ALU },
665 {"CF_NATIVE", { 0x00, 0x00, 0x00, 0x00 }, 0 }
666 };
667
668
669 #define ALU_OP2_ADD 0
670 #define ALU_OP2_MUL 1
671 #define ALU_OP2_MUL_IEEE 2
672 #define ALU_OP2_MAX 3
673 #define ALU_OP2_MIN 4
674 #define ALU_OP2_MAX_DX10 5
675 #define ALU_OP2_MIN_DX10 6
676 #define ALU_OP2_SETE 7
677 #define ALU_OP2_SETGT 8
678 #define ALU_OP2_SETGE 9
679 #define ALU_OP2_SETNE 10
680 #define ALU_OP2_SETE_DX10 11
681 #define ALU_OP2_SETGT_DX10 12
682 #define ALU_OP2_SETGE_DX10 13
683 #define ALU_OP2_SETNE_DX10 14
684 #define ALU_OP1_FRACT 15
685 #define ALU_OP1_TRUNC 16
686 #define ALU_OP1_CEIL 17
687 #define ALU_OP1_RNDNE 18
688 #define ALU_OP1_FLOOR 19
689 #define ALU_OP2_ASHR_INT 20
690 #define ALU_OP2_LSHR_INT 21
691 #define ALU_OP2_LSHL_INT 22
692 #define ALU_OP1_MOV 23
693 #define ALU_OP0_NOP 24
694 #define ALU_OP2_PRED_SETGT_UINT 25
695 #define ALU_OP2_PRED_SETGE_UINT 26
696 #define ALU_OP2_PRED_SETE 27
697 #define ALU_OP2_PRED_SETGT 28
698 #define ALU_OP2_PRED_SETGE 29
699 #define ALU_OP2_PRED_SETNE 30
700 #define ALU_OP1_PRED_SET_INV 31
701 #define ALU_OP2_PRED_SET_POP 32
702 #define ALU_OP0_PRED_SET_CLR 33
703 #define ALU_OP1_PRED_SET_RESTORE 34
704 #define ALU_OP2_PRED_SETE_PUSH 35
705 #define ALU_OP2_PRED_SETGT_PUSH 36
706 #define ALU_OP2_PRED_SETGE_PUSH 37
707 #define ALU_OP2_PRED_SETNE_PUSH 38
708 #define ALU_OP2_KILLE 39
709 #define ALU_OP2_KILLGT 40
710 #define ALU_OP2_KILLGE 41
711 #define ALU_OP2_KILLNE 42
712 #define ALU_OP2_AND_INT 43
713 #define ALU_OP2_OR_INT 44
714 #define ALU_OP2_XOR_INT 45
715 #define ALU_OP1_NOT_INT 46
716 #define ALU_OP2_ADD_INT 47
717 #define ALU_OP2_SUB_INT 48
718 #define ALU_OP2_MAX_INT 49
719 #define ALU_OP2_MIN_INT 50
720 #define ALU_OP2_MAX_UINT 51
721 #define ALU_OP2_MIN_UINT 52
722 #define ALU_OP2_SETE_INT 53
723 #define ALU_OP2_SETGT_INT 54
724 #define ALU_OP2_SETGE_INT 55
725 #define ALU_OP2_SETNE_INT 56
726 #define ALU_OP2_SETGT_UINT 57
727 #define ALU_OP2_SETGE_UINT 58
728 #define ALU_OP2_KILLGT_UINT 59
729 #define ALU_OP2_KILLGE_UINT 60
730 #define ALU_OP2_PRED_SETE_INT 61
731 #define ALU_OP2_PRED_SETGT_INT 62
732 #define ALU_OP2_PRED_SETGE_INT 63
733 #define ALU_OP2_PRED_SETNE_INT 64
734 #define ALU_OP2_KILLE_INT 65
735 #define ALU_OP2_KILLGT_INT 66
736 #define ALU_OP2_KILLGE_INT 67
737 #define ALU_OP2_KILLNE_INT 68
738 #define ALU_OP2_PRED_SETE_PUSH_INT 69
739 #define ALU_OP2_PRED_SETGT_PUSH_INT 70
740 #define ALU_OP2_PRED_SETGE_PUSH_INT 71
741 #define ALU_OP2_PRED_SETNE_PUSH_INT 72
742 #define ALU_OP2_PRED_SETLT_PUSH_INT 73
743 #define ALU_OP2_PRED_SETLE_PUSH_INT 74
744 #define ALU_OP1_FLT_TO_INT 75
745 #define ALU_OP1_BFREV_INT 76
746 #define ALU_OP2_ADDC_UINT 77
747 #define ALU_OP2_SUBB_UINT 78
748 #define ALU_OP0_GROUP_BARRIER 79
749 #define ALU_OP0_GROUP_SEQ_BEGIN 80
750 #define ALU_OP0_GROUP_SEQ_END 81
751 #define ALU_OP2_SET_MODE 82
752 #define ALU_OP0_SET_CF_IDX0 83
753 #define ALU_OP0_SET_CF_IDX1 84
754 #define ALU_OP2_SET_LDS_SIZE 85
755 #define ALU_OP2_MUL_INT24 86
756 #define ALU_OP2_MULHI_INT24 87
757 #define ALU_OP1_FLT_TO_INT_TRUNC 88
758 #define ALU_OP1_EXP_IEEE 89
759 #define ALU_OP1_LOG_CLAMPED 90
760 #define ALU_OP1_LOG_IEEE 91
761 #define ALU_OP1_RECIP_CLAMPED 92
762 #define ALU_OP1_RECIP_FF 93
763 #define ALU_OP1_RECIP_IEEE 94
764 #define ALU_OP1_RECIPSQRT_CLAMPED 95
765 #define ALU_OP1_RECIPSQRT_FF 96
766 #define ALU_OP1_RECIPSQRT_IEEE 97
767 #define ALU_OP1_SQRT_IEEE 98
768 #define ALU_OP1_SIN 99
769 #define ALU_OP1_COS 100
770 #define ALU_OP2_MULLO_INT 101
771 #define ALU_OP2_MULHI_INT 102
772 #define ALU_OP2_MULLO_UINT 103
773 #define ALU_OP2_MULHI_UINT 104
774 #define ALU_OP1_RECIP_INT 105
775 #define ALU_OP1_RECIP_UINT 106
776 #define ALU_OP2_RECIP_64 107
777 #define ALU_OP2_RECIP_CLAMPED_64 108
778 #define ALU_OP2_RECIPSQRT_64 109
779 #define ALU_OP2_RECIPSQRT_CLAMPED_64 110
780 #define ALU_OP2_SQRT_64 111
781 #define ALU_OP1_FLT_TO_UINT 112
782 #define ALU_OP1_INT_TO_FLT 113
783 #define ALU_OP1_UINT_TO_FLT 114
784 #define ALU_OP2_BFM_INT 115
785 #define ALU_OP1_FLT32_TO_FLT16 116
786 #define ALU_OP1_FLT16_TO_FLT32 117
787 #define ALU_OP1_UBYTE0_FLT 118
788 #define ALU_OP1_UBYTE1_FLT 119
789 #define ALU_OP1_UBYTE2_FLT 120
790 #define ALU_OP1_UBYTE3_FLT 121
791 #define ALU_OP1_BCNT_INT 122
792 #define ALU_OP1_FFBH_UINT 123
793 #define ALU_OP1_FFBL_INT 124
794 #define ALU_OP1_FFBH_INT 125
795 #define ALU_OP1_FLT_TO_UINT4 126
796 #define ALU_OP2_DOT_IEEE 127
797 #define ALU_OP1_FLT_TO_INT_RPI 128
798 #define ALU_OP1_FLT_TO_INT_FLOOR 129
799 #define ALU_OP2_MULHI_UINT24 130
800 #define ALU_OP1_MBCNT_32HI_INT 131
801 #define ALU_OP1_OFFSET_TO_FLT 132
802 #define ALU_OP2_MUL_UINT24 133
803 #define ALU_OP1_BCNT_ACCUM_PREV_INT 134
804 #define ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT 135
805 #define ALU_OP2_SETE_64 136
806 #define ALU_OP2_SETNE_64 137
807 #define ALU_OP2_SETGT_64 138
808 #define ALU_OP2_SETGE_64 139
809 #define ALU_OP2_MIN_64 140
810 #define ALU_OP2_MAX_64 141
811 #define ALU_OP2_DOT4 142
812 #define ALU_OP2_DOT4_IEEE 143
813 #define ALU_OP2_CUBE 144
814 #define ALU_OP1_MAX4 145
815 #define ALU_OP1_FREXP_64 146
816 #define ALU_OP2_LDEXP_64 147
817 #define ALU_OP1_FRACT_64 148
818 #define ALU_OP2_PRED_SETGT_64 149
819 #define ALU_OP2_PRED_SETE_64 150
820 #define ALU_OP2_PRED_SETGE_64 151
821 #define ALU_OP2_MUL_64 152
822 #define ALU_OP2_ADD_64 153
823 #define ALU_OP1_MOVA_INT 154
824 #define ALU_OP1_FLT64_TO_FLT32 155
825 #define ALU_OP1_FLT32_TO_FLT64 156
826 #define ALU_OP2_SAD_ACCUM_PREV_UINT 157
827 #define ALU_OP2_DOT 158
828 #define ALU_OP1_MUL_PREV 159
829 #define ALU_OP1_MUL_IEEE_PREV 160
830 #define ALU_OP1_ADD_PREV 161
831 #define ALU_OP2_MULADD_PREV 162
832 #define ALU_OP2_MULADD_IEEE_PREV 163
833 #define ALU_OP2_INTERP_XY 164
834 #define ALU_OP2_INTERP_ZW 165
835 #define ALU_OP2_INTERP_X 166
836 #define ALU_OP2_INTERP_Z 167
837 #define ALU_OP1_STORE_FLAGS 168
838 #define ALU_OP1_LOAD_STORE_FLAGS 169
839 #define ALU_OP2_LDS_1A 170
840 #define ALU_OP2_LDS_1A1D 171
841 #define ALU_OP2_LDS_2A 172
842 #define ALU_OP1_INTERP_LOAD_P0 173
843 #define ALU_OP1_INTERP_LOAD_P10 174
844 #define ALU_OP1_INTERP_LOAD_P20 175
845 #define ALU_OP3_BFE_UINT 176
846 #define ALU_OP3_BFE_INT 177
847 #define ALU_OP3_BFI_INT 178
848 #define ALU_OP3_FMA 179
849 #define ALU_OP3_MULADD_INT24 180
850 #define ALU_OP3_CNDNE_64 181
851 #define ALU_OP3_FMA_64 182
852 #define ALU_OP3_LERP_UINT 183
853 #define ALU_OP3_BIT_ALIGN_INT 184
854 #define ALU_OP3_BYTE_ALIGN_INT 185
855 #define ALU_OP3_SAD_ACCUM_UINT 186
856 #define ALU_OP3_SAD_ACCUM_HI_UINT 187
857 #define ALU_OP3_MULADD_UINT24 188
858 #define ALU_OP3_LDS_IDX_OP 189
859 #define ALU_OP3_MULADD 190
860 #define ALU_OP3_MULADD_M2 191
861 #define ALU_OP3_MULADD_M4 192
862 #define ALU_OP3_MULADD_D2 193
863 #define ALU_OP3_MULADD_IEEE 194
864 #define ALU_OP3_CNDE 195
865 #define ALU_OP3_CNDGT 196
866 #define ALU_OP3_CNDGE 197
867 #define ALU_OP3_CNDE_INT 198
868 #define ALU_OP3_CNDGT_INT 199
869 #define ALU_OP3_CNDGE_INT 200
870 #define ALU_OP3_MUL_LIT 201
871 #define ALU_OP1_MOVA 202
872 #define ALU_OP1_MOVA_FLOOR 203
873 #define ALU_OP1_MOVA_GPR_INT 204
874 #define ALU_OP3_MULADD_64 205
875 #define ALU_OP3_MULADD_64_M2 206
876 #define ALU_OP3_MULADD_64_M4 207
877 #define ALU_OP3_MULADD_64_D2 208
878 #define ALU_OP3_MUL_LIT_M2 209
879 #define ALU_OP3_MUL_LIT_M4 210
880 #define ALU_OP3_MUL_LIT_D2 211
881 #define ALU_OP3_MULADD_IEEE_M2 212
882 #define ALU_OP3_MULADD_IEEE_M4 213
883 #define ALU_OP3_MULADD_IEEE_D2 214
884
885 #define LDS_OP2_LDS_ADD 215
886 #define LDS_OP2_LDS_SUB 216
887 #define LDS_OP2_LDS_RSUB 217
888 #define LDS_OP2_LDS_INC 218
889 #define LDS_OP2_LDS_DEC 219
890 #define LDS_OP2_LDS_MIN_INT 220
891 #define LDS_OP2_LDS_MAX_INT 221
892 #define LDS_OP2_LDS_MIN_UINT 222
893 #define LDS_OP2_LDS_MAX_UINT 223
894 #define LDS_OP2_LDS_AND 224
895 #define LDS_OP2_LDS_OR 225
896 #define LDS_OP2_LDS_XOR 226
897 #define LDS_OP3_LDS_MSKOR 227
898 #define LDS_OP2_LDS_WRITE 228
899 #define LDS_OP3_LDS_WRITE_REL 229
900 #define LDS_OP3_LDS_WRITE2 230
901 #define LDS_OP3_LDS_CMP_STORE 231
902 #define LDS_OP3_LDS_CMP_STORE_SPF 232
903 #define LDS_OP2_LDS_BYTE_WRITE 233
904 #define LDS_OP2_LDS_SHORT_WRITE 234
905 #define LDS_OP2_LDS_ADD_RET 235
906 #define LDS_OP2_LDS_SUB_RET 236
907 #define LDS_OP2_LDS_RSUB_RET 237
908 #define LDS_OP2_LDS_INC_RET 238
909 #define LDS_OP2_LDS_DEC_RET 239
910 #define LDS_OP2_LDS_MIN_INT_RET 240
911 #define LDS_OP2_LDS_MAX_INT_RET 241
912 #define LDS_OP2_LDS_MIN_UINT_RET 242
913 #define LDS_OP2_LDS_MAX_UINT_RET 243
914 #define LDS_OP2_LDS_AND_RET 244
915 #define LDS_OP2_LDS_OR_RET 245
916 #define LDS_OP2_LDS_XOR_RET 246
917 #define LDS_OP3_LDS_MSKOR_RET 247
918 #define LDS_OP2_LDS_XCHG_RET 248
919 #define LDS_OP3_LDS_XCHG_REL_RET 249
920 #define LDS_OP3_LDS_XCHG2_RET 250
921 #define LDS_OP3_LDS_CMP_XCHG_RET 251
922 #define LDS_OP3_LDS_CMP_XCHG_SPF_RET 252
923 #define LDS_OP1_LDS_READ_RET 253
924 #define LDS_OP1_LDS_READ_REL_RET 254
925 #define LDS_OP2_LDS_READ2_RET 255
926 #define LDS_OP3_LDS_READWRITE_RET 256
927 #define LDS_OP1_LDS_BYTE_READ_RET 257
928 #define LDS_OP1_LDS_UBYTE_READ_RET 258
929 #define LDS_OP1_LDS_SHORT_READ_RET 259
930 #define LDS_OP1_LDS_USHORT_READ_RET 260
931
932 #define FETCH_OP_VFETCH 0
933 #define FETCH_OP_SEMFETCH 1
934 #define FETCH_OP_READ_SCRATCH 2
935 #define FETCH_OP_READ_REDUCT 3
936 #define FETCH_OP_READ_MEM 4
937 #define FETCH_OP_DS_LOCAL_WRITE 5
938 #define FETCH_OP_DS_LOCAL_READ 6
939 #define FETCH_OP_GDS_ADD 7
940 #define FETCH_OP_GDS_SUB 8
941 #define FETCH_OP_GDS_RSUB 9
942 #define FETCH_OP_GDS_INC 10
943 #define FETCH_OP_GDS_DEC 11
944 #define FETCH_OP_GDS_MIN_INT 12
945 #define FETCH_OP_GDS_MAX_INT 13
946 #define FETCH_OP_GDS_MIN_UINT 14
947 #define FETCH_OP_GDS_MAX_UINT 15
948 #define FETCH_OP_GDS_AND 16
949 #define FETCH_OP_GDS_OR 17
950 #define FETCH_OP_GDS_XOR 18
951 #define FETCH_OP_GDS_MSKOR 19
952 #define FETCH_OP_GDS_WRITE 20
953 #define FETCH_OP_GDS_WRITE_REL 21
954 #define FETCH_OP_GDS_WRITE2 22
955 #define FETCH_OP_GDS_CMP_STORE 23
956 #define FETCH_OP_GDS_CMP_STORE_SPF 24
957 #define FETCH_OP_GDS_BYTE_WRITE 25
958 #define FETCH_OP_GDS_SHORT_WRITE 26
959 #define FETCH_OP_GDS_ADD_RET 27
960 #define FETCH_OP_GDS_SUB_RET 28
961 #define FETCH_OP_GDS_RSUB_RET 29
962 #define FETCH_OP_GDS_INC_RET 30
963 #define FETCH_OP_GDS_DEC_RET 31
964 #define FETCH_OP_GDS_MIN_INT_RET 32
965 #define FETCH_OP_GDS_MAX_INT_RET 33
966 #define FETCH_OP_GDS_MIN_UINT_RET 34
967 #define FETCH_OP_GDS_MAX_UINT_RET 35
968 #define FETCH_OP_GDS_AND_RET 36
969 #define FETCH_OP_GDS_OR_RET 37
970 #define FETCH_OP_GDS_XOR_RET 38
971 #define FETCH_OP_GDS_MSKOR_RET 39
972 #define FETCH_OP_GDS_XCHG_RET 40
973 #define FETCH_OP_GDS_XCHG_REL_RET 41
974 #define FETCH_OP_GDS_XCHG2_RET 42
975 #define FETCH_OP_GDS_CMP_XCHG_RET 43
976 #define FETCH_OP_GDS_CMP_XCHG_SPF_RET 44
977 #define FETCH_OP_GDS_READ_RET 45
978 #define FETCH_OP_GDS_READ_REL_RET 46
979 #define FETCH_OP_GDS_READ2_RET 47
980 #define FETCH_OP_GDS_READWRITE_RET 48
981 #define FETCH_OP_GDS_BYTE_READ_RET 49
982 #define FETCH_OP_GDS_UBYTE_READ_RET 50
983 #define FETCH_OP_GDS_SHORT_READ_RET 51
984 #define FETCH_OP_GDS_USHORT_READ_RET 52
985 #define FETCH_OP_GDS_ATOMIC_ORDERED_ALLOC 53
986 #define FETCH_OP_TF_WRITE 54
987 #define FETCH_OP_DS_GLOBAL_WRITE 55
988 #define FETCH_OP_DS_GLOBAL_READ 56
989 #define FETCH_OP_LD 57
990 #define FETCH_OP_LDFPTR 58
991 #define FETCH_OP_GET_TEXTURE_RESINFO 59
992 #define FETCH_OP_GET_NUMBER_OF_SAMPLES 60
993 #define FETCH_OP_GET_LOD 61
994 #define FETCH_OP_GET_GRADIENTS_H 62
995 #define FETCH_OP_GET_GRADIENTS_V 63
996 #define FETCH_OP_GET_GRADIENTS_H_FINE 64
997 #define FETCH_OP_GET_GRADIENTS_V_FINE 65
998 #define FETCH_OP_GET_LERP 66
999 #define FETCH_OP_SET_TEXTURE_OFFSETS 67
1000 #define FETCH_OP_KEEP_GRADIENTS 68
1001 #define FETCH_OP_SET_GRADIENTS_H 69
1002 #define FETCH_OP_SET_GRADIENTS_V 70
1003 #define FETCH_OP_SET_GRADIENTS_H_COARSE 71
1004 #define FETCH_OP_SET_GRADIENTS_V_COARSE 72
1005 #define FETCH_OP_SET_GRADIENTS_H_PACKED_FINE 73
1006 #define FETCH_OP_SET_GRADIENTS_V_PACKED_FINE 74
1007 #define FETCH_OP_SET_GRADIENTS_H_PACKED_COARSE 75
1008 #define FETCH_OP_SET_GRADIENTS_V_PACKED_COARSE 76
1009 #define FETCH_OP_PASS 77
1010 #define FETCH_OP_PASS1 78
1011 #define FETCH_OP_PASS2 79
1012 #define FETCH_OP_PASS3 80
1013 #define FETCH_OP_SET_CUBEMAP_INDEX 81
1014 #define FETCH_OP_GET_BUFFER_RESINFO 82
1015 #define FETCH_OP_FETCH4 83
1016 #define FETCH_OP_SAMPLE 84
1017 #define FETCH_OP_SAMPLE_L 85
1018 #define FETCH_OP_SAMPLE_LB 86
1019 #define FETCH_OP_SAMPLE_LZ 87
1020 #define FETCH_OP_SAMPLE_G 88
1021 #define FETCH_OP_SAMPLE_G_L 89
1022 #define FETCH_OP_GATHER4 90
1023 #define FETCH_OP_SAMPLE_G_LB 91
1024 #define FETCH_OP_SAMPLE_G_LZ 92
1025 #define FETCH_OP_GATHER4_O 93
1026 #define FETCH_OP_SAMPLE_C 94
1027 #define FETCH_OP_SAMPLE_C_L 95
1028 #define FETCH_OP_SAMPLE_C_LB 96
1029 #define FETCH_OP_SAMPLE_C_LZ 97
1030 #define FETCH_OP_SAMPLE_C_G 98
1031 #define FETCH_OP_SAMPLE_C_G_L 99
1032 #define FETCH_OP_GATHER4_C 100
1033 #define FETCH_OP_SAMPLE_C_G_LB 101
1034 #define FETCH_OP_SAMPLE_C_G_LZ 102
1035 #define FETCH_OP_GATHER4_C_O 103
1036
1037 #define CF_OP_NOP 0
1038 #define CF_OP_TEX 1
1039 #define CF_OP_VTX 2
1040 #define CF_OP_VTX_TC 3
1041 #define CF_OP_GDS 4
1042 #define CF_OP_LOOP_START 5
1043 #define CF_OP_LOOP_END 6
1044 #define CF_OP_LOOP_START_DX10 7
1045 #define CF_OP_LOOP_START_NO_AL 8
1046 #define CF_OP_LOOP_CONTINUE 9
1047 #define CF_OP_LOOP_BREAK 10
1048 #define CF_OP_JUMP 11
1049 #define CF_OP_PUSH 12
1050 #define CF_OP_PUSH_ELSE 13
1051 #define CF_OP_ELSE 14
1052 #define CF_OP_POP 15
1053 #define CF_OP_POP_JUMP 16
1054 #define CF_OP_POP_PUSH 17
1055 #define CF_OP_POP_PUSH_ELSE 18
1056 #define CF_OP_CALL 19
1057 #define CF_OP_CALL_FS 20
1058 #define CF_OP_RET 21
1059 #define CF_OP_EMIT_VERTEX 22
1060 #define CF_OP_EMIT_CUT_VERTEX 23
1061 #define CF_OP_CUT_VERTEX 24
1062 #define CF_OP_KILL 25
1063 #define CF_OP_END_PROGRAM 26
1064 #define CF_OP_WAIT_ACK 27
1065 #define CF_OP_TEX_ACK 28
1066 #define CF_OP_VTX_ACK 29
1067 #define CF_OP_VTX_TC_ACK 30
1068 #define CF_OP_JUMPTABLE 31
1069 #define CF_OP_WAVE_SYNC 32
1070 #define CF_OP_HALT 33
1071 #define CF_OP_CF_END 34
1072 #define CF_OP_LDS_DEALLOC 35
1073 #define CF_OP_PUSH_WQM 36
1074 #define CF_OP_POP_WQM 37
1075 #define CF_OP_ELSE_WQM 38
1076 #define CF_OP_JUMP_ANY 39
1077 #define CF_OP_REACTIVATE 40
1078 #define CF_OP_REACTIVATE_WQM 41
1079 #define CF_OP_INTERRUPT 42
1080 #define CF_OP_INTERRUPT_AND_SLEEP 43
1081 #define CF_OP_SET_PRIORITY 44
1082 #define CF_OP_MEM_STREAM0_BUF0 45
1083 #define CF_OP_MEM_STREAM0_BUF1 46
1084 #define CF_OP_MEM_STREAM0_BUF2 47
1085 #define CF_OP_MEM_STREAM0_BUF3 48
1086 #define CF_OP_MEM_STREAM1_BUF0 49
1087 #define CF_OP_MEM_STREAM1_BUF1 50
1088 #define CF_OP_MEM_STREAM1_BUF2 51
1089 #define CF_OP_MEM_STREAM1_BUF3 52
1090 #define CF_OP_MEM_STREAM2_BUF0 53
1091 #define CF_OP_MEM_STREAM2_BUF1 54
1092 #define CF_OP_MEM_STREAM2_BUF2 55
1093 #define CF_OP_MEM_STREAM2_BUF3 56
1094 #define CF_OP_MEM_STREAM3_BUF0 57
1095 #define CF_OP_MEM_STREAM3_BUF1 58
1096 #define CF_OP_MEM_STREAM3_BUF2 59
1097 #define CF_OP_MEM_STREAM3_BUF3 60
1098 #define CF_OP_MEM_STREAM0 61
1099 #define CF_OP_MEM_STREAM1 62
1100 #define CF_OP_MEM_STREAM2 63
1101 #define CF_OP_MEM_STREAM3 64
1102 #define CF_OP_MEM_SCRATCH 65
1103 #define CF_OP_MEM_REDUCT 66
1104 #define CF_OP_MEM_RING 67
1105 #define CF_OP_EXPORT 68
1106 #define CF_OP_EXPORT_DONE 69
1107 #define CF_OP_MEM_EXPORT 70
1108 #define CF_OP_MEM_RAT 71
1109 #define CF_OP_MEM_RAT_NOCACHE 72
1110 #define CF_OP_MEM_RING1 73
1111 #define CF_OP_MEM_RING2 74
1112 #define CF_OP_MEM_RING3 75
1113 #define CF_OP_MEM_MEM_COMBINED 76
1114 #define CF_OP_MEM_RAT_COMBINED_NOCACHE 77
1115 #define CF_OP_MEM_RAT_COMBINED 78
1116 #define CF_OP_EXPORT_DONE_END 79
1117 #define CF_OP_ALU 80
1118 #define CF_OP_ALU_PUSH_BEFORE 81
1119 #define CF_OP_ALU_POP_AFTER 82
1120 #define CF_OP_ALU_POP2_AFTER 83
1121 #define CF_OP_ALU_EXT 84
1122 #define CF_OP_ALU_CONTINUE 85
1123 #define CF_OP_ALU_BREAK 86
1124 #define CF_OP_ALU_ELSE_AFTER 87
1125
1126 /* CF_NATIVE means that r600_bytecode_cf contains pre-encoded native data */
1127 #define CF_NATIVE 88
1128
1129 enum r600_chip_class {
1130 ISA_CC_R600,
1131 ISA_CC_R700,
1132 ISA_CC_EVERGREEN,
1133 ISA_CC_CAYMAN
1134 };
1135
1136 struct r600_isa {
1137 enum r600_chip_class hw_class;
1138
1139 /* these arrays provide reverse mapping - opcode => table_index,
1140 * typically we don't need such lookup, unless we are decoding the native
1141 * bytecode (e.g. when reading the bytestream from llvm backend) */
1142 unsigned *alu_op2_map;
1143 unsigned *alu_op3_map;
1144 unsigned *fetch_map;
1145 unsigned *cf_map;
1146 };
1147
1148 struct r600_context;
1149
1150 int r600_isa_init(struct r600_context *ctx, struct r600_isa *isa);
1151 int r600_isa_destroy(struct r600_isa *isa);
1152
1153 #define TABLE_SIZE(t) (sizeof(t)/sizeof(t[0]))
1154
1155 static inline const struct alu_op_info *
1156 r600_isa_alu(unsigned op) {
1157 assert (op < TABLE_SIZE(alu_op_table));
1158 return &alu_op_table[op];
1159 }
1160
1161 static inline const struct fetch_op_info *
1162 r600_isa_fetch(unsigned op) {
1163 assert (op < TABLE_SIZE(fetch_op_table));
1164 return &fetch_op_table[op];
1165 }
1166
1167 static inline const struct cf_op_info *
1168 r600_isa_cf(unsigned op) {
1169 assert (op < TABLE_SIZE(cf_op_table));
1170 return &cf_op_table[op];
1171 }
1172
1173 static inline unsigned
1174 r600_isa_alu_opcode(enum r600_chip_class chip_class, unsigned op) {
1175 int opc = r600_isa_alu(op)->opcode[chip_class >> 1];
1176 assert(opc != -1);
1177 return opc;
1178 }
1179
1180 static inline unsigned
1181 r600_isa_alu_slots(enum r600_chip_class chip_class, unsigned op) {
1182 unsigned slots = r600_isa_alu(op)->slots[chip_class];
1183 assert(slots != 0);
1184 return slots;
1185 }
1186
1187 static inline unsigned
1188 r600_isa_fetch_opcode(enum r600_chip_class chip_class, unsigned op) {
1189 int opc = r600_isa_fetch(op)->opcode[chip_class];
1190 assert(opc != -1);
1191 return opc;
1192 }
1193
1194 static inline unsigned
1195 r600_isa_cf_opcode(enum r600_chip_class chip_class, unsigned op) {
1196 int opc = r600_isa_cf(op)->opcode[chip_class];
1197 assert(opc != -1);
1198 return opc;
1199 }
1200
1201 static inline unsigned
1202 r600_isa_alu_by_opcode(struct r600_isa* isa, unsigned opcode, unsigned is_op3) {
1203 unsigned op;
1204 if (is_op3) {
1205 assert(isa->alu_op3_map);
1206 op = isa->alu_op3_map[opcode];
1207 } else {
1208 assert(isa->alu_op2_map);
1209 op = isa->alu_op2_map[opcode];
1210 }
1211 assert(op);
1212 return op - 1;
1213 }
1214
1215 static inline unsigned
1216 r600_isa_fetch_by_opcode(struct r600_isa* isa, unsigned opcode) {
1217 unsigned op;
1218 assert(isa->fetch_map);
1219 op = isa->fetch_map[opcode];
1220 assert(op);
1221 return op - 1;
1222 }
1223
1224 static inline unsigned
1225 r600_isa_cf_by_opcode(struct r600_isa* isa, unsigned opcode, unsigned is_alu) {
1226 unsigned op;
1227 assert(isa->cf_map);
1228 /* using offset for CF_ALU_xxx opcodes because they overlap with other
1229 * CF opcodes (they use different encoding in hw) */
1230 op = isa->cf_map[is_alu ? opcode + 0x80 : opcode];
1231 assert(op);
1232 return op - 1;
1233 }
1234
1235 #endif /* R600_ISA_H_ */