src/gallium/drivers/r600/r600_llvm.c

   1 #include "r600_llvm.h"
   2
   3 #include "gallivm/lp_bld_const.h"
   4 #include "gallivm/lp_bld_intr.h"
   5 #include "gallivm/lp_bld_gather.h"
   6 #include "tgsi/tgsi_parse.h"
   7 #include "util/u_double_list.h"
   8 #include "util/u_memory.h"
   9
  10 #include "r600.h"
  11 #include "r600_asm.h"
  12 #include "r600_opcodes.h"
  13 #include "r600_shader.h"
  14 #include "radeon_llvm.h"
  15 #include "radeon_llvm_emit.h"
  16
  17 #include <stdio.h>
  18
  19 static LLVMValueRef llvm_fetch_const(
  20         struct lp_build_tgsi_context * bld_base,
  21         const struct tgsi_full_src_register *reg,
  22         enum tgsi_opcode_type type,
  23         unsigned swizzle)
  24 {
  25         LLVMValueRef idx = lp_build_const_int32(bld_base->base.gallivm,
  26                         radeon_llvm_reg_index_soa(reg->Register.Index, swizzle));
  27         LLVMValueRef cval = build_intrinsic(bld_base->base.gallivm->builder,
  28                 "llvm.AMDGPU.load.const", bld_base->base.elem_type,
  29                 &idx, 1, LLVMReadNoneAttribute);
  30
  31         return bitcast(bld_base, type, cval);
  32 }
  33
  34 static void llvm_load_system_value(
  35                 struct radeon_llvm_context * ctx,
  36                 unsigned index,
  37                 const struct tgsi_full_declaration *decl)
  38 {
  39         unsigned chan;
  40
  41         switch (decl->Semantic.Name) {
  42         case TGSI_SEMANTIC_INSTANCEID: chan = 3; break;
  43         case TGSI_SEMANTIC_VERTEXID: chan = 0; break;
  44         default: assert(!"unknown system value");
  45         }
  46
  47         LLVMValueRef reg = lp_build_const_int32(
  48                         ctx->soa.bld_base.base.gallivm, chan);
  49         ctx->system_values[index] = build_intrinsic(
  50                         ctx->soa.bld_base.base.gallivm->builder,
  51                         "llvm.R600.load.input",
  52                         ctx->soa.bld_base.base.elem_type, &reg, 1,
  53                         LLVMReadNoneAttribute);
  54 }
  55
  56 static LLVMValueRef llvm_fetch_system_value(
  57                 struct lp_build_tgsi_context * bld_base,
  58                 const struct tgsi_full_src_register *reg,
  59                 enum tgsi_opcode_type type,
  60                 unsigned swizzle)
  61 {
  62         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
  63         LLVMValueRef cval = ctx->system_values[reg->Register.Index];
  64         return bitcast(bld_base, type, cval);
  65 }
  66
  67 static void llvm_load_input(
  68         struct radeon_llvm_context * ctx,
  69         unsigned input_index,
  70         const struct tgsi_full_declaration *decl)
  71 {
  72         unsigned chan;
  73
  74         for (chan = 0; chan < 4; chan++) {
  75                 unsigned soa_index = radeon_llvm_reg_index_soa(input_index,
  76                                                                 chan);
  77
  78                 /* The * 4 is assuming that we are in soa mode. */
  79                 LLVMValueRef reg = lp_build_const_int32(
  80                                 ctx->soa.bld_base.base.gallivm,
  81                                 soa_index + (ctx->reserved_reg_count * 4));
  82                 ctx->inputs[soa_index] = build_intrinsic(
  83                                 ctx->soa.bld_base.base.gallivm->builder,
  84                                 "llvm.R600.load.input",
  85                                 ctx->soa.bld_base.base.elem_type, &reg, 1,
  86                                 LLVMReadNoneAttribute);
  87         }
  88 }
  89
  90 static void llvm_emit_prologue(struct lp_build_tgsi_context * bld_base)
  91 {
  92         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
  93         struct lp_build_context * base = &bld_base->base;
  94         unsigned i;
  95
  96         /* Reserve special input registers */
  97         for (i = 0; i < ctx->reserved_reg_count; i++) {
  98                 unsigned chan;
  99                 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 100                         LLVMValueRef reg_index = lp_build_const_int32(
 101                                         base->gallivm,
 102                                         radeon_llvm_reg_index_soa(i, chan));
 103                         lp_build_intrinsic_unary(base->gallivm->builder,
 104                                 "llvm.AMDGPU.reserve.reg",
 105                                 LLVMVoidTypeInContext(base->gallivm->context),
 106                                 reg_index);
 107                 }
 108         }
 109 }
 110
 111 static void llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
 112 {
 113         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 114         struct lp_build_context * base = &bld_base->base;
 115         unsigned i;
 116
 117         /* Add the necessary export instructions */
 118         for (i = 0; i < ctx->output_reg_count; i++) {
 119                 unsigned chan;
 120                 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 121                         LLVMValueRef output;
 122                         unsigned adjusted_reg_idx = i +
 123                                         ctx->reserved_reg_count;
 124                         LLVMValueRef reg_index = lp_build_const_int32(
 125                                 base->gallivm,
 126                                 radeon_llvm_reg_index_soa(adjusted_reg_idx, chan));
 127
 128                         output = LLVMBuildLoad(base->gallivm->builder,
 129                                 ctx->soa.outputs[i][chan], "");
 130
 131                         lp_build_intrinsic_binary(
 132                                 base->gallivm->builder,
 133                                 "llvm.AMDGPU.store.output",
 134                                 LLVMVoidTypeInContext(base->gallivm->context),
 135                                 output, reg_index);
 136                 }
 137         }
 138 }
 139
 140 static void llvm_emit_tex(
 141         const struct lp_build_tgsi_action * action,
 142         struct lp_build_tgsi_context * bld_base,
 143         struct lp_build_emit_data * emit_data)
 144 {
 145         struct gallivm_state * gallivm = bld_base->base.gallivm;
 146         LLVMValueRef args[6];
 147         unsigned c;
 148
 149         assert(emit_data->arg_count + 2 <= Elements(args));
 150
 151         for (c = 0; c < emit_data->arg_count; ++c)
 152                 args[c] = emit_data->args[c];
 153
 154         args[c++] = lp_build_const_int32(gallivm,
 155                                         emit_data->inst->Src[1].Register.Index);
 156         args[c++] = lp_build_const_int32(gallivm,
 157                                         emit_data->inst->Texture.Texture);
 158
 159         emit_data->output[0] = build_intrinsic(gallivm->builder,
 160                                         action->intr_name,
 161                                         emit_data->dst_type, args, c, LLVMReadNoneAttribute);
 162 }
 163
 164 static void dp_fetch_args(
 165         struct lp_build_tgsi_context * bld_base,
 166         struct lp_build_emit_data * emit_data)
 167 {
 168         struct lp_build_context * base = &bld_base->base;
 169         unsigned chan;
 170         LLVMValueRef elements[2][4];
 171         unsigned opcode = emit_data->inst->Instruction.Opcode;
 172         unsigned dp_components = (opcode == TGSI_OPCODE_DP2 ? 2 :
 173                                         (opcode == TGSI_OPCODE_DP3 ? 3 : 4));
 174         for (chan = 0 ; chan < dp_components; chan++) {
 175                 elements[0][chan] = lp_build_emit_fetch(bld_base,
 176                                                 emit_data->inst, 0, chan);
 177                 elements[1][chan] = lp_build_emit_fetch(bld_base,
 178                                                 emit_data->inst, 1, chan);
 179         }
 180
 181         for ( ; chan < 4; chan++) {
 182                 elements[0][chan] = base->zero;
 183                 elements[1][chan] = base->zero;
 184         }
 185
 186          /* Fix up for DPH */
 187         if (opcode == TGSI_OPCODE_DPH) {
 188                 elements[0][TGSI_CHAN_W] = base->one;
 189         }
 190
 191         emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
 192                                                         elements[0], 4);
 193         emit_data->args[1] = lp_build_gather_values(bld_base->base.gallivm,
 194                                                         elements[1], 4);
 195         emit_data->arg_count = 2;
 196
 197         emit_data->dst_type = base->elem_type;
 198 }
 199
 200 static struct lp_build_tgsi_action dot_action = {
 201         .fetch_args = dp_fetch_args,
 202         .emit = build_tgsi_intrinsic_nomem,
 203         .intr_name = "llvm.AMDGPU.dp4"
 204 };
 205
 206
 207
 208 LLVMModuleRef r600_tgsi_llvm(
 209         struct radeon_llvm_context * ctx,
 210         const struct tgsi_token * tokens)
 211 {
 212         struct tgsi_shader_info shader_info;
 213         struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
 214         radeon_llvm_context_init(ctx);
 215         tgsi_scan_shader(tokens, &shader_info);
 216
 217         bld_base->info = &shader_info;
 218         bld_base->userdata = ctx;
 219         bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = llvm_fetch_const;
 220         bld_base->emit_fetch_funcs[TGSI_FILE_SYSTEM_VALUE] = llvm_fetch_system_value;
 221         bld_base->emit_prologue = llvm_emit_prologue;
 222         bld_base->emit_epilogue = llvm_emit_epilogue;
 223         ctx->userdata = ctx;
 224         ctx->load_input = llvm_load_input;
 225         ctx->load_system_value = llvm_load_system_value;
 226
 227         bld_base->op_actions[TGSI_OPCODE_DP2] = dot_action;
 228         bld_base->op_actions[TGSI_OPCODE_DP3] = dot_action;
 229         bld_base->op_actions[TGSI_OPCODE_DP4] = dot_action;
 230         bld_base->op_actions[TGSI_OPCODE_DPH] = dot_action;
 231         bld_base->op_actions[TGSI_OPCODE_DDX].emit = llvm_emit_tex;
 232         bld_base->op_actions[TGSI_OPCODE_DDY].emit = llvm_emit_tex;
 233         bld_base->op_actions[TGSI_OPCODE_TEX].emit = llvm_emit_tex;
 234         bld_base->op_actions[TGSI_OPCODE_TXB].emit = llvm_emit_tex;
 235         bld_base->op_actions[TGSI_OPCODE_TXD].emit = llvm_emit_tex;
 236         bld_base->op_actions[TGSI_OPCODE_TXL].emit = llvm_emit_tex;
 237         bld_base->op_actions[TGSI_OPCODE_TXF].emit = llvm_emit_tex;
 238         bld_base->op_actions[TGSI_OPCODE_TXQ].emit = llvm_emit_tex;
 239         bld_base->op_actions[TGSI_OPCODE_TXP].emit = llvm_emit_tex;
 240
 241         lp_build_tgsi_llvm(bld_base, tokens);
 242
 243         radeon_llvm_finalize_module(ctx);
 244
 245         return ctx->gallivm.module;
 246 }
 247
 248 const char * r600_llvm_gpu_string(enum radeon_family family)
 249 {
 250         const char * gpu_family;
 251
 252         switch (family) {
 253         case CHIP_R600:
 254         case CHIP_RV610:
 255         case CHIP_RV630:
 256         case CHIP_RV620:
 257         case CHIP_RV635:
 258         case CHIP_RS780:
 259         case CHIP_RS880:
 260         case CHIP_RV710:
 261                 gpu_family = "rv710";
 262                 break;
 263         case CHIP_RV730:
 264                 gpu_family = "rv730";
 265                 break;
 266         case CHIP_RV670:
 267         case CHIP_RV740:
 268         case CHIP_RV770:
 269                 gpu_family = "rv770";
 270                 break;
 271         case CHIP_PALM:
 272         case CHIP_CEDAR:
 273                 gpu_family = "cedar";
 274                 break;
 275         case CHIP_SUMO:
 276         case CHIP_SUMO2:
 277         case CHIP_REDWOOD:
 278                 gpu_family = "redwood";
 279                 break;
 280         case CHIP_JUNIPER:
 281                 gpu_family = "juniper";
 282                 break;
 283         case CHIP_HEMLOCK:
 284         case CHIP_CYPRESS:
 285                 gpu_family = "cypress";
 286                 break;
 287         case CHIP_BARTS:
 288                 gpu_family = "barts";
 289                 break;
 290         case CHIP_TURKS:
 291                 gpu_family = "turks";
 292                 break;
 293         case CHIP_CAICOS:
 294                 gpu_family = "caicos";
 295                 break;
 296         case CHIP_CAYMAN:
 297         case CHIP_ARUBA:
 298                 gpu_family = "cayman";
 299                 break;
 300         default:
 301                 gpu_family = "";
 302                 fprintf(stderr, "Chip not supported by r600 llvm "
 303                         "backend, please file a bug at bugs.freedesktop.org\n");
 304                 break;
 305         }
 306         return gpu_family;
 307 }
 308
 309 unsigned r600_llvm_compile(
 310         LLVMModuleRef mod,
 311         unsigned char ** inst_bytes,
 312         unsigned * inst_byte_count,
 313         enum radeon_family family,
 314         unsigned dump)
 315 {
 316         const char * gpu_family = r600_llvm_gpu_string(family);
 317         return radeon_llvm_compile(mod, inst_bytes, inst_byte_count,
 318                                                         gpu_family, dump);
 319 }