3 #include "gallivm/lp_bld_const.h"
4 #include "gallivm/lp_bld_intr.h"
5 #include "gallivm/lp_bld_gather.h"
6 #include "tgsi/tgsi_parse.h"
7 #include "util/u_double_list.h"
8 #include "util/u_memory.h"
12 #include "r600_opcodes.h"
13 #include "r600_shader.h"
14 #include "r600_pipe.h"
15 #include "radeon_llvm.h"
16 #include "radeon_llvm_emit.h"
20 #if defined R600_USE_LLVM || defined HAVE_OPENCL
22 #define CONSTANT_BUFFER_0_ADDR_SPACE 8
23 #define CONSTANT_BUFFER_1_ADDR_SPACE (CONSTANT_BUFFER_0_ADDR_SPACE + R600_UCP_CONST_BUFFER)
25 static LLVMValueRef
llvm_fetch_const(
26 struct lp_build_tgsi_context
* bld_base
,
27 const struct tgsi_full_src_register
*reg
,
28 enum tgsi_opcode_type type
,
31 LLVMValueRef offset
[2] = {
32 LLVMConstInt(LLVMInt64TypeInContext(bld_base
->base
.gallivm
->context
), 0, false),
33 lp_build_const_int32(bld_base
->base
.gallivm
, reg
->Register
.Index
)
35 if (reg
->Register
.Indirect
) {
36 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
37 LLVMValueRef index
= LLVMBuildLoad(bld_base
->base
.gallivm
->builder
, bld
->addr
[reg
->Indirect
.Index
][reg
->Indirect
.Swizzle
], "");
38 offset
[1] = LLVMBuildAdd(bld_base
->base
.gallivm
->builder
, offset
[1], index
, "");
40 unsigned ConstantAddressSpace
= CONSTANT_BUFFER_0_ADDR_SPACE
;
41 if (reg
->Register
.Dimension
) {
42 ConstantAddressSpace
+= reg
->Dimension
.Index
;
44 LLVMTypeRef const_ptr_type
= LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base
->base
.elem_type
, 4), 1024),
45 ConstantAddressSpace
);
46 LLVMValueRef const_ptr
= LLVMBuildIntToPtr(bld_base
->base
.gallivm
->builder
, lp_build_const_int32(bld_base
->base
.gallivm
, 0), const_ptr_type
, "");
47 LLVMValueRef ptr
= LLVMBuildGEP(bld_base
->base
.gallivm
->builder
, const_ptr
, offset
, 2, "");
48 LLVMValueRef cvecval
= LLVMBuildLoad(bld_base
->base
.gallivm
->builder
, ptr
, "");
49 LLVMValueRef cval
= LLVMBuildExtractElement(bld_base
->base
.gallivm
->builder
, cvecval
, lp_build_const_int32(bld_base
->base
.gallivm
, swizzle
), "");
50 return bitcast(bld_base
, type
, cval
);
53 static void llvm_load_system_value(
54 struct radeon_llvm_context
* ctx
,
56 const struct tgsi_full_declaration
*decl
)
60 switch (decl
->Semantic
.Name
) {
61 case TGSI_SEMANTIC_INSTANCEID
: chan
= 3; break;
62 case TGSI_SEMANTIC_VERTEXID
: chan
= 0; break;
63 default: assert(!"unknown system value");
66 LLVMValueRef reg
= lp_build_const_int32(
67 ctx
->soa
.bld_base
.base
.gallivm
, chan
);
68 ctx
->system_values
[index
] = build_intrinsic(
69 ctx
->soa
.bld_base
.base
.gallivm
->builder
,
70 "llvm.R600.load.input",
71 ctx
->soa
.bld_base
.base
.elem_type
, ®
, 1,
72 LLVMReadNoneAttribute
);
75 static LLVMValueRef
llvm_fetch_system_value(
76 struct lp_build_tgsi_context
* bld_base
,
77 const struct tgsi_full_src_register
*reg
,
78 enum tgsi_opcode_type type
,
81 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
82 LLVMValueRef cval
= ctx
->system_values
[reg
->Register
.Index
];
83 return bitcast(bld_base
, type
, cval
);
87 llvm_load_input_helper(
88 struct radeon_llvm_context
* ctx
,
89 unsigned idx
, int interp
, int ij_index
)
91 const struct lp_build_context
* bb
= &ctx
->soa
.bld_base
.base
;
94 const char * intrinsic
;
96 arg
[0] = lp_build_const_int32(bb
->gallivm
, idx
);
99 intrinsic
= "llvm.R600.interp.input";
100 arg
[1] = lp_build_const_int32(bb
->gallivm
, ij_index
);
103 intrinsic
= "llvm.R600.load.input";
107 return build_intrinsic(bb
->gallivm
->builder
, intrinsic
,
108 bb
->elem_type
, &arg
[0], arg_count
, LLVMReadNoneAttribute
);
112 llvm_face_select_helper(
113 struct radeon_llvm_context
* ctx
,
114 unsigned face_loc
, LLVMValueRef front_color
, LLVMValueRef back_color
)
116 const struct lp_build_context
* bb
= &ctx
->soa
.bld_base
.base
;
117 LLVMValueRef face
= llvm_load_input_helper(ctx
, face_loc
, 0, 0);
118 LLVMValueRef is_front
= LLVMBuildFCmp(
119 bb
->gallivm
->builder
, LLVMRealUGT
, face
,
120 lp_build_const_float(bb
->gallivm
, 0.0f
), "");
121 return LLVMBuildSelect(bb
->gallivm
->builder
, is_front
,
122 front_color
, back_color
, "");
125 static void llvm_load_input(
126 struct radeon_llvm_context
* ctx
,
127 unsigned input_index
,
128 const struct tgsi_full_declaration
*decl
)
130 const struct r600_shader_io
* input
= &ctx
->r600_inputs
[input_index
];
134 int two_side
= (ctx
->two_side
&& input
->name
== TGSI_SEMANTIC_COLOR
);
137 if (ctx
->chip_class
>= EVERGREEN
&& ctx
->type
== TGSI_PROCESSOR_FRAGMENT
&&
140 ij_index
= (input
->interpolate
> 0) ? input
->ij_index
: -1;
143 for (chan
= 0; chan
< 4; chan
++) {
144 unsigned soa_index
= radeon_llvm_reg_index_soa(input_index
, chan
);
148 loc
= 4 * input
->lds_pos
+ chan
;
150 if (input
->name
== TGSI_SEMANTIC_FACE
)
151 loc
= 4 * ctx
->face_gpr
;
153 loc
= 4 * input
->gpr
+ chan
;
156 v
= llvm_load_input_helper(ctx
, loc
, interp
, ij_index
);
159 struct r600_shader_io
* back_input
=
160 &ctx
->r600_inputs
[input
->back_color_input
];
161 int back_loc
= interp
? back_input
->lds_pos
: back_input
->gpr
;
164 back_loc
= 4 * back_loc
+ chan
;
165 v2
= llvm_load_input_helper(ctx
, back_loc
, interp
, ij_index
);
166 v
= llvm_face_select_helper(ctx
, 4 * ctx
->face_gpr
, v
, v2
);
167 } else if (input
->name
== TGSI_SEMANTIC_POSITION
&&
168 ctx
->type
== TGSI_PROCESSOR_FRAGMENT
&& chan
== 3) {
169 /* RCP for fragcoord.w */
170 v
= LLVMBuildFDiv(ctx
->gallivm
.builder
,
171 lp_build_const_float(&(ctx
->gallivm
), 1.0f
),
175 ctx
->inputs
[soa_index
] = v
;
179 static void llvm_emit_prologue(struct lp_build_tgsi_context
* bld_base
)
181 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
185 static void llvm_emit_epilogue(struct lp_build_tgsi_context
* bld_base
)
187 struct radeon_llvm_context
* ctx
= radeon_llvm_context(bld_base
);
188 struct lp_build_context
* base
= &bld_base
->base
;
189 struct pipe_stream_output_info
* so
= ctx
->stream_outputs
;
191 unsigned next_pos
= 60;
192 unsigned next_param
= 0;
194 unsigned color_count
= 0;
195 boolean has_color
= false;
197 if (ctx
->type
== TGSI_PROCESSOR_VERTEX
&& so
->num_outputs
) {
198 for (i
= 0; i
< so
->num_outputs
; i
++) {
199 unsigned register_index
= so
->output
[i
].register_index
;
200 unsigned start_component
= so
->output
[i
].start_component
;
201 unsigned num_components
= so
->output
[i
].num_components
;
202 unsigned dst_offset
= so
->output
[i
].dst_offset
;
204 LLVMValueRef elements
[4];
205 if (dst_offset
< start_component
) {
206 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
207 elements
[chan
] = LLVMBuildLoad(base
->gallivm
->builder
,
208 ctx
->soa
.outputs
[register_index
][(chan
+ start_component
) % TGSI_NUM_CHANNELS
], "");
212 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
213 elements
[chan
] = LLVMBuildLoad(base
->gallivm
->builder
,
214 ctx
->soa
.outputs
[register_index
][chan
], "");
217 LLVMValueRef output
= lp_build_gather_values(base
->gallivm
, elements
, 4);
218 LLVMValueRef args
[4];
220 args
[1] = lp_build_const_int32(base
->gallivm
, dst_offset
- start_component
);
221 args
[2] = lp_build_const_int32(base
->gallivm
, so
->output
[i
].output_buffer
);
222 args
[3] = lp_build_const_int32(base
->gallivm
, ((1 << num_components
) - 1) << start_component
);
223 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.R600.store.stream.output",
224 LLVMVoidTypeInContext(base
->gallivm
->context
), args
, 4);
228 /* Add the necessary export instructions */
229 for (i
= 0; i
< ctx
->output_reg_count
; i
++) {
231 LLVMValueRef elements
[4];
232 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
233 elements
[chan
] = LLVMBuildLoad(base
->gallivm
->builder
,
234 ctx
->soa
.outputs
[i
][chan
], "");
236 if (ctx
->alpha_to_one
&& ctx
->type
== TGSI_PROCESSOR_FRAGMENT
&& ctx
->r600_outputs
[i
].name
== TGSI_SEMANTIC_COLOR
)
237 elements
[3] = lp_build_const_float(base
->gallivm
, 1.0f
);
238 LLVMValueRef output
= lp_build_gather_values(base
->gallivm
, elements
, 4);
240 if (ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
241 switch (ctx
->r600_outputs
[i
].name
) {
242 case TGSI_SEMANTIC_POSITION
:
243 case TGSI_SEMANTIC_PSIZE
: {
244 LLVMValueRef args
[3];
246 args
[1] = lp_build_const_int32(base
->gallivm
, next_pos
++);
247 args
[2] = lp_build_const_int32(base
->gallivm
, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
);
249 base
->gallivm
->builder
,
250 "llvm.R600.store.swizzle",
251 LLVMVoidTypeInContext(base
->gallivm
->context
),
255 case TGSI_SEMANTIC_CLIPVERTEX
: {
256 LLVMValueRef args
[3];
258 unsigned base_vector_chan
;
259 LLVMValueRef adjusted_elements
[4];
260 for (reg_index
= 0; reg_index
< 2; reg_index
++) {
261 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
262 LLVMValueRef offset
[2] = {
263 LLVMConstInt(LLVMInt64TypeInContext(bld_base
->base
.gallivm
->context
), 0, false),
264 lp_build_const_int32(bld_base
->base
.gallivm
, reg_index
* 4 + chan
)
266 LLVMTypeRef const_ptr_type
= LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base
->base
.elem_type
, 4), 1024), CONSTANT_BUFFER_1_ADDR_SPACE
);
267 LLVMValueRef const_ptr
= LLVMBuildIntToPtr(bld_base
->base
.gallivm
->builder
, lp_build_const_int32(bld_base
->base
.gallivm
, 0), const_ptr_type
, "");
268 LLVMValueRef ptr
= LLVMBuildGEP(bld_base
->base
.gallivm
->builder
, const_ptr
, offset
, 2, "");
269 LLVMValueRef base_vector
= LLVMBuildLoad(bld_base
->base
.gallivm
->builder
, ptr
, "");
271 args
[1] = base_vector
;
272 adjusted_elements
[chan
] = build_intrinsic(base
->gallivm
->builder
,
273 "llvm.AMDGPU.dp4", bld_base
->base
.elem_type
,
274 args
, 2, LLVMReadNoneAttribute
);
276 args
[0] = lp_build_gather_values(base
->gallivm
,
277 adjusted_elements
, 4);
278 args
[1] = lp_build_const_int32(base
->gallivm
, next_pos
++);
279 args
[2] = lp_build_const_int32(base
->gallivm
, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
);
281 base
->gallivm
->builder
,
282 "llvm.R600.store.swizzle",
283 LLVMVoidTypeInContext(base
->gallivm
->context
),
288 case TGSI_SEMANTIC_CLIPDIST
: {
289 LLVMValueRef args
[3];
291 args
[1] = lp_build_const_int32(base
->gallivm
, next_pos
++);
292 args
[2] = lp_build_const_int32(base
->gallivm
, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
);
294 base
->gallivm
->builder
,
295 "llvm.R600.store.swizzle",
296 LLVMVoidTypeInContext(base
->gallivm
->context
),
298 args
[1] = lp_build_const_int32(base
->gallivm
, next_param
++);
299 args
[2] = lp_build_const_int32(base
->gallivm
, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
);
301 base
->gallivm
->builder
,
302 "llvm.R600.store.swizzle",
303 LLVMVoidTypeInContext(base
->gallivm
->context
),
307 case TGSI_SEMANTIC_FOG
: {
308 elements
[0] = LLVMBuildLoad(base
->gallivm
->builder
,
309 ctx
->soa
.outputs
[i
][0], "");
310 elements
[1] = elements
[2] = lp_build_const_float(base
->gallivm
, 0.0f
);
311 elements
[3] = lp_build_const_float(base
->gallivm
, 1.0f
);
313 LLVMValueRef args
[3];
314 args
[0] = lp_build_gather_values(base
->gallivm
, elements
, 4);
315 args
[1] = lp_build_const_int32(base
->gallivm
, next_param
++);
316 args
[2] = lp_build_const_int32(base
->gallivm
, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
);
318 base
->gallivm
->builder
,
319 "llvm.R600.store.swizzle",
320 LLVMVoidTypeInContext(base
->gallivm
->context
),
325 LLVMValueRef args
[3];
327 args
[1] = lp_build_const_int32(base
->gallivm
, next_param
++);
328 args
[2] = lp_build_const_int32(base
->gallivm
, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
);
330 base
->gallivm
->builder
,
331 "llvm.R600.store.swizzle",
332 LLVMVoidTypeInContext(base
->gallivm
->context
),
337 } else if (ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
338 switch (ctx
->r600_outputs
[i
].name
) {
339 case TGSI_SEMANTIC_COLOR
:
341 if ( color_count
< ctx
->color_buffer_count
) {
342 LLVMValueRef args
[3];
344 if (ctx
->fs_color_all
) {
345 for (unsigned j
= 0; j
< ctx
->color_buffer_count
; j
++) {
346 args
[1] = lp_build_const_int32(base
->gallivm
, j
);
347 args
[2] = lp_build_const_int32(base
->gallivm
, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
);
349 base
->gallivm
->builder
,
350 "llvm.R600.store.swizzle",
351 LLVMVoidTypeInContext(base
->gallivm
->context
),
355 args
[1] = lp_build_const_int32(base
->gallivm
, color_count
++);
356 args
[2] = lp_build_const_int32(base
->gallivm
, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
);
358 base
->gallivm
->builder
,
359 "llvm.R600.store.swizzle",
360 LLVMVoidTypeInContext(base
->gallivm
->context
),
365 case TGSI_SEMANTIC_POSITION
:
366 lp_build_intrinsic_unary(
367 base
->gallivm
->builder
,
368 "llvm.R600.store.pixel.depth",
369 LLVMVoidTypeInContext(base
->gallivm
->context
),
370 LLVMBuildLoad(base
->gallivm
->builder
, ctx
->soa
.outputs
[i
][2], ""));
372 case TGSI_SEMANTIC_STENCIL
:
373 lp_build_intrinsic_unary(
374 base
->gallivm
->builder
,
375 "llvm.R600.store.pixel.stencil",
376 LLVMVoidTypeInContext(base
->gallivm
->context
),
377 LLVMBuildLoad(base
->gallivm
->builder
, ctx
->soa
.outputs
[i
][1], ""));
383 if (ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
385 lp_build_intrinsic_unary(base
->gallivm
->builder
, "llvm.R600.store.dummy",
386 LLVMVoidTypeInContext(base
->gallivm
->context
),
387 lp_build_const_int32(base
->gallivm
, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
));
389 if (!(next_pos
-60)) {
390 lp_build_intrinsic_unary(base
->gallivm
->builder
, "llvm.R600.store.dummy",
391 LLVMVoidTypeInContext(base
->gallivm
->context
),
392 lp_build_const_int32(base
->gallivm
, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
));
395 if (ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
397 lp_build_intrinsic_unary(base
->gallivm
->builder
, "llvm.R600.store.dummy",
398 LLVMVoidTypeInContext(base
->gallivm
->context
),
399 lp_build_const_int32(base
->gallivm
, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
));
405 static void llvm_emit_tex(
406 const struct lp_build_tgsi_action
* action
,
407 struct lp_build_tgsi_context
* bld_base
,
408 struct lp_build_emit_data
* emit_data
)
410 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
411 LLVMValueRef args
[6];
412 unsigned c
, sampler_src
;
414 if (emit_data
->inst
->Texture
.Texture
== TGSI_TEXTURE_BUFFER
) {
415 switch (emit_data
->inst
->Instruction
.Opcode
) {
416 case TGSI_OPCODE_TXQ
: {
417 LLVMValueRef offset
[2] = {
418 LLVMConstInt(LLVMInt64TypeInContext(bld_base
->base
.gallivm
->context
), 0, false),
419 lp_build_const_int32(bld_base
->base
.gallivm
, 1)
421 LLVMTypeRef const_ptr_type
= LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base
->base
.elem_type
, 4), 1024),
422 R600_BUFFER_INFO_CONST_BUFFER
);
423 LLVMValueRef const_ptr
= LLVMBuildIntToPtr(bld_base
->base
.gallivm
->builder
, lp_build_const_int32(bld_base
->base
.gallivm
, 0), const_ptr_type
, "");
424 LLVMValueRef ptr
= LLVMBuildGEP(bld_base
->base
.gallivm
->builder
, const_ptr
, offset
, 2, "");
425 LLVMValueRef cvecval
= LLVMBuildLoad(bld_base
->base
.gallivm
->builder
, ptr
, "");
426 emit_data
->output
[0] = cvecval
;
429 case TGSI_OPCODE_TXF
: {
430 args
[0] = LLVMBuildExtractElement(gallivm
->builder
, emit_data
->args
[0], lp_build_const_int32(gallivm
, 0), "");
431 args
[1] = lp_build_const_int32(gallivm
, R600_MAX_CONST_BUFFERS
);
432 emit_data
->output
[0] = build_intrinsic(gallivm
->builder
,
433 "llvm.R600.load.texbuf",
434 emit_data
->dst_type
, args
, 2, LLVMReadNoneAttribute
);
442 assert(emit_data
->arg_count
+ 2 <= Elements(args
));
444 for (c
= 0; c
< emit_data
->arg_count
; ++c
)
445 args
[c
] = emit_data
->args
[c
];
447 sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
-1;
449 args
[c
++] = lp_build_const_int32(gallivm
,
450 emit_data
->inst
->Src
[sampler_src
].Register
.Index
+ R600_MAX_CONST_BUFFERS
);
451 args
[c
++] = lp_build_const_int32(gallivm
,
452 emit_data
->inst
->Src
[sampler_src
].Register
.Index
);
453 args
[c
++] = lp_build_const_int32(gallivm
,
454 emit_data
->inst
->Texture
.Texture
);
456 emit_data
->output
[0] = build_intrinsic(gallivm
->builder
,
458 emit_data
->dst_type
, args
, c
, LLVMReadNoneAttribute
);
461 static void emit_cndlt(
462 const struct lp_build_tgsi_action
* action
,
463 struct lp_build_tgsi_context
* bld_base
,
464 struct lp_build_emit_data
* emit_data
)
466 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
467 LLVMValueRef float_zero
= lp_build_const_float(
468 bld_base
->base
.gallivm
, 0.0f
);
469 LLVMValueRef cmp
= LLVMBuildFCmp(
470 builder
, LLVMRealULT
, emit_data
->args
[0], float_zero
, "");
471 emit_data
->output
[emit_data
->chan
] = LLVMBuildSelect(builder
,
472 cmp
, emit_data
->args
[1], emit_data
->args
[2], "");
475 static void dp_fetch_args(
476 struct lp_build_tgsi_context
* bld_base
,
477 struct lp_build_emit_data
* emit_data
)
479 struct lp_build_context
* base
= &bld_base
->base
;
481 LLVMValueRef elements
[2][4];
482 unsigned opcode
= emit_data
->inst
->Instruction
.Opcode
;
483 unsigned dp_components
= (opcode
== TGSI_OPCODE_DP2
? 2 :
484 (opcode
== TGSI_OPCODE_DP3
? 3 : 4));
485 for (chan
= 0 ; chan
< dp_components
; chan
++) {
486 elements
[0][chan
] = lp_build_emit_fetch(bld_base
,
487 emit_data
->inst
, 0, chan
);
488 elements
[1][chan
] = lp_build_emit_fetch(bld_base
,
489 emit_data
->inst
, 1, chan
);
492 for ( ; chan
< 4; chan
++) {
493 elements
[0][chan
] = base
->zero
;
494 elements
[1][chan
] = base
->zero
;
498 if (opcode
== TGSI_OPCODE_DPH
) {
499 elements
[0][TGSI_CHAN_W
] = base
->one
;
502 emit_data
->args
[0] = lp_build_gather_values(bld_base
->base
.gallivm
,
504 emit_data
->args
[1] = lp_build_gather_values(bld_base
->base
.gallivm
,
506 emit_data
->arg_count
= 2;
508 emit_data
->dst_type
= base
->elem_type
;
511 static struct lp_build_tgsi_action dot_action
= {
512 .fetch_args
= dp_fetch_args
,
513 .emit
= build_tgsi_intrinsic_nomem
,
514 .intr_name
= "llvm.AMDGPU.dp4"
519 LLVMModuleRef
r600_tgsi_llvm(
520 struct radeon_llvm_context
* ctx
,
521 const struct tgsi_token
* tokens
)
523 struct tgsi_shader_info shader_info
;
524 struct lp_build_tgsi_context
* bld_base
= &ctx
->soa
.bld_base
;
525 radeon_llvm_context_init(ctx
);
526 radeon_llvm_create_func(ctx
, NULL
, 0);
527 tgsi_scan_shader(tokens
, &shader_info
);
529 bld_base
->info
= &shader_info
;
530 bld_base
->userdata
= ctx
;
531 bld_base
->emit_fetch_funcs
[TGSI_FILE_CONSTANT
] = llvm_fetch_const
;
532 bld_base
->emit_fetch_funcs
[TGSI_FILE_SYSTEM_VALUE
] = llvm_fetch_system_value
;
533 bld_base
->emit_prologue
= llvm_emit_prologue
;
534 bld_base
->emit_epilogue
= llvm_emit_epilogue
;
536 ctx
->load_input
= llvm_load_input
;
537 ctx
->load_system_value
= llvm_load_system_value
;
539 bld_base
->op_actions
[TGSI_OPCODE_DP2
] = dot_action
;
540 bld_base
->op_actions
[TGSI_OPCODE_DP3
] = dot_action
;
541 bld_base
->op_actions
[TGSI_OPCODE_DP4
] = dot_action
;
542 bld_base
->op_actions
[TGSI_OPCODE_DPH
] = dot_action
;
543 bld_base
->op_actions
[TGSI_OPCODE_DDX
].emit
= llvm_emit_tex
;
544 bld_base
->op_actions
[TGSI_OPCODE_DDY
].emit
= llvm_emit_tex
;
545 bld_base
->op_actions
[TGSI_OPCODE_TEX
].emit
= llvm_emit_tex
;
546 bld_base
->op_actions
[TGSI_OPCODE_TEX2
].emit
= llvm_emit_tex
;
547 bld_base
->op_actions
[TGSI_OPCODE_TXB
].emit
= llvm_emit_tex
;
548 bld_base
->op_actions
[TGSI_OPCODE_TXB2
].emit
= llvm_emit_tex
;
549 bld_base
->op_actions
[TGSI_OPCODE_TXD
].emit
= llvm_emit_tex
;
550 bld_base
->op_actions
[TGSI_OPCODE_TXL
].emit
= llvm_emit_tex
;
551 bld_base
->op_actions
[TGSI_OPCODE_TXL2
].emit
= llvm_emit_tex
;
552 bld_base
->op_actions
[TGSI_OPCODE_TXF
].emit
= llvm_emit_tex
;
553 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].emit
= llvm_emit_tex
;
554 bld_base
->op_actions
[TGSI_OPCODE_TXP
].emit
= llvm_emit_tex
;
555 bld_base
->op_actions
[TGSI_OPCODE_CMP
].emit
= emit_cndlt
;
557 lp_build_tgsi_llvm(bld_base
, tokens
);
559 radeon_llvm_finalize_module(ctx
);
561 return ctx
->gallivm
.module
;
564 const char * r600_llvm_gpu_string(enum radeon_family family
)
566 const char * gpu_family
;
580 gpu_family
= "rv710";
583 gpu_family
= "rv730";
587 gpu_family
= "rv770";
591 gpu_family
= "cedar";
596 gpu_family
= "redwood";
599 gpu_family
= "juniper";
603 gpu_family
= "cypress";
606 gpu_family
= "barts";
609 gpu_family
= "turks";
612 gpu_family
= "caicos";
616 gpu_family
= "cayman";
620 fprintf(stderr
, "Chip not supported by r600 llvm "
621 "backend, please file a bug at " PACKAGE_BUGREPORT
"\n");
627 unsigned r600_llvm_compile(
629 unsigned char ** inst_bytes
,
630 unsigned * inst_byte_count
,
631 enum radeon_family family
,
634 const char * gpu_family
= r600_llvm_gpu_string(family
);
635 return radeon_llvm_compile(mod
, inst_bytes
, inst_byte_count
,