src/gallium/drivers/r600/r600_llvm.c

   1 #include "r600_llvm.h"
   2
   3 #include "gallivm/lp_bld_const.h"
   4 #include "gallivm/lp_bld_intr.h"
   5 #include "gallivm/lp_bld_gather.h"
   6 #include "tgsi/tgsi_parse.h"
   7 #include "util/u_double_list.h"
   8 #include "util/u_memory.h"
   9
  10 #include "r600.h"
  11 #include "r600_asm.h"
  12 #include "r600_opcodes.h"
  13 #include "r600_shader.h"
  14 #include "radeon_llvm.h"
  15 #include "radeon_llvm_emit.h"
  16
  17 #include <stdio.h>
  18
  19 #if defined R600_USE_LLVM || defined HAVE_OPENCL
  20
  21 static LLVMValueRef llvm_fetch_const(
  22         struct lp_build_tgsi_context * bld_base,
  23         const struct tgsi_full_src_register *reg,
  24         enum tgsi_opcode_type type,
  25         unsigned swizzle)
  26 {
  27         LLVMValueRef idx = lp_build_const_int32(bld_base->base.gallivm,
  28                         radeon_llvm_reg_index_soa(reg->Register.Index, swizzle));
  29         LLVMValueRef cval = build_intrinsic(bld_base->base.gallivm->builder,
  30                 "llvm.AMDGPU.load.const", bld_base->base.elem_type,
  31                 &idx, 1, LLVMReadNoneAttribute);
  32
  33         return bitcast(bld_base, type, cval);
  34 }
  35
  36 static void llvm_load_system_value(
  37                 struct radeon_llvm_context * ctx,
  38                 unsigned index,
  39                 const struct tgsi_full_declaration *decl)
  40 {
  41         unsigned chan;
  42
  43         switch (decl->Semantic.Name) {
  44         case TGSI_SEMANTIC_INSTANCEID: chan = 3; break;
  45         case TGSI_SEMANTIC_VERTEXID: chan = 0; break;
  46         default: assert(!"unknown system value");
  47         }
  48
  49         LLVMValueRef reg = lp_build_const_int32(
  50                         ctx->soa.bld_base.base.gallivm, chan);
  51         ctx->system_values[index] = build_intrinsic(
  52                         ctx->soa.bld_base.base.gallivm->builder,
  53                         "llvm.R600.load.input",
  54                         ctx->soa.bld_base.base.elem_type, &reg, 1,
  55                         LLVMReadNoneAttribute);
  56 }
  57
  58 static LLVMValueRef llvm_fetch_system_value(
  59                 struct lp_build_tgsi_context * bld_base,
  60                 const struct tgsi_full_src_register *reg,
  61                 enum tgsi_opcode_type type,
  62                 unsigned swizzle)
  63 {
  64         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
  65         LLVMValueRef cval = ctx->system_values[reg->Register.Index];
  66         return bitcast(bld_base, type, cval);
  67 }
  68
  69 static void llvm_load_input(
  70         struct radeon_llvm_context * ctx,
  71         unsigned input_index,
  72         const struct tgsi_full_declaration *decl)
  73 {
  74         unsigned chan;
  75
  76         for (chan = 0; chan < 4; chan++) {
  77                 unsigned soa_index = radeon_llvm_reg_index_soa(input_index,
  78                                                                 chan);
  79
  80                 /* The * 4 is assuming that we are in soa mode. */
  81                 LLVMValueRef reg = lp_build_const_int32(
  82                                 ctx->soa.bld_base.base.gallivm,
  83                                 soa_index + (ctx->reserved_reg_count * 4));
  84                 ctx->inputs[soa_index] = build_intrinsic(
  85                                 ctx->soa.bld_base.base.gallivm->builder,
  86                                 "llvm.R600.load.input",
  87                                 ctx->soa.bld_base.base.elem_type, &reg, 1,
  88                                 LLVMReadNoneAttribute);
  89         }
  90 }
  91
  92 static void llvm_emit_prologue(struct lp_build_tgsi_context * bld_base)
  93 {
  94         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
  95         struct lp_build_context * base = &bld_base->base;
  96         unsigned i;
  97
  98         /* Reserve special input registers */
  99         for (i = 0; i < ctx->reserved_reg_count; i++) {
 100                 unsigned chan;
 101                 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 102                         LLVMValueRef reg_index = lp_build_const_int32(
 103                                         base->gallivm,
 104                                         radeon_llvm_reg_index_soa(i, chan));
 105                         lp_build_intrinsic_unary(base->gallivm->builder,
 106                                 "llvm.AMDGPU.reserve.reg",
 107                                 LLVMVoidTypeInContext(base->gallivm->context),
 108                                 reg_index);
 109                 }
 110         }
 111 }
 112
 113 static void llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
 114 {
 115         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 116         struct lp_build_context * base = &bld_base->base;
 117         unsigned i;
 118
 119         /* Add the necessary export instructions */
 120         for (i = 0; i < ctx->output_reg_count; i++) {
 121                 unsigned chan;
 122                 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 123                         LLVMValueRef output;
 124                         unsigned adjusted_reg_idx = i +
 125                                         ctx->reserved_reg_count;
 126                         LLVMValueRef reg_index = lp_build_const_int32(
 127                                 base->gallivm,
 128                                 radeon_llvm_reg_index_soa(adjusted_reg_idx, chan));
 129
 130                         output = LLVMBuildLoad(base->gallivm->builder,
 131                                 ctx->soa.outputs[i][chan], "");
 132
 133                         lp_build_intrinsic_binary(
 134                                 base->gallivm->builder,
 135                                 "llvm.AMDGPU.store.output",
 136                                 LLVMVoidTypeInContext(base->gallivm->context),
 137                                 output, reg_index);
 138                 }
 139         }
 140 }
 141
 142 static void llvm_emit_tex(
 143         const struct lp_build_tgsi_action * action,
 144         struct lp_build_tgsi_context * bld_base,
 145         struct lp_build_emit_data * emit_data)
 146 {
 147         struct gallivm_state * gallivm = bld_base->base.gallivm;
 148         LLVMValueRef args[6];
 149         unsigned c, sampler_src;
 150
 151         assert(emit_data->arg_count + 2 <= Elements(args));
 152
 153         for (c = 0; c < emit_data->arg_count; ++c)
 154                 args[c] = emit_data->args[c];
 155
 156         sampler_src = emit_data->inst->Instruction.NumSrcRegs-1;
 157
 158         args[c++] = lp_build_const_int32(gallivm,
 159                                         emit_data->inst->Src[sampler_src].Register.Index);
 160         args[c++] = lp_build_const_int32(gallivm,
 161                                         emit_data->inst->Texture.Texture);
 162
 163         emit_data->output[0] = build_intrinsic(gallivm->builder,
 164                                         action->intr_name,
 165                                         emit_data->dst_type, args, c, LLVMReadNoneAttribute);
 166 }
 167
 168 static void emit_cndlt(
 169                 const struct lp_build_tgsi_action * action,
 170                 struct lp_build_tgsi_context * bld_base,
 171                 struct lp_build_emit_data * emit_data)
 172 {
 173         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 174         LLVMValueRef float_zero = lp_build_const_float(
 175                 bld_base->base.gallivm, 0.0f);
 176         LLVMValueRef cmp = LLVMBuildFCmp(
 177                 builder, LLVMRealULT, emit_data->args[0], float_zero, "");
 178         emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
 179                 cmp, emit_data->args[1], emit_data->args[2], "");
 180 }
 181
 182 static void dp_fetch_args(
 183         struct lp_build_tgsi_context * bld_base,
 184         struct lp_build_emit_data * emit_data)
 185 {
 186         struct lp_build_context * base = &bld_base->base;
 187         unsigned chan;
 188         LLVMValueRef elements[2][4];
 189         unsigned opcode = emit_data->inst->Instruction.Opcode;
 190         unsigned dp_components = (opcode == TGSI_OPCODE_DP2 ? 2 :
 191                                         (opcode == TGSI_OPCODE_DP3 ? 3 : 4));
 192         for (chan = 0 ; chan < dp_components; chan++) {
 193                 elements[0][chan] = lp_build_emit_fetch(bld_base,
 194                                                 emit_data->inst, 0, chan);
 195                 elements[1][chan] = lp_build_emit_fetch(bld_base,
 196                                                 emit_data->inst, 1, chan);
 197         }
 198
 199         for ( ; chan < 4; chan++) {
 200                 elements[0][chan] = base->zero;
 201                 elements[1][chan] = base->zero;
 202         }
 203
 204          /* Fix up for DPH */
 205         if (opcode == TGSI_OPCODE_DPH) {
 206                 elements[0][TGSI_CHAN_W] = base->one;
 207         }
 208
 209         emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
 210                                                         elements[0], 4);
 211         emit_data->args[1] = lp_build_gather_values(bld_base->base.gallivm,
 212                                                         elements[1], 4);
 213         emit_data->arg_count = 2;
 214
 215         emit_data->dst_type = base->elem_type;
 216 }
 217
 218 static struct lp_build_tgsi_action dot_action = {
 219         .fetch_args = dp_fetch_args,
 220         .emit = build_tgsi_intrinsic_nomem,
 221         .intr_name = "llvm.AMDGPU.dp4"
 222 };
 223
 224
 225
 226 LLVMModuleRef r600_tgsi_llvm(
 227         struct radeon_llvm_context * ctx,
 228         const struct tgsi_token * tokens)
 229 {
 230         struct tgsi_shader_info shader_info;
 231         struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
 232         radeon_llvm_context_init(ctx);
 233         tgsi_scan_shader(tokens, &shader_info);
 234
 235         bld_base->info = &shader_info;
 236         bld_base->userdata = ctx;
 237         bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = llvm_fetch_const;
 238         bld_base->emit_fetch_funcs[TGSI_FILE_SYSTEM_VALUE] = llvm_fetch_system_value;
 239         bld_base->emit_prologue = llvm_emit_prologue;
 240         bld_base->emit_epilogue = llvm_emit_epilogue;
 241         ctx->userdata = ctx;
 242         ctx->load_input = llvm_load_input;
 243         ctx->load_system_value = llvm_load_system_value;
 244
 245         bld_base->op_actions[TGSI_OPCODE_DP2] = dot_action;
 246         bld_base->op_actions[TGSI_OPCODE_DP3] = dot_action;
 247         bld_base->op_actions[TGSI_OPCODE_DP4] = dot_action;
 248         bld_base->op_actions[TGSI_OPCODE_DPH] = dot_action;
 249         bld_base->op_actions[TGSI_OPCODE_DDX].emit = llvm_emit_tex;
 250         bld_base->op_actions[TGSI_OPCODE_DDY].emit = llvm_emit_tex;
 251         bld_base->op_actions[TGSI_OPCODE_TEX].emit = llvm_emit_tex;
 252         bld_base->op_actions[TGSI_OPCODE_TXB].emit = llvm_emit_tex;
 253         bld_base->op_actions[TGSI_OPCODE_TXD].emit = llvm_emit_tex;
 254         bld_base->op_actions[TGSI_OPCODE_TXL].emit = llvm_emit_tex;
 255         bld_base->op_actions[TGSI_OPCODE_TXF].emit = llvm_emit_tex;
 256         bld_base->op_actions[TGSI_OPCODE_TXQ].emit = llvm_emit_tex;
 257         bld_base->op_actions[TGSI_OPCODE_TXP].emit = llvm_emit_tex;
 258         bld_base->op_actions[TGSI_OPCODE_CMP].emit = emit_cndlt;
 259
 260         lp_build_tgsi_llvm(bld_base, tokens);
 261
 262         radeon_llvm_finalize_module(ctx);
 263
 264         return ctx->gallivm.module;
 265 }
 266
 267 const char * r600_llvm_gpu_string(enum radeon_family family)
 268 {
 269         const char * gpu_family;
 270
 271         switch (family) {
 272         case CHIP_R600:
 273         case CHIP_RV610:
 274         case CHIP_RV630:
 275         case CHIP_RV620:
 276         case CHIP_RV635:
 277         case CHIP_RS780:
 278         case CHIP_RS880:
 279                 gpu_family = "r600";
 280                 break;
 281         case CHIP_RV710:
 282                 gpu_family = "rv710";
 283                 break;
 284         case CHIP_RV730:
 285                 gpu_family = "rv730";
 286                 break;
 287         case CHIP_RV670:
 288         case CHIP_RV740:
 289         case CHIP_RV770:
 290                 gpu_family = "rv770";
 291                 break;
 292         case CHIP_PALM:
 293         case CHIP_CEDAR:
 294                 gpu_family = "cedar";
 295                 break;
 296         case CHIP_SUMO:
 297         case CHIP_SUMO2:
 298         case CHIP_REDWOOD:
 299                 gpu_family = "redwood";
 300                 break;
 301         case CHIP_JUNIPER:
 302                 gpu_family = "juniper";
 303                 break;
 304         case CHIP_HEMLOCK:
 305         case CHIP_CYPRESS:
 306                 gpu_family = "cypress";
 307                 break;
 308         case CHIP_BARTS:
 309                 gpu_family = "barts";
 310                 break;
 311         case CHIP_TURKS:
 312                 gpu_family = "turks";
 313                 break;
 314         case CHIP_CAICOS:
 315                 gpu_family = "caicos";
 316                 break;
 317         case CHIP_CAYMAN:
 318         case CHIP_ARUBA:
 319                 gpu_family = "cayman";
 320                 break;
 321         default:
 322                 gpu_family = "";
 323                 fprintf(stderr, "Chip not supported by r600 llvm "
 324                         "backend, please file a bug at bugs.freedesktop.org\n");
 325                 break;
 326         }
 327         return gpu_family;
 328 }
 329
 330 unsigned r600_llvm_compile(
 331         LLVMModuleRef mod,
 332         unsigned char ** inst_bytes,
 333         unsigned * inst_byte_count,
 334         enum radeon_family family,
 335         unsigned dump)
 336 {
 337         const char * gpu_family = r600_llvm_gpu_string(family);
 338         return radeon_llvm_compile(mod, inst_bytes, inst_byte_count,
 339                                                         gpu_family, dump);
 340 }
 341
 342 #endif