src/gallium/drivers/r600/r600_llvm.c

   1 #include "r600_llvm.h"
   2
   3 #include "gallivm/lp_bld_const.h"
   4 #include "gallivm/lp_bld_intr.h"
   5 #include "gallivm/lp_bld_gather.h"
   6 #include "tgsi/tgsi_parse.h"
   7 #include "util/u_double_list.h"
   8 #include "util/u_memory.h"
   9
  10 #include "r600.h"
  11 #include "r600_asm.h"
  12 #include "r600_sq.h"
  13 #include "r600_opcodes.h"
  14 #include "r600_shader.h"
  15 #include "r600_pipe.h"
  16 #include "radeon_llvm.h"
  17 #include "radeon_llvm_emit.h"
  18
  19 #include <stdio.h>
  20
  21 #if defined R600_USE_LLVM || defined HAVE_OPENCL
  22
  23 #define CONSTANT_BUFFER_0_ADDR_SPACE 8
  24 #define CONSTANT_BUFFER_1_ADDR_SPACE (CONSTANT_BUFFER_0_ADDR_SPACE + R600_UCP_CONST_BUFFER)
  25
  26 static LLVMValueRef llvm_fetch_const(
  27         struct lp_build_tgsi_context * bld_base,
  28         const struct tgsi_full_src_register *reg,
  29         enum tgsi_opcode_type type,
  30         unsigned swizzle)
  31 {
  32         LLVMValueRef offset[2] = {
  33                 LLVMConstInt(LLVMInt64TypeInContext(bld_base->base.gallivm->context), 0, false),
  34                 lp_build_const_int32(bld_base->base.gallivm, reg->Register.Index)
  35         };
  36         if (reg->Register.Indirect) {
  37                 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
  38                 LLVMValueRef index = LLVMBuildLoad(bld_base->base.gallivm->builder, bld->addr[reg->Indirect.Index][reg->Indirect.SwizzleX], "");
  39                 offset[1] = LLVMBuildAdd(bld_base->base.gallivm->builder, offset[1], index, "");
  40         }
  41         unsigned ConstantAddressSpace = CONSTANT_BUFFER_0_ADDR_SPACE ;
  42         if (reg->Register.Dimension) {
  43                 ConstantAddressSpace += reg->Dimension.Index;
  44         }
  45         LLVMTypeRef const_ptr_type = LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4), 1024),
  46                                                         ConstantAddressSpace);
  47         LLVMValueRef const_ptr = LLVMBuildIntToPtr(bld_base->base.gallivm->builder, lp_build_const_int32(bld_base->base.gallivm, 0), const_ptr_type, "");
  48         LLVMValueRef ptr = LLVMBuildGEP(bld_base->base.gallivm->builder, const_ptr, offset, 2, "");
  49         LLVMValueRef cvecval = LLVMBuildLoad(bld_base->base.gallivm->builder, ptr, "");
  50         LLVMValueRef cval = LLVMBuildExtractElement(bld_base->base.gallivm->builder, cvecval, lp_build_const_int32(bld_base->base.gallivm, swizzle), "");
  51         return bitcast(bld_base, type, cval);
  52 }
  53
  54 static void llvm_load_system_value(
  55                 struct radeon_llvm_context * ctx,
  56                 unsigned index,
  57                 const struct tgsi_full_declaration *decl)
  58 {
  59         unsigned chan;
  60
  61         switch (decl->Semantic.Name) {
  62         case TGSI_SEMANTIC_INSTANCEID: chan = 3; break;
  63         case TGSI_SEMANTIC_VERTEXID: chan = 0; break;
  64         default: assert(!"unknown system value");
  65         }
  66
  67         LLVMValueRef reg = lp_build_const_int32(
  68                         ctx->soa.bld_base.base.gallivm, chan);
  69         ctx->system_values[index] = build_intrinsic(
  70                         ctx->soa.bld_base.base.gallivm->builder,
  71                         "llvm.R600.load.input",
  72                         ctx->soa.bld_base.base.elem_type, &reg, 1,
  73                         LLVMReadNoneAttribute);
  74 }
  75
  76 static LLVMValueRef llvm_fetch_system_value(
  77                 struct lp_build_tgsi_context * bld_base,
  78                 const struct tgsi_full_src_register *reg,
  79                 enum tgsi_opcode_type type,
  80                 unsigned swizzle)
  81 {
  82         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
  83         LLVMValueRef cval = ctx->system_values[reg->Register.Index];
  84         return bitcast(bld_base, type, cval);
  85 }
  86
  87 static LLVMValueRef
  88 llvm_load_input_helper(
  89         struct radeon_llvm_context * ctx,
  90         unsigned idx, int interp, int ij_index)
  91 {
  92         const struct lp_build_context * bb = &ctx->soa.bld_base.base;
  93         LLVMValueRef arg[2];
  94         int arg_count;
  95         const char * intrinsic;
  96
  97         arg[0] = lp_build_const_int32(bb->gallivm, idx);
  98
  99         if (interp) {
 100                 intrinsic = "llvm.R600.interp.input";
 101                 arg[1] = lp_build_const_int32(bb->gallivm, ij_index);
 102                 arg_count = 2;
 103         } else {
 104                 intrinsic = "llvm.R600.load.input";
 105                 arg_count = 1;
 106         }
 107
 108         return build_intrinsic(bb->gallivm->builder, intrinsic,
 109                 bb->elem_type, &arg[0], arg_count, LLVMReadNoneAttribute);
 110 }
 111
 112 static LLVMValueRef
 113 llvm_face_select_helper(
 114         struct radeon_llvm_context * ctx,
 115         unsigned face_loc, LLVMValueRef front_color, LLVMValueRef back_color)
 116 {
 117         const struct lp_build_context * bb = &ctx->soa.bld_base.base;
 118         LLVMValueRef face = llvm_load_input_helper(ctx, face_loc, 0, 0);
 119         LLVMValueRef is_front = LLVMBuildFCmp(
 120                 bb->gallivm->builder, LLVMRealUGT, face,
 121                 lp_build_const_float(bb->gallivm, 0.0f),        "");
 122         return LLVMBuildSelect(bb->gallivm->builder, is_front,
 123                 front_color, back_color, "");
 124 }
 125
 126 static void llvm_load_input(
 127         struct radeon_llvm_context * ctx,
 128         unsigned input_index,
 129         const struct tgsi_full_declaration *decl)
 130 {
 131         const struct r600_shader_io * input = &ctx->r600_inputs[input_index];
 132         unsigned chan;
 133         unsigned interp = 0;
 134         int ij_index;
 135         int two_side = (ctx->two_side && input->name == TGSI_SEMANTIC_COLOR);
 136         LLVMValueRef v;
 137
 138         if (ctx->chip_class >= EVERGREEN && ctx->type == TGSI_PROCESSOR_FRAGMENT &&
 139                         input->spi_sid) {
 140                 interp = 1;
 141                 ij_index = (input->interpolate > 0) ? input->ij_index : -1;
 142         }
 143
 144         for (chan = 0; chan < 4; chan++) {
 145                 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
 146                 int loc;
 147
 148                 if (interp) {
 149                         loc = 4 * input->lds_pos + chan;
 150                 } else {
 151                         if (input->name == TGSI_SEMANTIC_FACE)
 152                                 loc = 4 * ctx->face_gpr;
 153                         else
 154                                 loc = 4 * input->gpr + chan;
 155                 }
 156
 157                 v = llvm_load_input_helper(ctx, loc, interp, ij_index);
 158
 159                 if (two_side) {
 160                         struct r600_shader_io * back_input =
 161                                         &ctx->r600_inputs[input->back_color_input];
 162                         int back_loc = interp ? back_input->lds_pos : back_input->gpr;
 163                         LLVMValueRef v2;
 164
 165                         back_loc = 4 * back_loc + chan;
 166                         v2 = llvm_load_input_helper(ctx, back_loc, interp, ij_index);
 167                         v = llvm_face_select_helper(ctx, 4 * ctx->face_gpr, v, v2);
 168                 } else if (input->name == TGSI_SEMANTIC_POSITION &&
 169                                 ctx->type == TGSI_PROCESSOR_FRAGMENT && chan == 3) {
 170                         /* RCP for fragcoord.w */
 171                         v = LLVMBuildFDiv(ctx->gallivm.builder,
 172                                         lp_build_const_float(&(ctx->gallivm), 1.0f),
 173                                         v, "");
 174                 }
 175
 176                 ctx->inputs[soa_index] = v;
 177         }
 178 }
 179
 180 static void llvm_emit_prologue(struct lp_build_tgsi_context * bld_base)
 181 {
 182         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 183
 184 }
 185
 186 static void llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
 187 {
 188         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 189         struct lp_build_context * base = &bld_base->base;
 190         struct pipe_stream_output_info * so = ctx->stream_outputs;
 191         unsigned i;
 192         unsigned next_pos = 60;
 193         unsigned next_param = 0;
 194
 195         unsigned color_count = 0;
 196         boolean has_color = false;
 197
 198         if (ctx->type == TGSI_PROCESSOR_VERTEX && so->num_outputs) {
 199                 for (i = 0; i < so->num_outputs; i++) {
 200                         unsigned register_index = so->output[i].register_index;
 201                         unsigned start_component = so->output[i].start_component;
 202                         unsigned num_components = so->output[i].num_components;
 203                         unsigned dst_offset = so->output[i].dst_offset;
 204                         unsigned chan;
 205                         LLVMValueRef elements[4];
 206                         if (dst_offset < start_component) {
 207                                 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 208                                         elements[chan] = LLVMBuildLoad(base->gallivm->builder,
 209                                                 ctx->soa.outputs[register_index][(chan + start_component) % TGSI_NUM_CHANNELS], "");
 210                                 }
 211                                 start_component = 0;
 212                         } else {
 213                                 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 214                                         elements[chan] = LLVMBuildLoad(base->gallivm->builder,
 215                                                 ctx->soa.outputs[register_index][chan], "");
 216                                 }
 217                         }
 218                         LLVMValueRef output = lp_build_gather_values(base->gallivm, elements, 4);
 219                         LLVMValueRef args[4];
 220                         args[0] = output;
 221                         args[1] = lp_build_const_int32(base->gallivm, dst_offset - start_component);
 222                         args[2] = lp_build_const_int32(base->gallivm, so->output[i].output_buffer);
 223                         args[3] = lp_build_const_int32(base->gallivm, ((1 << num_components) - 1) << start_component);
 224                         lp_build_intrinsic(base->gallivm->builder, "llvm.R600.store.stream.output",
 225                                 LLVMVoidTypeInContext(base->gallivm->context), args, 4);
 226                 }
 227         }
 228
 229         /* Add the necessary export instructions */
 230         for (i = 0; i < ctx->output_reg_count; i++) {
 231                 unsigned chan;
 232                 LLVMValueRef elements[4];
 233                 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 234                         elements[chan] = LLVMBuildLoad(base->gallivm->builder,
 235                                 ctx->soa.outputs[i][chan], "");
 236                 }
 237                 if (ctx->alpha_to_one && ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->r600_outputs[i].name == TGSI_SEMANTIC_COLOR)
 238                         elements[3] = lp_build_const_float(base->gallivm, 1.0f);
 239                 LLVMValueRef output = lp_build_gather_values(base->gallivm, elements, 4);
 240
 241                 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
 242                         switch (ctx->r600_outputs[i].name) {
 243                         case TGSI_SEMANTIC_POSITION:
 244                         case TGSI_SEMANTIC_PSIZE: {
 245                                 LLVMValueRef args[3];
 246                                 args[0] = output;
 247                                 args[1] = lp_build_const_int32(base->gallivm, next_pos++);
 248                                 args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS);
 249                                 build_intrinsic(
 250                                         base->gallivm->builder,
 251                                         "llvm.R600.store.swizzle",
 252                                         LLVMVoidTypeInContext(base->gallivm->context),
 253                                         args, 3, 0);
 254                                 break;
 255                         }
 256                         case TGSI_SEMANTIC_CLIPVERTEX: {
 257                                 LLVMValueRef args[3];
 258                                 unsigned reg_index;
 259                                 unsigned base_vector_chan;
 260                                 LLVMValueRef adjusted_elements[4];
 261                                 for (reg_index = 0; reg_index < 2; reg_index ++) {
 262                                         for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 263                                                 LLVMValueRef offset[2] = {
 264                                                         LLVMConstInt(LLVMInt64TypeInContext(bld_base->base.gallivm->context), 0, false),
 265                                                         lp_build_const_int32(bld_base->base.gallivm, reg_index * 4 + chan)
 266                                                 };
 267                                                 LLVMTypeRef const_ptr_type = LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4), 1024), CONSTANT_BUFFER_1_ADDR_SPACE);
 268                                                 LLVMValueRef const_ptr = LLVMBuildIntToPtr(bld_base->base.gallivm->builder, lp_build_const_int32(bld_base->base.gallivm, 0), const_ptr_type, "");
 269                                                 LLVMValueRef ptr = LLVMBuildGEP(bld_base->base.gallivm->builder, const_ptr, offset, 2, "");
 270                                                 LLVMValueRef base_vector = LLVMBuildLoad(bld_base->base.gallivm->builder, ptr, "");
 271                                                 args[0] = output;
 272                                                 args[1] = base_vector;
 273                                                 adjusted_elements[chan] = build_intrinsic(base->gallivm->builder,
 274                                                         "llvm.AMDGPU.dp4", bld_base->base.elem_type,
 275                                                         args, 2, LLVMReadNoneAttribute);
 276                                         }
 277                                         args[0] = lp_build_gather_values(base->gallivm,
 278                                                 adjusted_elements, 4);
 279                                         args[1] = lp_build_const_int32(base->gallivm, next_pos++);
 280                                         args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS);
 281                                         build_intrinsic(
 282                                                 base->gallivm->builder,
 283                                                 "llvm.R600.store.swizzle",
 284                                                 LLVMVoidTypeInContext(base->gallivm->context),
 285                                                 args, 3, 0);
 286                                 }
 287                                 break;
 288                         }
 289                         case TGSI_SEMANTIC_CLIPDIST : {
 290                                 LLVMValueRef args[3];
 291                                 args[0] = output;
 292                                 args[1] = lp_build_const_int32(base->gallivm, next_pos++);
 293                                 args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS);
 294                                 build_intrinsic(
 295                                         base->gallivm->builder,
 296                                         "llvm.R600.store.swizzle",
 297                                         LLVMVoidTypeInContext(base->gallivm->context),
 298                                         args, 3, 0);
 299                                 args[1] = lp_build_const_int32(base->gallivm, next_param++);
 300                                 args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM);
 301                                 build_intrinsic(
 302                                         base->gallivm->builder,
 303                                         "llvm.R600.store.swizzle",
 304                                         LLVMVoidTypeInContext(base->gallivm->context),
 305                                         args, 3, 0);
 306                                 break;
 307                         }
 308                         case TGSI_SEMANTIC_FOG: {
 309                                 elements[0] = LLVMBuildLoad(base->gallivm->builder,
 310                                         ctx->soa.outputs[i][0], "");
 311                                 elements[1] = elements[2] = lp_build_const_float(base->gallivm, 0.0f);
 312                                 elements[3] = lp_build_const_float(base->gallivm, 1.0f);
 313
 314                                 LLVMValueRef args[3];
 315                                 args[0] = lp_build_gather_values(base->gallivm, elements, 4);
 316                                 args[1] = lp_build_const_int32(base->gallivm, next_param++);
 317                                 args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM);
 318                                 build_intrinsic(
 319                                         base->gallivm->builder,
 320                                         "llvm.R600.store.swizzle",
 321                                         LLVMVoidTypeInContext(base->gallivm->context),
 322                                         args, 3, 0);
 323                                 break;
 324                         }
 325                         default: {
 326                                 LLVMValueRef args[3];
 327                                 args[0] = output;
 328                                 args[1] = lp_build_const_int32(base->gallivm, next_param++);
 329                                 args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM);
 330                                 build_intrinsic(
 331                                         base->gallivm->builder,
 332                                         "llvm.R600.store.swizzle",
 333                                         LLVMVoidTypeInContext(base->gallivm->context),
 334                                         args, 3, 0);
 335                                 break;
 336                         }
 337                         }
 338                 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
 339                         switch (ctx->r600_outputs[i].name) {
 340                         case TGSI_SEMANTIC_COLOR:
 341                                 has_color = true;
 342                                 if ( color_count < ctx->color_buffer_count) {
 343                                         LLVMValueRef args[3];
 344                                         args[0] = output;
 345                                         if (ctx->fs_color_all) {
 346                                                 for (unsigned j = 0; j < ctx->color_buffer_count; j++) {
 347                                                         args[1] = lp_build_const_int32(base->gallivm, j);
 348                                                         args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL);
 349                                                         build_intrinsic(
 350                                                                 base->gallivm->builder,
 351                                                                 "llvm.R600.store.swizzle",
 352                                                                 LLVMVoidTypeInContext(base->gallivm->context),
 353                                                                 args, 3, 0);
 354                                                 }
 355                                         } else {
 356                                                 args[1] = lp_build_const_int32(base->gallivm, color_count++);
 357                                                 args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL);
 358                                                 build_intrinsic(
 359                                                         base->gallivm->builder,
 360                                                         "llvm.R600.store.swizzle",
 361                                                         LLVMVoidTypeInContext(base->gallivm->context),
 362                                                         args, 3, 0);
 363                                         }
 364                                 }
 365                                 break;
 366                         case TGSI_SEMANTIC_POSITION:
 367                                 lp_build_intrinsic_unary(
 368                                         base->gallivm->builder,
 369                                         "llvm.R600.store.pixel.depth",
 370                                         LLVMVoidTypeInContext(base->gallivm->context),
 371                                         LLVMBuildLoad(base->gallivm->builder, ctx->soa.outputs[i][2], ""));
 372                                 break;
 373                         case TGSI_SEMANTIC_STENCIL:
 374                                 lp_build_intrinsic_unary(
 375                                         base->gallivm->builder,
 376                                         "llvm.R600.store.pixel.stencil",
 377                                         LLVMVoidTypeInContext(base->gallivm->context),
 378                                         LLVMBuildLoad(base->gallivm->builder, ctx->soa.outputs[i][1], ""));
 379                                 break;
 380                         }
 381                 }
 382         }
 383         // Add dummy exports
 384         if (ctx->type == TGSI_PROCESSOR_VERTEX) {
 385                 if (!next_param) {
 386                         lp_build_intrinsic_unary(base->gallivm->builder, "llvm.R600.store.dummy",
 387                                 LLVMVoidTypeInContext(base->gallivm->context),
 388                                 lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM));
 389                 }
 390                 if (!(next_pos-60)) {
 391                         lp_build_intrinsic_unary(base->gallivm->builder, "llvm.R600.store.dummy",
 392                                 LLVMVoidTypeInContext(base->gallivm->context),
 393                                 lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS));
 394                 }
 395         }
 396         if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
 397                 if (!has_color) {
 398                         lp_build_intrinsic_unary(base->gallivm->builder, "llvm.R600.store.dummy",
 399                                 LLVMVoidTypeInContext(base->gallivm->context),
 400                                 lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL));
 401                 }
 402         }
 403
 404 }
 405
 406 static void llvm_emit_tex(
 407         const struct lp_build_tgsi_action * action,
 408         struct lp_build_tgsi_context * bld_base,
 409         struct lp_build_emit_data * emit_data)
 410 {
 411         struct gallivm_state * gallivm = bld_base->base.gallivm;
 412         LLVMValueRef args[6];
 413         unsigned c, sampler_src;
 414
 415         if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
 416                 switch (emit_data->inst->Instruction.Opcode) {
 417                 case TGSI_OPCODE_TXQ: {
 418                         LLVMValueRef offset[2] = {
 419                                 LLVMConstInt(LLVMInt64TypeInContext(bld_base->base.gallivm->context), 0, false),
 420                                 lp_build_const_int32(bld_base->base.gallivm, 1)
 421                         };
 422                         LLVMTypeRef const_ptr_type = LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4), 1024),
 423                                                                         R600_BUFFER_INFO_CONST_BUFFER);
 424                         LLVMValueRef const_ptr = LLVMBuildIntToPtr(bld_base->base.gallivm->builder, lp_build_const_int32(bld_base->base.gallivm, 0), const_ptr_type, "");
 425                         LLVMValueRef ptr = LLVMBuildGEP(bld_base->base.gallivm->builder, const_ptr, offset, 2, "");
 426                         LLVMValueRef cvecval = LLVMBuildLoad(bld_base->base.gallivm->builder, ptr, "");
 427                         emit_data->output[0] = cvecval;
 428                         return;
 429                 }
 430                 case TGSI_OPCODE_TXF: {
 431                         args[0] = LLVMBuildExtractElement(gallivm->builder, emit_data->args[0], lp_build_const_int32(gallivm, 0), "");
 432                         args[1] = lp_build_const_int32(gallivm, R600_MAX_CONST_BUFFERS);
 433                         emit_data->output[0] = build_intrinsic(gallivm->builder,
 434                                                         "llvm.R600.load.texbuf",
 435                                                         emit_data->dst_type, args, 2, LLVMReadNoneAttribute);
 436                 }
 437                         return;
 438                 default:
 439                         break;
 440                 }
 441         }
 442
 443         assert(emit_data->arg_count + 2 <= Elements(args));
 444
 445         for (c = 0; c < emit_data->arg_count; ++c)
 446                 args[c] = emit_data->args[c];
 447
 448         sampler_src = emit_data->inst->Instruction.NumSrcRegs-1;
 449
 450         args[c++] = lp_build_const_int32(gallivm,
 451                                         emit_data->inst->Src[sampler_src].Register.Index + R600_MAX_CONST_BUFFERS);
 452         args[c++] = lp_build_const_int32(gallivm,
 453                                         emit_data->inst->Src[sampler_src].Register.Index);
 454         args[c++] = lp_build_const_int32(gallivm,
 455                                         emit_data->inst->Texture.Texture);
 456
 457         emit_data->output[0] = build_intrinsic(gallivm->builder,
 458                                         action->intr_name,
 459                                         emit_data->dst_type, args, c, LLVMReadNoneAttribute);
 460 }
 461
 462 static void emit_cndlt(
 463                 const struct lp_build_tgsi_action * action,
 464                 struct lp_build_tgsi_context * bld_base,
 465                 struct lp_build_emit_data * emit_data)
 466 {
 467         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 468         LLVMValueRef float_zero = lp_build_const_float(
 469                 bld_base->base.gallivm, 0.0f);
 470         LLVMValueRef cmp = LLVMBuildFCmp(
 471                 builder, LLVMRealULT, emit_data->args[0], float_zero, "");
 472         emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
 473                 cmp, emit_data->args[1], emit_data->args[2], "");
 474 }
 475
 476 static void dp_fetch_args(
 477         struct lp_build_tgsi_context * bld_base,
 478         struct lp_build_emit_data * emit_data)
 479 {
 480         struct lp_build_context * base = &bld_base->base;
 481         unsigned chan;
 482         LLVMValueRef elements[2][4];
 483         unsigned opcode = emit_data->inst->Instruction.Opcode;
 484         unsigned dp_components = (opcode == TGSI_OPCODE_DP2 ? 2 :
 485                                         (opcode == TGSI_OPCODE_DP3 ? 3 : 4));
 486         for (chan = 0 ; chan < dp_components; chan++) {
 487                 elements[0][chan] = lp_build_emit_fetch(bld_base,
 488                                                 emit_data->inst, 0, chan);
 489                 elements[1][chan] = lp_build_emit_fetch(bld_base,
 490                                                 emit_data->inst, 1, chan);
 491         }
 492
 493         for ( ; chan < 4; chan++) {
 494                 elements[0][chan] = base->zero;
 495                 elements[1][chan] = base->zero;
 496         }
 497
 498          /* Fix up for DPH */
 499         if (opcode == TGSI_OPCODE_DPH) {
 500                 elements[0][TGSI_CHAN_W] = base->one;
 501         }
 502
 503         emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
 504                                                         elements[0], 4);
 505         emit_data->args[1] = lp_build_gather_values(bld_base->base.gallivm,
 506                                                         elements[1], 4);
 507         emit_data->arg_count = 2;
 508
 509         emit_data->dst_type = base->elem_type;
 510 }
 511
 512 static struct lp_build_tgsi_action dot_action = {
 513         .fetch_args = dp_fetch_args,
 514         .emit = build_tgsi_intrinsic_nomem,
 515         .intr_name = "llvm.AMDGPU.dp4"
 516 };
 517
 518
 519
 520 LLVMModuleRef r600_tgsi_llvm(
 521         struct radeon_llvm_context * ctx,
 522         const struct tgsi_token * tokens)
 523 {
 524         struct tgsi_shader_info shader_info;
 525         struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
 526         radeon_llvm_context_init(ctx);
 527         radeon_llvm_create_func(ctx, NULL, 0);
 528         tgsi_scan_shader(tokens, &shader_info);
 529
 530         bld_base->info = &shader_info;
 531         bld_base->userdata = ctx;
 532         bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = llvm_fetch_const;
 533         bld_base->emit_fetch_funcs[TGSI_FILE_SYSTEM_VALUE] = llvm_fetch_system_value;
 534         bld_base->emit_prologue = llvm_emit_prologue;
 535         bld_base->emit_epilogue = llvm_emit_epilogue;
 536         ctx->userdata = ctx;
 537         ctx->load_input = llvm_load_input;
 538         ctx->load_system_value = llvm_load_system_value;
 539
 540         bld_base->op_actions[TGSI_OPCODE_DP2] = dot_action;
 541         bld_base->op_actions[TGSI_OPCODE_DP3] = dot_action;
 542         bld_base->op_actions[TGSI_OPCODE_DP4] = dot_action;
 543         bld_base->op_actions[TGSI_OPCODE_DPH] = dot_action;
 544         bld_base->op_actions[TGSI_OPCODE_DDX].emit = llvm_emit_tex;
 545         bld_base->op_actions[TGSI_OPCODE_DDY].emit = llvm_emit_tex;
 546         bld_base->op_actions[TGSI_OPCODE_TEX].emit = llvm_emit_tex;
 547         bld_base->op_actions[TGSI_OPCODE_TEX2].emit = llvm_emit_tex;
 548         bld_base->op_actions[TGSI_OPCODE_TXB].emit = llvm_emit_tex;
 549         bld_base->op_actions[TGSI_OPCODE_TXB2].emit = llvm_emit_tex;
 550         bld_base->op_actions[TGSI_OPCODE_TXD].emit = llvm_emit_tex;
 551         bld_base->op_actions[TGSI_OPCODE_TXL].emit = llvm_emit_tex;
 552         bld_base->op_actions[TGSI_OPCODE_TXL2].emit = llvm_emit_tex;
 553         bld_base->op_actions[TGSI_OPCODE_TXF].emit = llvm_emit_tex;
 554         bld_base->op_actions[TGSI_OPCODE_TXQ].emit = llvm_emit_tex;
 555         bld_base->op_actions[TGSI_OPCODE_TXP].emit = llvm_emit_tex;
 556         bld_base->op_actions[TGSI_OPCODE_CMP].emit = emit_cndlt;
 557
 558         lp_build_tgsi_llvm(bld_base, tokens);
 559
 560         radeon_llvm_finalize_module(ctx);
 561
 562         return ctx->gallivm.module;
 563 }
 564
 565 const char * r600_llvm_gpu_string(enum radeon_family family)
 566 {
 567         const char * gpu_family;
 568
 569         switch (family) {
 570         case CHIP_R600:
 571         case CHIP_RV610:
 572         case CHIP_RV630:
 573         case CHIP_RV620:
 574         case CHIP_RV635:
 575         case CHIP_RV670:
 576         case CHIP_RS780:
 577         case CHIP_RS880:
 578                 gpu_family = "r600";
 579                 break;
 580         case CHIP_RV710:
 581                 gpu_family = "rv710";
 582                 break;
 583         case CHIP_RV730:
 584                 gpu_family = "rv730";
 585                 break;
 586         case CHIP_RV740:
 587         case CHIP_RV770:
 588                 gpu_family = "rv770";
 589                 break;
 590         case CHIP_PALM:
 591         case CHIP_CEDAR:
 592                 gpu_family = "cedar";
 593                 break;
 594         case CHIP_SUMO:
 595         case CHIP_SUMO2:
 596         case CHIP_REDWOOD:
 597                 gpu_family = "redwood";
 598                 break;
 599         case CHIP_JUNIPER:
 600                 gpu_family = "juniper";
 601                 break;
 602         case CHIP_HEMLOCK:
 603         case CHIP_CYPRESS:
 604                 gpu_family = "cypress";
 605                 break;
 606         case CHIP_BARTS:
 607                 gpu_family = "barts";
 608                 break;
 609         case CHIP_TURKS:
 610                 gpu_family = "turks";
 611                 break;
 612         case CHIP_CAICOS:
 613                 gpu_family = "caicos";
 614                 break;
 615         case CHIP_CAYMAN:
 616         case CHIP_ARUBA:
 617                 gpu_family = "cayman";
 618                 break;
 619         default:
 620                 gpu_family = "";
 621                 fprintf(stderr, "Chip not supported by r600 llvm "
 622                         "backend, please file a bug at bugs.freedesktop.org\n");
 623                 break;
 624         }
 625         return gpu_family;
 626 }
 627
 628 unsigned r600_llvm_compile(
 629         LLVMModuleRef mod,
 630         unsigned char ** inst_bytes,
 631         unsigned * inst_byte_count,
 632         enum radeon_family family,
 633         unsigned dump)
 634 {
 635         const char * gpu_family = r600_llvm_gpu_string(family);
 636         return radeon_llvm_compile(mod, inst_bytes, inst_byte_count,
 637                                                         gpu_family, dump);
 638 }
 639
 640 #endif