src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_blitter.h"
  34 #include "util/u_debug.h"
  35 #include "util/u_memory.h"
  36 #include "util/u_simple_shaders.h"
  37 #include "util/u_upload_mgr.h"
  38 #include "util/u_math.h"
  39 #include "vl/vl_decoder.h"
  40 #include "vl/vl_video_buffer.h"
  41 #include "radeon/radeon_uvd.h"
  42 #include "os/os_time.h"
  43
  44 static const struct debug_named_value r600_debug_options[] = {
  45         /* features */
  46         { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
  47 #if defined(R600_USE_LLVM)
  48         { "nollvm", DBG_NO_LLVM, "Disable the LLVM shader compiler" },
  49 #endif
  50         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  51         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
  52         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
  53         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
  54
  55         /* shader backend */
  56         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  57         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  58         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  59         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  60         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  61         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  62         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  63         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  64
  65         DEBUG_NAMED_VALUE_END /* must be last */
  66 };
  67
  68 /*
  69  * pipe_context
  70  */
  71
  72 static void r600_flush(struct pipe_context *ctx, unsigned flags)
  73 {
  74         struct r600_context *rctx = (struct r600_context *)ctx;
  75         struct pipe_query *render_cond = NULL;
  76         unsigned render_cond_mode = 0;
  77         boolean render_cond_cond = FALSE;
  78
  79         if (rctx->b.rings.gfx.cs->cdw == rctx->initial_gfx_cs_size)
  80                 return;
  81
  82         rctx->b.rings.gfx.flushing = true;
  83         /* Disable render condition. */
  84         if (rctx->current_render_cond) {
  85                 render_cond = rctx->current_render_cond;
  86                 render_cond_cond = rctx->current_render_cond_cond;
  87                 render_cond_mode = rctx->current_render_cond_mode;
  88                 ctx->render_condition(ctx, NULL, FALSE, 0);
  89         }
  90
  91         r600_context_flush(rctx, flags);
  92         rctx->b.rings.gfx.flushing = false;
  93         r600_begin_new_cs(rctx);
  94
  95         /* Re-enable render condition. */
  96         if (render_cond) {
  97                 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
  98         }
  99
 100         rctx->initial_gfx_cs_size = rctx->b.rings.gfx.cs->cdw;
 101 }
 102
 103 static void r600_flush_from_st(struct pipe_context *ctx,
 104                                struct pipe_fence_handle **fence,
 105                                unsigned flags)
 106 {
 107         struct r600_context *rctx = (struct r600_context *)ctx;
 108         unsigned fflags;
 109
 110         fflags = flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0;
 111         if (fence) {
 112                 *fence = rctx->b.ws->cs_create_fence(rctx->b.rings.gfx.cs);
 113         }
 114         /* flush gfx & dma ring, order does not matter as only one can be live */
 115         if (rctx->b.rings.dma.cs) {
 116                 rctx->b.rings.dma.flush(rctx, fflags);
 117         }
 118         rctx->b.rings.gfx.flush(rctx, fflags);
 119 }
 120
 121 static void r600_flush_gfx_ring(void *ctx, unsigned flags)
 122 {
 123         r600_flush((struct pipe_context*)ctx, flags);
 124 }
 125
 126 static void r600_flush_dma_ring(void *ctx, unsigned flags)
 127 {
 128         struct r600_context *rctx = (struct r600_context *)ctx;
 129         struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
 130
 131         if (!cs->cdw) {
 132                 return;
 133         }
 134
 135         rctx->b.rings.dma.flushing = true;
 136         rctx->b.ws->cs_flush(cs, flags, 0);
 137         rctx->b.rings.dma.flushing = false;
 138 }
 139
 140 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 141 {
 142         struct r600_context *rctx = (struct r600_context *)ctx;
 143
 144         rctx->b.rings.gfx.flush(rctx, flags);
 145 }
 146
 147 static void r600_flush_dma_from_winsys(void *ctx, unsigned flags)
 148 {
 149         struct r600_context *rctx = (struct r600_context *)ctx;
 150
 151         rctx->b.rings.dma.flush(rctx, flags);
 152 }
 153
 154 static void r600_destroy_context(struct pipe_context *context)
 155 {
 156         struct r600_context *rctx = (struct r600_context *)context;
 157
 158         r600_isa_destroy(rctx->isa);
 159
 160         r600_sb_context_destroy(rctx->sb_context);
 161
 162         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
 163         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
 164
 165         if (rctx->dummy_pixel_shader) {
 166                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 167         }
 168         if (rctx->custom_dsa_flush) {
 169                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
 170         }
 171         if (rctx->custom_blend_resolve) {
 172                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
 173         }
 174         if (rctx->custom_blend_decompress) {
 175                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
 176         }
 177         if (rctx->custom_blend_fastclear) {
 178                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
 179         }
 180         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 181
 182         if (rctx->blitter) {
 183                 util_blitter_destroy(rctx->blitter);
 184         }
 185         if (rctx->uploader) {
 186                 u_upload_destroy(rctx->uploader);
 187         }
 188         if (rctx->allocator_fetch_shader) {
 189                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 190         }
 191         util_slab_destroy(&rctx->pool_transfers);
 192
 193         r600_release_command_buffer(&rctx->start_cs_cmd);
 194
 195         if (rctx->b.rings.gfx.cs) {
 196                 rctx->b.ws->cs_destroy(rctx->b.rings.gfx.cs);
 197         }
 198         if (rctx->b.rings.dma.cs) {
 199                 rctx->b.ws->cs_destroy(rctx->b.rings.dma.cs);
 200         }
 201
 202         r600_common_context_cleanup(&rctx->b);
 203         FREE(rctx);
 204 }
 205
 206 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 207 {
 208         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 209         struct r600_screen* rscreen = (struct r600_screen *)screen;
 210
 211         if (rctx == NULL)
 212                 return NULL;
 213
 214         util_slab_create(&rctx->pool_transfers,
 215                          sizeof(struct r600_transfer), 64,
 216                          UTIL_SLAB_SINGLETHREADED);
 217
 218         rctx->b.b.screen = screen;
 219         rctx->b.b.priv = priv;
 220         rctx->b.b.destroy = r600_destroy_context;
 221         rctx->b.b.flush = r600_flush_from_st;
 222
 223         if (!r600_common_context_init(&rctx->b, &rscreen->b))
 224                 goto fail;
 225
 226         rctx->screen = rscreen;
 227         rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
 228
 229         LIST_INITHEAD(&rctx->active_nontimer_queries);
 230
 231         r600_init_blit_functions(rctx);
 232         r600_init_query_functions(rctx);
 233         r600_init_context_resource_functions(rctx);
 234
 235         if (rscreen->b.info.has_uvd) {
 236                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 237                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 238         } else {
 239                 rctx->b.b.create_video_codec = vl_create_decoder;
 240                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 241         }
 242
 243         r600_init_common_state_functions(rctx);
 244
 245         switch (rctx->b.chip_class) {
 246         case R600:
 247         case R700:
 248                 r600_init_state_functions(rctx);
 249                 r600_init_atom_start_cs(rctx);
 250                 rctx->max_db = 4;
 251                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 252                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 253                                                                       : r600_create_resolve_blend(rctx);
 254                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 255                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 256                                            rctx->b.family == CHIP_RV620 ||
 257                                            rctx->b.family == CHIP_RS780 ||
 258                                            rctx->b.family == CHIP_RS880 ||
 259                                            rctx->b.family == CHIP_RV710);
 260                 break;
 261         case EVERGREEN:
 262         case CAYMAN:
 263                 evergreen_init_state_functions(rctx);
 264                 evergreen_init_atom_start_cs(rctx);
 265                 evergreen_init_atom_start_compute_cs(rctx);
 266                 rctx->max_db = 8;
 267                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 268                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 269                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 270                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 271                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 272                                            rctx->b.family == CHIP_PALM ||
 273                                            rctx->b.family == CHIP_SUMO ||
 274                                            rctx->b.family == CHIP_SUMO2 ||
 275                                            rctx->b.family == CHIP_CAICOS ||
 276                                            rctx->b.family == CHIP_CAYMAN ||
 277                                            rctx->b.family == CHIP_ARUBA);
 278                 break;
 279         default:
 280                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 281                 goto fail;
 282         }
 283
 284         if (rscreen->trace_bo) {
 285                 rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, rscreen->trace_bo->cs_buf);
 286         } else {
 287                 rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, NULL);
 288         }
 289         rctx->b.rings.gfx.flush = r600_flush_gfx_ring;
 290         rctx->b.ws->cs_set_flush_callback(rctx->b.rings.gfx.cs, r600_flush_from_winsys, rctx);
 291         rctx->b.rings.gfx.flushing = false;
 292
 293         rctx->b.rings.dma.cs = NULL;
 294         if (rscreen->b.info.r600_has_dma && !(rscreen->b.debug_flags & DBG_NO_ASYNC_DMA)) {
 295                 rctx->b.rings.dma.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_DMA, NULL);
 296                 rctx->b.rings.dma.flush = r600_flush_dma_ring;
 297                 rctx->b.ws->cs_set_flush_callback(rctx->b.rings.dma.cs, r600_flush_dma_from_winsys, rctx);
 298                 rctx->b.rings.dma.flushing = false;
 299         }
 300
 301         rctx->uploader = u_upload_create(&rctx->b.b, 1024 * 1024, 256,
 302                                         PIPE_BIND_INDEX_BUFFER |
 303                                         PIPE_BIND_CONSTANT_BUFFER);
 304         if (!rctx->uploader)
 305                 goto fail;
 306
 307         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
 308                                                              0, PIPE_USAGE_STATIC, FALSE);
 309         if (!rctx->allocator_fetch_shader)
 310                 goto fail;
 311
 312         rctx->isa = calloc(1, sizeof(struct r600_isa));
 313         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 314                 goto fail;
 315
 316         rctx->blitter = util_blitter_create(&rctx->b.b);
 317         if (rctx->blitter == NULL)
 318                 goto fail;
 319         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 320         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 321
 322         r600_begin_new_cs(rctx);
 323         r600_get_backend_mask(rctx); /* this emits commands and must be last */
 324
 325         rctx->dummy_pixel_shader =
 326                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 327                                                      TGSI_SEMANTIC_GENERIC,
 328                                                      TGSI_INTERPOLATE_CONSTANT);
 329         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 330
 331         return &rctx->b.b;
 332
 333 fail:
 334         r600_destroy_context(&rctx->b.b);
 335         return NULL;
 336 }
 337
 338 /*
 339  * pipe_screen
 340  */
 341 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 342 {
 343         return "X.Org";
 344 }
 345
 346 static const char *r600_get_family_name(enum radeon_family family)
 347 {
 348         switch(family) {
 349         case CHIP_R600: return "AMD R600";
 350         case CHIP_RV610: return "AMD RV610";
 351         case CHIP_RV630: return "AMD RV630";
 352         case CHIP_RV670: return "AMD RV670";
 353         case CHIP_RV620: return "AMD RV620";
 354         case CHIP_RV635: return "AMD RV635";
 355         case CHIP_RS780: return "AMD RS780";
 356         case CHIP_RS880: return "AMD RS880";
 357         case CHIP_RV770: return "AMD RV770";
 358         case CHIP_RV730: return "AMD RV730";
 359         case CHIP_RV710: return "AMD RV710";
 360         case CHIP_RV740: return "AMD RV740";
 361         case CHIP_CEDAR: return "AMD CEDAR";
 362         case CHIP_REDWOOD: return "AMD REDWOOD";
 363         case CHIP_JUNIPER: return "AMD JUNIPER";
 364         case CHIP_CYPRESS: return "AMD CYPRESS";
 365         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 366         case CHIP_PALM: return "AMD PALM";
 367         case CHIP_SUMO: return "AMD SUMO";
 368         case CHIP_SUMO2: return "AMD SUMO2";
 369         case CHIP_BARTS: return "AMD BARTS";
 370         case CHIP_TURKS: return "AMD TURKS";
 371         case CHIP_CAICOS: return "AMD CAICOS";
 372         case CHIP_CAYMAN: return "AMD CAYMAN";
 373         case CHIP_ARUBA: return "AMD ARUBA";
 374         default: return "AMD unknown";
 375         }
 376 }
 377
 378 static const char* r600_get_name(struct pipe_screen* pscreen)
 379 {
 380         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 381
 382         return r600_get_family_name(rscreen->b.family);
 383 }
 384
 385 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 386 {
 387         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 388         enum radeon_family family = rscreen->b.family;
 389
 390         switch (param) {
 391         /* Supported features (boolean caps). */
 392         case PIPE_CAP_NPOT_TEXTURES:
 393         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 394         case PIPE_CAP_TWO_SIDED_STENCIL:
 395         case PIPE_CAP_ANISOTROPIC_FILTER:
 396         case PIPE_CAP_POINT_SPRITE:
 397         case PIPE_CAP_OCCLUSION_QUERY:
 398         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 399         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 400         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 401         case PIPE_CAP_TEXTURE_SWIZZLE:
 402         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 403         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 404         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 405         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 406         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 407         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 408         case PIPE_CAP_SM3:
 409         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 410         case PIPE_CAP_PRIMITIVE_RESTART:
 411         case PIPE_CAP_CONDITIONAL_RENDER:
 412         case PIPE_CAP_TEXTURE_BARRIER:
 413         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 414         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 415         case PIPE_CAP_TGSI_INSTANCEID:
 416         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 417         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 418         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 419         case PIPE_CAP_USER_INDEX_BUFFERS:
 420         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 421         case PIPE_CAP_COMPUTE:
 422         case PIPE_CAP_START_INSTANCE:
 423         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 424         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 425         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 426         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 427         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 428                 return 1;
 429
 430         case PIPE_CAP_TGSI_TEXCOORD:
 431                 return 0;
 432
 433         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 434                 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
 435
 436         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 437                 return R600_MAP_BUFFER_ALIGNMENT;
 438
 439         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 440                 return 256;
 441
 442         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 443                 return 1;
 444
 445         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 446                 return 140;
 447
 448         /* Supported except the original R600. */
 449         case PIPE_CAP_INDEP_BLEND_ENABLE:
 450         case PIPE_CAP_INDEP_BLEND_FUNC:
 451                 /* R600 doesn't support per-MRT blends */
 452                 return family == CHIP_R600 ? 0 : 1;
 453
 454         /* Supported on Evergreen. */
 455         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 456         case PIPE_CAP_CUBE_MAP_ARRAY:
 457                 return family >= CHIP_CEDAR ? 1 : 0;
 458
 459         /* Unsupported features. */
 460         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 461         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 462         case PIPE_CAP_SCALED_RESOLVE:
 463         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 464         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 465         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 466         case PIPE_CAP_USER_VERTEX_BUFFERS:
 467         case PIPE_CAP_TGSI_VS_LAYER:
 468                 return 0;
 469
 470         /* Stream output. */
 471         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 472                 return rscreen->b.has_streamout ? 4 : 0;
 473         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 474                 return rscreen->b.has_streamout ? 1 : 0;
 475         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 476         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 477                 return 32*4;
 478
 479         /* Texturing. */
 480         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 481         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 482         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 483                 if (family >= CHIP_CEDAR)
 484                         return 15;
 485                 else
 486                         return 14;
 487         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 488                 return rscreen->b.info.drm_minor >= 9 ?
 489                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 490         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 491                 return 32;
 492
 493         /* Render targets. */
 494         case PIPE_CAP_MAX_RENDER_TARGETS:
 495                 /* XXX some r6xx are buggy and can only do 4 */
 496                 return 8;
 497
 498         case PIPE_CAP_MAX_VIEWPORTS:
 499                 return 1;
 500
 501         /* Timer queries, present when the clock frequency is non zero. */
 502         case PIPE_CAP_QUERY_TIME_ELAPSED:
 503                 return rscreen->b.info.r600_clock_crystal_freq != 0;
 504         case PIPE_CAP_QUERY_TIMESTAMP:
 505                 return rscreen->b.info.drm_minor >= 20 &&
 506                        rscreen->b.info.r600_clock_crystal_freq != 0;
 507
 508         case PIPE_CAP_MIN_TEXEL_OFFSET:
 509                 return -8;
 510
 511         case PIPE_CAP_MAX_TEXEL_OFFSET:
 512                 return 7;
 513
 514         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 515                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 516         case PIPE_CAP_ENDIANNESS:
 517                 return PIPE_ENDIAN_LITTLE;
 518         }
 519         return 0;
 520 }
 521
 522 static float r600_get_paramf(struct pipe_screen* pscreen,
 523                              enum pipe_capf param)
 524 {
 525         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 526         enum radeon_family family = rscreen->b.family;
 527
 528         switch (param) {
 529         case PIPE_CAPF_MAX_LINE_WIDTH:
 530         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 531         case PIPE_CAPF_MAX_POINT_WIDTH:
 532         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 533                 if (family >= CHIP_CEDAR)
 534                         return 16384.0f;
 535                 else
 536                         return 8192.0f;
 537         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 538                 return 16.0f;
 539         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 540                 return 16.0f;
 541         case PIPE_CAPF_GUARD_BAND_LEFT:
 542         case PIPE_CAPF_GUARD_BAND_TOP:
 543         case PIPE_CAPF_GUARD_BAND_RIGHT:
 544         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 545                 return 0.0f;
 546         }
 547         return 0.0f;
 548 }
 549
 550 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 551 {
 552         switch(shader)
 553         {
 554         case PIPE_SHADER_FRAGMENT:
 555         case PIPE_SHADER_VERTEX:
 556         case PIPE_SHADER_COMPUTE:
 557                 break;
 558         case PIPE_SHADER_GEOMETRY:
 559                 /* XXX: support and enable geometry programs */
 560                 return 0;
 561         default:
 562                 /* XXX: support tessellation on Evergreen */
 563                 return 0;
 564         }
 565
 566         switch (param) {
 567         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 568         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 569         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 570         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 571                 return 16384;
 572         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 573                 return 32;
 574         case PIPE_SHADER_CAP_MAX_INPUTS:
 575                 return 32;
 576         case PIPE_SHADER_CAP_MAX_TEMPS:
 577                 return 256; /* Max native temporaries. */
 578         case PIPE_SHADER_CAP_MAX_ADDRS:
 579                 /* XXX Isn't this equal to TEMPS? */
 580                 return 1; /* Max native address registers */
 581         case PIPE_SHADER_CAP_MAX_CONSTS:
 582                 return R600_MAX_CONST_BUFFER_SIZE;
 583         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 584                 return R600_MAX_USER_CONST_BUFFERS;
 585         case PIPE_SHADER_CAP_MAX_PREDS:
 586                 return 0; /* nothing uses this */
 587         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 588                 return 1;
 589         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 590                 return 0;
 591         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 592         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 593         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 594         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 595                 return 1;
 596         case PIPE_SHADER_CAP_SUBROUTINES:
 597                 return 0;
 598         case PIPE_SHADER_CAP_INTEGERS:
 599                 return 1;
 600         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 601         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 602                 return 16;
 603         case PIPE_SHADER_CAP_PREFERRED_IR:
 604                 if (shader == PIPE_SHADER_COMPUTE) {
 605                         return PIPE_SHADER_IR_LLVM;
 606                 } else {
 607                         return PIPE_SHADER_IR_TGSI;
 608                 }
 609         }
 610         return 0;
 611 }
 612
 613 static int r600_get_video_param(struct pipe_screen *screen,
 614                                 enum pipe_video_profile profile,
 615                                 enum pipe_video_entrypoint entrypoint,
 616                                 enum pipe_video_cap param)
 617 {
 618         switch (param) {
 619         case PIPE_VIDEO_CAP_SUPPORTED:
 620                 return vl_profile_supported(screen, profile, entrypoint);
 621         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 622                 return 1;
 623         case PIPE_VIDEO_CAP_MAX_WIDTH:
 624         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 625                 return vl_video_buffer_max_size(screen);
 626         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 627                 return PIPE_FORMAT_NV12;
 628         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 629                 return false;
 630         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 631                 return false;
 632         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 633                 return true;
 634         case PIPE_VIDEO_CAP_MAX_LEVEL:
 635                 return vl_level_supported(screen, profile);
 636         default:
 637                 return 0;
 638         }
 639 }
 640
 641 const char * r600_llvm_gpu_string(enum radeon_family family)
 642 {
 643         const char * gpu_family;
 644
 645         switch (family) {
 646         case CHIP_R600:
 647         case CHIP_RV630:
 648         case CHIP_RV635:
 649         case CHIP_RV670:
 650                 gpu_family = "r600";
 651                 break;
 652         case CHIP_RV610:
 653         case CHIP_RV620:
 654         case CHIP_RS780:
 655         case CHIP_RS880:
 656                 gpu_family = "rs880";
 657                 break;
 658         case CHIP_RV710:
 659                 gpu_family = "rv710";
 660                 break;
 661         case CHIP_RV730:
 662                 gpu_family = "rv730";
 663                 break;
 664         case CHIP_RV740:
 665         case CHIP_RV770:
 666                 gpu_family = "rv770";
 667                 break;
 668         case CHIP_PALM:
 669         case CHIP_CEDAR:
 670                 gpu_family = "cedar";
 671                 break;
 672         case CHIP_SUMO:
 673         case CHIP_SUMO2:
 674                 gpu_family = "sumo";
 675                 break;
 676         case CHIP_REDWOOD:
 677                 gpu_family = "redwood";
 678                 break;
 679         case CHIP_JUNIPER:
 680                 gpu_family = "juniper";
 681                 break;
 682         case CHIP_HEMLOCK:
 683         case CHIP_CYPRESS:
 684                 gpu_family = "cypress";
 685                 break;
 686         case CHIP_BARTS:
 687                 gpu_family = "barts";
 688                 break;
 689         case CHIP_TURKS:
 690                 gpu_family = "turks";
 691                 break;
 692         case CHIP_CAICOS:
 693                 gpu_family = "caicos";
 694                 break;
 695         case CHIP_CAYMAN:
 696         case CHIP_ARUBA:
 697                 gpu_family = "cayman";
 698                 break;
 699         default:
 700                 gpu_family = "";
 701                 fprintf(stderr, "Chip not supported by r600 llvm "
 702                         "backend, please file a bug at " PACKAGE_BUGREPORT "\n");
 703                 break;
 704         }
 705         return gpu_family;
 706 }
 707
 708
 709 static int r600_get_compute_param(struct pipe_screen *screen,
 710         enum pipe_compute_cap param,
 711         void *ret)
 712 {
 713         struct r600_screen *rscreen = (struct r600_screen *)screen;
 714         //TODO: select these params by asic
 715         switch (param) {
 716         case PIPE_COMPUTE_CAP_IR_TARGET: {
 717                 const char *gpu = r600_llvm_gpu_string(rscreen->b.family);
 718                 if (ret) {
 719                         sprintf(ret, "%s-r600--", gpu);
 720                 }
 721                 return (8 + strlen(gpu)) * sizeof(char);
 722         }
 723         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 724                 if (ret) {
 725                         uint64_t * grid_dimension = ret;
 726                         grid_dimension[0] = 3;
 727                 }
 728                 return 1 * sizeof(uint64_t);
 729
 730         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 731                 if (ret) {
 732                         uint64_t * grid_size = ret;
 733                         grid_size[0] = 65535;
 734                         grid_size[1] = 65535;
 735                         grid_size[2] = 1;
 736                 }
 737                 return 3 * sizeof(uint64_t) ;
 738
 739         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 740                 if (ret) {
 741                         uint64_t * block_size = ret;
 742                         block_size[0] = 256;
 743                         block_size[1] = 256;
 744                         block_size[2] = 256;
 745                 }
 746                 return 3 * sizeof(uint64_t);
 747
 748         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 749                 if (ret) {
 750                         uint64_t * max_threads_per_block = ret;
 751                         *max_threads_per_block = 256;
 752                 }
 753                 return sizeof(uint64_t);
 754
 755         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 756                 if (ret) {
 757                         uint64_t * max_global_size = ret;
 758                         /* XXX: This is what the proprietary driver reports, we
 759                          * may want to use a different value. */
 760                         *max_global_size = 201326592;
 761                 }
 762                 return sizeof(uint64_t);
 763
 764         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 765                 if (ret) {
 766                         uint64_t * max_input_size = ret;
 767                         *max_input_size = 1024;
 768                 }
 769                 return sizeof(uint64_t);
 770
 771         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 772                 if (ret) {
 773                         uint64_t * max_local_size = ret;
 774                         /* XXX: This is what the proprietary driver reports, we
 775                          * may want to use a different value. */
 776                         *max_local_size = 32768;
 777                 }
 778                 return sizeof(uint64_t);
 779
 780         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 781                 if (ret) {
 782                         uint64_t max_global_size;
 783                         uint64_t * max_mem_alloc_size = ret;
 784                         r600_get_compute_param(screen,
 785                                         PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
 786                                         &max_global_size);
 787                         /* OpenCL requres this value be at least
 788                          * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
 789                          * I'm really not sure what value to report here, but
 790                          * MAX_GLOBAL_SIZE / 4 seems resonable.
 791                          */
 792                         *max_mem_alloc_size = max_global_size / 4;
 793                 }
 794                 return sizeof(uint64_t);
 795
 796         default:
 797                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 798                 return 0;
 799         }
 800 }
 801
 802 static void r600_destroy_screen(struct pipe_screen* pscreen)
 803 {
 804         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 805
 806         if (rscreen == NULL)
 807                 return;
 808
 809         if (!radeon_winsys_unref(rscreen->b.ws))
 810                 return;
 811
 812         r600_common_screen_cleanup(&rscreen->b);
 813
 814         if (rscreen->global_pool) {
 815                 compute_memory_pool_delete(rscreen->global_pool);
 816         }
 817
 818         if (rscreen->trace_bo) {
 819                 rscreen->b.ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 820                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 821         }
 822
 823         rscreen->b.ws->destroy(rscreen->b.ws);
 824         FREE(rscreen);
 825 }
 826
 827 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 828 {
 829         struct r600_screen *rscreen = (struct r600_screen*)screen;
 830
 831         return 1000000 * rscreen->b.ws->query_value(rscreen->b.ws, RADEON_TIMESTAMP) /
 832                         rscreen->b.info.r600_clock_crystal_freq;
 833 }
 834
 835 static int r600_get_driver_query_info(struct pipe_screen *screen,
 836                                       unsigned index,
 837                                       struct pipe_driver_query_info *info)
 838 {
 839         struct r600_screen *rscreen = (struct r600_screen*)screen;
 840         struct pipe_driver_query_info list[] = {
 841                 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
 842                 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->b.info.vram_size, TRUE},
 843                 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->b.info.gart_size, TRUE},
 844                 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE}
 845         };
 846
 847         if (!info)
 848                 return Elements(list);
 849
 850         if (index >= Elements(list))
 851                 return 0;
 852
 853         *info = list[index];
 854         return 1;
 855 }
 856
 857 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 858 {
 859         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 860
 861         if (rscreen == NULL) {
 862                 return NULL;
 863         }
 864
 865         ws->query_info(ws, &rscreen->b.info);
 866
 867         /* Set functions first. */
 868         rscreen->b.b.context_create = r600_create_context;
 869         rscreen->b.b.destroy = r600_destroy_screen;
 870         rscreen->b.b.get_name = r600_get_name;
 871         rscreen->b.b.get_vendor = r600_get_vendor;
 872         rscreen->b.b.get_param = r600_get_param;
 873         rscreen->b.b.get_shader_param = r600_get_shader_param;
 874         rscreen->b.b.get_paramf = r600_get_paramf;
 875         rscreen->b.b.get_compute_param = r600_get_compute_param;
 876         rscreen->b.b.get_timestamp = r600_get_timestamp;
 877         if (rscreen->b.info.chip_class >= EVERGREEN) {
 878                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 879         } else {
 880                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 881         }
 882         rscreen->b.b.get_driver_query_info = r600_get_driver_query_info;
 883         if (rscreen->b.info.has_uvd) {
 884                 rscreen->b.b.get_video_param = ruvd_get_video_param;
 885                 rscreen->b.b.is_video_format_supported = ruvd_is_format_supported;
 886         } else {
 887                 rscreen->b.b.get_video_param = r600_get_video_param;
 888                 rscreen->b.b.is_video_format_supported = vl_video_buffer_is_format_supported;
 889         }
 890         r600_init_screen_resource_functions(&rscreen->b.b);
 891
 892         if (!r600_common_screen_init(&rscreen->b, ws)) {
 893                 FREE(rscreen);
 894                 return NULL;
 895         }
 896
 897         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 898         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 899                 rscreen->b.debug_flags |= DBG_COMPUTE;
 900         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 901                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 902         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
 903                 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
 904         if (!debug_get_bool_option("R600_LLVM", TRUE))
 905                 rscreen->b.debug_flags |= DBG_NO_LLVM;
 906
 907         if (rscreen->b.family == CHIP_UNKNOWN) {
 908                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 909                 FREE(rscreen);
 910                 return NULL;
 911         }
 912
 913         /* Figure out streamout kernel support. */
 914         switch (rscreen->b.chip_class) {
 915         case R600:
 916                 if (rscreen->b.family < CHIP_RS780) {
 917                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 918                 } else {
 919                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 920                 }
 921                 break;
 922         case R700:
 923                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 924                 break;
 925         case EVERGREEN:
 926         case CAYMAN:
 927                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 928                 break;
 929         default:
 930                 rscreen->b.has_streamout = FALSE;
 931                 break;
 932         }
 933
 934         /* MSAA support. */
 935         switch (rscreen->b.chip_class) {
 936         case R600:
 937         case R700:
 938                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 939                 rscreen->has_compressed_msaa_texturing = false;
 940                 break;
 941         case EVERGREEN:
 942                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 943                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 944                 break;
 945         case CAYMAN:
 946                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 947                 rscreen->has_compressed_msaa_texturing = true;
 948                 break;
 949         default:
 950                 rscreen->has_msaa = FALSE;
 951                 rscreen->has_compressed_msaa_texturing = false;
 952         }
 953
 954         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 955                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 956
 957         rscreen->global_pool = compute_memory_pool_new(rscreen);
 958
 959         rscreen->cs_count = 0;
 960         if (rscreen->b.info.drm_minor >= 28 && (rscreen->b.debug_flags & DBG_TRACE_CS)) {
 961                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b.b,
 962                                                                                 PIPE_BIND_CUSTOM,
 963                                                                                 PIPE_USAGE_STAGING,
 964                                                                                 4096);
 965                 if (rscreen->trace_bo) {
 966                         rscreen->trace_ptr = rscreen->b.ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 967                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 968                 }
 969         }
 970
 971         /* Create the auxiliary context. This must be done last. */
 972         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
 973
 974 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 975         struct pipe_resource templ = {};
 976
 977         templ.width0 = 4;
 978         templ.height0 = 2048;
 979         templ.depth0 = 1;
 980         templ.array_size = 1;
 981         templ.target = PIPE_TEXTURE_2D;
 982         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 983         templ.usage = PIPE_USAGE_STATIC;
 984
 985         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 986         unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
 987
 988         memset(map, 0, 256);
 989
 990         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 991         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 992         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 993         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 994         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 995
 996         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 997
 998         int i;
 999         for (i = 0; i < 256; i++) {
1000                 printf("%02X", map[i]);
1001                 if (i % 16 == 15)
1002                         printf("\n");
1003         }
1004 #endif
1005
1006         return &rscreen->b.b;
1007 }