src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_blitter.h"
  34 #include "util/u_debug.h"
  35 #include "util/u_memory.h"
  36 #include "util/u_simple_shaders.h"
  37 #include "util/u_upload_mgr.h"
  38 #include "util/u_math.h"
  39 #include "vl/vl_decoder.h"
  40 #include "vl/vl_video_buffer.h"
  41 #include "radeon/radeon_video.h"
  42 #include "radeon/radeon_uvd.h"
  43 #include "os/os_time.h"
  44
  45 static const struct debug_named_value r600_debug_options[] = {
  46         /* features */
  47 #if defined(R600_USE_LLVM)
  48         { "llvm", DBG_LLVM, "Enable the LLVM shader compiler" },
  49 #endif
  50         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  51
  52         /* shader backend */
  53         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  54         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  55         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  56         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  57         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  58         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  59         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  60         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  61
  62         DEBUG_NAMED_VALUE_END /* must be last */
  63 };
  64
  65 /*
  66  * pipe_context
  67  */
  68
  69 static void r600_destroy_context(struct pipe_context *context)
  70 {
  71         struct r600_context *rctx = (struct r600_context *)context;
  72
  73         r600_isa_destroy(rctx->isa);
  74
  75         r600_sb_context_destroy(rctx->sb_context);
  76
  77         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
  78         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
  79
  80         if (rctx->dummy_pixel_shader) {
  81                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
  82         }
  83         if (rctx->custom_dsa_flush) {
  84                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
  85         }
  86         if (rctx->custom_blend_resolve) {
  87                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
  88         }
  89         if (rctx->custom_blend_decompress) {
  90                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
  91         }
  92         if (rctx->custom_blend_fastclear) {
  93                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
  94         }
  95         util_unreference_framebuffer_state(&rctx->framebuffer.state);
  96
  97         if (rctx->blitter) {
  98                 util_blitter_destroy(rctx->blitter);
  99         }
 100         if (rctx->allocator_fetch_shader) {
 101                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 102         }
 103
 104         r600_release_command_buffer(&rctx->start_cs_cmd);
 105
 106         FREE(rctx->start_compute_cs_cmd.buf);
 107
 108         r600_common_context_cleanup(&rctx->b);
 109         FREE(rctx);
 110 }
 111
 112 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 113 {
 114         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 115         struct r600_screen* rscreen = (struct r600_screen *)screen;
 116         struct radeon_winsys *ws = rscreen->b.ws;
 117
 118         if (rctx == NULL)
 119                 return NULL;
 120
 121         rctx->b.b.screen = screen;
 122         rctx->b.b.priv = priv;
 123         rctx->b.b.destroy = r600_destroy_context;
 124
 125         if (!r600_common_context_init(&rctx->b, &rscreen->b))
 126                 goto fail;
 127
 128         rctx->screen = rscreen;
 129         rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
 130
 131         r600_init_blit_functions(rctx);
 132
 133         if (rscreen->b.info.has_uvd) {
 134                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 135                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 136         } else {
 137                 rctx->b.b.create_video_codec = vl_create_decoder;
 138                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 139         }
 140
 141         r600_init_common_state_functions(rctx);
 142
 143         switch (rctx->b.chip_class) {
 144         case R600:
 145         case R700:
 146                 r600_init_state_functions(rctx);
 147                 r600_init_atom_start_cs(rctx);
 148                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 149                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 150                                                                       : r600_create_resolve_blend(rctx);
 151                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 152                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 153                                            rctx->b.family == CHIP_RV620 ||
 154                                            rctx->b.family == CHIP_RS780 ||
 155                                            rctx->b.family == CHIP_RS880 ||
 156                                            rctx->b.family == CHIP_RV710);
 157                 break;
 158         case EVERGREEN:
 159         case CAYMAN:
 160                 evergreen_init_state_functions(rctx);
 161                 evergreen_init_atom_start_cs(rctx);
 162                 evergreen_init_atom_start_compute_cs(rctx);
 163                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 164                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 165                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 166                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 167                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 168                                            rctx->b.family == CHIP_PALM ||
 169                                            rctx->b.family == CHIP_SUMO ||
 170                                            rctx->b.family == CHIP_SUMO2 ||
 171                                            rctx->b.family == CHIP_CAICOS ||
 172                                            rctx->b.family == CHIP_CAYMAN ||
 173                                            rctx->b.family == CHIP_ARUBA);
 174                 break;
 175         default:
 176                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 177                 goto fail;
 178         }
 179
 180         rctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX,
 181                                              r600_context_gfx_flush, rctx,
 182                                              rscreen->b.trace_bo ?
 183                                                      rscreen->b.trace_bo->cs_buf : NULL);
 184         rctx->b.rings.gfx.flush = r600_context_gfx_flush;
 185
 186         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
 187                                                              0, PIPE_USAGE_DEFAULT, FALSE);
 188         if (!rctx->allocator_fetch_shader)
 189                 goto fail;
 190
 191         rctx->isa = calloc(1, sizeof(struct r600_isa));
 192         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 193                 goto fail;
 194
 195         rctx->blitter = util_blitter_create(&rctx->b.b);
 196         if (rctx->blitter == NULL)
 197                 goto fail;
 198         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 199         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 200
 201         r600_begin_new_cs(rctx);
 202         r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
 203
 204         rctx->dummy_pixel_shader =
 205                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 206                                                      TGSI_SEMANTIC_GENERIC,
 207                                                      TGSI_INTERPOLATE_CONSTANT);
 208         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 209
 210         return &rctx->b.b;
 211
 212 fail:
 213         r600_destroy_context(&rctx->b.b);
 214         return NULL;
 215 }
 216
 217 /*
 218  * pipe_screen
 219  */
 220
 221 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 222 {
 223         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 224         enum radeon_family family = rscreen->b.family;
 225
 226         switch (param) {
 227         /* Supported features (boolean caps). */
 228         case PIPE_CAP_NPOT_TEXTURES:
 229         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 230         case PIPE_CAP_TWO_SIDED_STENCIL:
 231         case PIPE_CAP_ANISOTROPIC_FILTER:
 232         case PIPE_CAP_POINT_SPRITE:
 233         case PIPE_CAP_OCCLUSION_QUERY:
 234         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 235         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 236         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 237         case PIPE_CAP_TEXTURE_SWIZZLE:
 238         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 239         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 240         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 241         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 242         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 243         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 244         case PIPE_CAP_SM3:
 245         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 246         case PIPE_CAP_PRIMITIVE_RESTART:
 247         case PIPE_CAP_CONDITIONAL_RENDER:
 248         case PIPE_CAP_TEXTURE_BARRIER:
 249         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 250         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 251         case PIPE_CAP_TGSI_INSTANCEID:
 252         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 253         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 254         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 255         case PIPE_CAP_USER_INDEX_BUFFERS:
 256         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 257         case PIPE_CAP_START_INSTANCE:
 258         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 259         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 260         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 261         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 262         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 263         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 264                 return 1;
 265
 266         case PIPE_CAP_COMPUTE:
 267                 return rscreen->b.chip_class > R700;
 268
 269         case PIPE_CAP_TGSI_TEXCOORD:
 270                 return 0;
 271
 272         case PIPE_CAP_FAKE_SW_MSAA:
 273                 return 0;
 274
 275         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 276                 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
 277
 278         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 279                 return R600_MAP_BUFFER_ALIGNMENT;
 280
 281         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 282                 return 256;
 283
 284         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 285                 return 1;
 286
 287         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 288                 if (family >= CHIP_CEDAR)
 289                    return 330;
 290                 /* pre-evergreen geom shaders need newer kernel */
 291                 if (rscreen->b.info.drm_minor >= 37)
 292                    return 330;
 293                 return 140;
 294
 295         /* Supported except the original R600. */
 296         case PIPE_CAP_INDEP_BLEND_ENABLE:
 297         case PIPE_CAP_INDEP_BLEND_FUNC:
 298                 /* R600 doesn't support per-MRT blends */
 299                 return family == CHIP_R600 ? 0 : 1;
 300
 301         /* Supported on Evergreen. */
 302         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 303         case PIPE_CAP_CUBE_MAP_ARRAY:
 304         case PIPE_CAP_TGSI_VS_LAYER:
 305                 return family >= CHIP_CEDAR ? 1 : 0;
 306
 307         /* Unsupported features. */
 308         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 309         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 310         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 311         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 312         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 313         case PIPE_CAP_USER_VERTEX_BUFFERS:
 314         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 315         case PIPE_CAP_TEXTURE_GATHER_SM5:
 316         case PIPE_CAP_TEXTURE_QUERY_LOD:
 317         case PIPE_CAP_SAMPLE_SHADING:
 318                 return 0;
 319
 320         /* Stream output. */
 321         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 322                 return rscreen->b.has_streamout ? 4 : 0;
 323         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 324                 return rscreen->b.has_streamout ? 1 : 0;
 325         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 326         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 327                 return 32*4;
 328
 329         /* Geometry shader output. */
 330         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 331                 return 1024;
 332         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 333                 return 16384;
 334
 335         /* Texturing. */
 336         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 337         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 338                 if (family >= CHIP_CEDAR)
 339                         return 15;
 340                 else
 341                         return 14;
 342         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 343                 /* textures support 8192, but layered rendering supports 2048 */
 344                 return 12;
 345         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 346                 /* textures support 8192, but layered rendering supports 2048 */
 347                 return rscreen->b.info.drm_minor >= 9 ? 2048 : 0;
 348
 349         /* Render targets. */
 350         case PIPE_CAP_MAX_RENDER_TARGETS:
 351                 /* XXX some r6xx are buggy and can only do 4 */
 352                 return 8;
 353
 354         case PIPE_CAP_MAX_VIEWPORTS:
 355                 return 16;
 356
 357         /* Timer queries, present when the clock frequency is non zero. */
 358         case PIPE_CAP_QUERY_TIME_ELAPSED:
 359                 return rscreen->b.info.r600_clock_crystal_freq != 0;
 360         case PIPE_CAP_QUERY_TIMESTAMP:
 361                 return rscreen->b.info.drm_minor >= 20 &&
 362                        rscreen->b.info.r600_clock_crystal_freq != 0;
 363
 364         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 365         case PIPE_CAP_MIN_TEXEL_OFFSET:
 366                 return -8;
 367
 368         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 369         case PIPE_CAP_MAX_TEXEL_OFFSET:
 370                 return 7;
 371
 372         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 373                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 374         case PIPE_CAP_ENDIANNESS:
 375                 return PIPE_ENDIAN_LITTLE;
 376         }
 377         return 0;
 378 }
 379
 380 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 381 {
 382         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 383
 384         switch(shader)
 385         {
 386         case PIPE_SHADER_FRAGMENT:
 387         case PIPE_SHADER_VERTEX:
 388         case PIPE_SHADER_COMPUTE:
 389                 break;
 390         case PIPE_SHADER_GEOMETRY:
 391                 if (rscreen->b.family >= CHIP_CEDAR)
 392                         break;
 393                 /* pre-evergreen geom shaders need newer kernel */
 394                 if (rscreen->b.info.drm_minor >= 37)
 395                         break;
 396                 return 0;
 397         default:
 398                 /* XXX: support tessellation on Evergreen */
 399                 return 0;
 400         }
 401
 402         switch (param) {
 403         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 404         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 405         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 406         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 407                 return 16384;
 408         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 409                 return 32;
 410         case PIPE_SHADER_CAP_MAX_INPUTS:
 411                 return 32;
 412         case PIPE_SHADER_CAP_MAX_TEMPS:
 413                 return 256; /* Max native temporaries. */
 414         case PIPE_SHADER_CAP_MAX_ADDRS:
 415                 /* XXX Isn't this equal to TEMPS? */
 416                 return 1; /* Max native address registers */
 417         case PIPE_SHADER_CAP_MAX_CONSTS:
 418                 return R600_MAX_CONST_BUFFER_SIZE;
 419         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 420                 return R600_MAX_USER_CONST_BUFFERS;
 421         case PIPE_SHADER_CAP_MAX_PREDS:
 422                 return 0; /* nothing uses this */
 423         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 424                 return 1;
 425         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 426                 return 0;
 427         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 428         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 429         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 430         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 431                 return 1;
 432         case PIPE_SHADER_CAP_SUBROUTINES:
 433                 return 0;
 434         case PIPE_SHADER_CAP_INTEGERS:
 435                 return 1;
 436         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 437         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 438                 return 16;
 439         case PIPE_SHADER_CAP_PREFERRED_IR:
 440                 if (shader == PIPE_SHADER_COMPUTE) {
 441                         return PIPE_SHADER_IR_LLVM;
 442                 } else {
 443                         return PIPE_SHADER_IR_TGSI;
 444                 }
 445         }
 446         return 0;
 447 }
 448
 449 static void r600_destroy_screen(struct pipe_screen* pscreen)
 450 {
 451         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 452
 453         if (rscreen == NULL)
 454                 return;
 455
 456         if (!rscreen->b.ws->unref(rscreen->b.ws))
 457                 return;
 458
 459         if (rscreen->global_pool) {
 460                 compute_memory_pool_delete(rscreen->global_pool);
 461         }
 462
 463         r600_destroy_common_screen(&rscreen->b);
 464 }
 465
 466 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 467                                                   const struct pipe_resource *templ)
 468 {
 469         if (templ->target == PIPE_BUFFER &&
 470             (templ->bind & PIPE_BIND_GLOBAL))
 471                 return r600_compute_global_buffer_create(screen, templ);
 472
 473         return r600_resource_create_common(screen, templ);
 474 }
 475
 476 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 477 {
 478         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 479
 480         if (rscreen == NULL) {
 481                 return NULL;
 482         }
 483
 484         /* Set functions first. */
 485         rscreen->b.b.context_create = r600_create_context;
 486         rscreen->b.b.destroy = r600_destroy_screen;
 487         rscreen->b.b.get_param = r600_get_param;
 488         rscreen->b.b.get_shader_param = r600_get_shader_param;
 489         rscreen->b.b.resource_create = r600_resource_create;
 490
 491         if (!r600_common_screen_init(&rscreen->b, ws)) {
 492                 FREE(rscreen);
 493                 return NULL;
 494         }
 495
 496         if (rscreen->b.info.chip_class >= EVERGREEN) {
 497                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 498         } else {
 499                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 500         }
 501
 502         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 503         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 504                 rscreen->b.debug_flags |= DBG_COMPUTE;
 505         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 506                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 507         if (debug_get_bool_option("R600_HYPERZ", FALSE))
 508                 rscreen->b.debug_flags |= DBG_HYPERZ;
 509         if (debug_get_bool_option("R600_LLVM", FALSE))
 510                 rscreen->b.debug_flags |= DBG_LLVM;
 511
 512         if (rscreen->b.family == CHIP_UNKNOWN) {
 513                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 514                 FREE(rscreen);
 515                 return NULL;
 516         }
 517
 518         /* Figure out streamout kernel support. */
 519         switch (rscreen->b.chip_class) {
 520         case R600:
 521                 if (rscreen->b.family < CHIP_RS780) {
 522                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 523                 } else {
 524                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 525                 }
 526                 break;
 527         case R700:
 528                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 529                 break;
 530         case EVERGREEN:
 531         case CAYMAN:
 532                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 533                 break;
 534         default:
 535                 rscreen->b.has_streamout = FALSE;
 536                 break;
 537         }
 538
 539         /* MSAA support. */
 540         switch (rscreen->b.chip_class) {
 541         case R600:
 542         case R700:
 543                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 544                 rscreen->has_compressed_msaa_texturing = false;
 545                 break;
 546         case EVERGREEN:
 547                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 548                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 549                 break;
 550         case CAYMAN:
 551                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 552                 rscreen->has_compressed_msaa_texturing = true;
 553                 break;
 554         default:
 555                 rscreen->has_msaa = FALSE;
 556                 rscreen->has_compressed_msaa_texturing = false;
 557         }
 558
 559         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 560                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 561
 562         rscreen->global_pool = compute_memory_pool_new(rscreen);
 563
 564         /* Create the auxiliary context. This must be done last. */
 565         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
 566
 567 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 568         struct pipe_resource templ = {};
 569
 570         templ.width0 = 4;
 571         templ.height0 = 2048;
 572         templ.depth0 = 1;
 573         templ.array_size = 1;
 574         templ.target = PIPE_TEXTURE_2D;
 575         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 576         templ.usage = PIPE_USAGE_DEFAULT;
 577
 578         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 579         unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
 580
 581         memset(map, 0, 256);
 582
 583         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 584         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 585         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 586         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 587         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 588
 589         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 590
 591         int i;
 592         for (i = 0; i < 256; i++) {
 593                 printf("%02X", map[i]);
 594                 if (i % 16 == 15)
 595                         printf("\n");
 596         }
 597 #endif
 598
 599         return &rscreen->b.b;
 600 }