src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25
  26 #include <errno.h>
  27 #include "pipe/p_shader_tokens.h"
  28 #include "util/u_blitter.h"
  29 #include "util/u_format_s3tc.h"
  30 #include "util/u_simple_shaders.h"
  31 #include "util/u_upload_mgr.h"
  32 #include "vl/vl_decoder.h"
  33 #include "vl/vl_video_buffer.h"
  34 #include "os/os_time.h"
  35
  36 /*
  37  * pipe_context
  38  */
  39 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  40 {
  41         struct r600_screen *rscreen = rctx->screen;
  42         struct r600_fence *fence = NULL;
  43
  44         pipe_mutex_lock(rscreen->fences.mutex);
  45
  46         if (!rscreen->fences.bo) {
  47                 /* Create the shared buffer object */
  48                 rscreen->fences.bo = (struct r600_resource*)
  49                         pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
  50                                            PIPE_USAGE_STAGING, 4096);
  51                 if (!rscreen->fences.bo) {
  52                         R600_ERR("r600: failed to create bo for fence objects\n");
  53                         goto out;
  54                 }
  55                 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf,
  56                                                            rctx->cs,
  57                                                            PIPE_TRANSFER_READ_WRITE);
  58         }
  59
  60         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  61                 struct r600_fence *entry;
  62
  63                 /* Try to find a freed fence that has been signalled */
  64                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  65                         if (rscreen->fences.data[entry->index] != 0) {
  66                                 LIST_DELINIT(&entry->head);
  67                                 fence = entry;
  68                                 break;
  69                         }
  70                 }
  71         }
  72
  73         if (!fence) {
  74                 /* Allocate a new fence */
  75                 struct r600_fence_block *block;
  76                 unsigned index;
  77
  78                 if ((rscreen->fences.next_index + 1) >= 1024) {
  79                         R600_ERR("r600: too many concurrent fences\n");
  80                         goto out;
  81                 }
  82
  83                 index = rscreen->fences.next_index++;
  84
  85                 if (!(index % FENCE_BLOCK_SIZE)) {
  86                         /* Allocate a new block */
  87                         block = CALLOC_STRUCT(r600_fence_block);
  88                         if (block == NULL)
  89                                 goto out;
  90
  91                         LIST_ADD(&block->head, &rscreen->fences.blocks);
  92                 } else {
  93                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
  94                 }
  95
  96                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
  97                 fence->index = index;
  98         }
  99
 100         pipe_reference_init(&fence->reference, 1);
 101
 102         rscreen->fences.data[fence->index] = 0;
 103         r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 104
 105         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 106         fence->sleep_bo = (struct r600_resource*)
 107                         pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
 108                                            PIPE_USAGE_STAGING, 1);
 109         /* Add the fence as a dummy relocation. */
 110         r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 111
 112 out:
 113         pipe_mutex_unlock(rscreen->fences.mutex);
 114         return fence;
 115 }
 116
 117
 118 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 119                 unsigned flags)
 120 {
 121         struct r600_context *rctx = (struct r600_context *)ctx;
 122         struct r600_fence **rfence = (struct r600_fence**)fence;
 123         struct pipe_query *render_cond = NULL;
 124         unsigned render_cond_mode = 0;
 125
 126         if (rfence)
 127                 *rfence = r600_create_fence(rctx);
 128
 129         /* Disable render condition. */
 130         if (rctx->current_render_cond) {
 131                 render_cond = rctx->current_render_cond;
 132                 render_cond_mode = rctx->current_render_cond_mode;
 133                 ctx->render_condition(ctx, NULL, 0);
 134         }
 135
 136         r600_context_flush(rctx, flags);
 137
 138         /* Re-enable render condition. */
 139         if (render_cond) {
 140                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 141         }
 142 }
 143
 144 static void r600_flush_from_st(struct pipe_context *ctx,
 145                                struct pipe_fence_handle **fence)
 146 {
 147         r600_flush(ctx, fence, 0);
 148 }
 149
 150 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 151 {
 152         r600_flush((struct pipe_context*)ctx, NULL, flags);
 153 }
 154
 155 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
 156 {
 157         pipe_mutex_lock(rscreen->mutex_num_contexts);
 158         if (diff > 0) {
 159                 rscreen->num_contexts++;
 160
 161                 if (rscreen->num_contexts > 1)
 162                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 163                                                     UTIL_SLAB_MULTITHREADED);
 164         } else {
 165                 rscreen->num_contexts--;
 166
 167                 if (rscreen->num_contexts <= 1)
 168                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 169                                                     UTIL_SLAB_SINGLETHREADED);
 170         }
 171         pipe_mutex_unlock(rscreen->mutex_num_contexts);
 172 }
 173
 174 static void r600_destroy_context(struct pipe_context *context)
 175 {
 176         struct r600_context *rctx = (struct r600_context *)context;
 177
 178         if (rctx->dummy_pixel_shader) {
 179                 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 180         }
 181         if (rctx->custom_dsa_flush) {
 182                 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 183         }
 184         util_unreference_framebuffer_state(&rctx->framebuffer);
 185
 186         r600_context_fini(rctx);
 187
 188         if (rctx->blitter) {
 189                 util_blitter_destroy(rctx->blitter);
 190         }
 191         for (int i = 0; i < R600_PIPE_NSTATES; i++) {
 192                 free(rctx->states[i]);
 193         }
 194
 195         if (rctx->uploader) {
 196                 u_upload_destroy(rctx->uploader);
 197         }
 198         util_slab_destroy(&rctx->pool_transfers);
 199
 200         r600_update_num_contexts(rctx->screen, -1);
 201
 202         r600_release_command_buffer(&rctx->start_cs_cmd);
 203
 204         if (rctx->cs) {
 205                 rctx->ws->cs_destroy(rctx->cs);
 206         }
 207
 208         FREE(rctx->range);
 209         FREE(rctx);
 210 }
 211
 212 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 213 {
 214         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 215         struct r600_screen* rscreen = (struct r600_screen *)screen;
 216
 217         if (rctx == NULL)
 218                 return NULL;
 219
 220         util_slab_create(&rctx->pool_transfers,
 221                          sizeof(struct pipe_transfer), 64,
 222                          UTIL_SLAB_SINGLETHREADED);
 223
 224         r600_update_num_contexts(rscreen, 1);
 225
 226         rctx->context.screen = screen;
 227         rctx->context.priv = priv;
 228         rctx->context.destroy = r600_destroy_context;
 229         rctx->context.flush = r600_flush_from_st;
 230
 231         /* Easy accessing of screen/winsys. */
 232         rctx->screen = rscreen;
 233         rctx->ws = rscreen->ws;
 234         rctx->family = rscreen->family;
 235         rctx->chip_class = rscreen->chip_class;
 236
 237         LIST_INITHEAD(&rctx->dirty_states);
 238         LIST_INITHEAD(&rctx->active_timer_queries);
 239         LIST_INITHEAD(&rctx->active_nontimer_queries);
 240         LIST_INITHEAD(&rctx->dirty);
 241         LIST_INITHEAD(&rctx->resource_dirty);
 242         LIST_INITHEAD(&rctx->enable_list);
 243
 244         rctx->range = CALLOC(NUM_RANGES, sizeof(struct r600_range));
 245         if (!rctx->range)
 246                 goto fail;
 247
 248         r600_init_blit_functions(rctx);
 249         r600_init_query_functions(rctx);
 250         r600_init_context_resource_functions(rctx);
 251         r600_init_surface_functions(rctx);
 252         rctx->context.draw_vbo = r600_draw_vbo;
 253
 254         rctx->context.create_video_decoder = vl_create_decoder;
 255         rctx->context.create_video_buffer = vl_video_buffer_create;
 256
 257         r600_init_common_atoms(rctx);
 258
 259         switch (rctx->chip_class) {
 260         case R600:
 261         case R700:
 262                 r600_init_state_functions(rctx);
 263                 r600_init_atom_start_cs(rctx);
 264                 if (r600_context_init(rctx))
 265                         goto fail;
 266                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 267                 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
 268                                            rctx->family == CHIP_RV620 ||
 269                                            rctx->family == CHIP_RS780 ||
 270                                            rctx->family == CHIP_RS880 ||
 271                                            rctx->family == CHIP_RV710);
 272                 break;
 273         case EVERGREEN:
 274         case CAYMAN:
 275                 evergreen_init_state_functions(rctx);
 276                 evergreen_init_atom_start_cs(rctx);
 277                 if (evergreen_context_init(rctx))
 278                         goto fail;
 279                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 280                 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
 281                                            rctx->family == CHIP_PALM ||
 282                                            rctx->family == CHIP_SUMO ||
 283                                            rctx->family == CHIP_SUMO2 ||
 284                                            rctx->family == CHIP_CAICOS ||
 285                                            rctx->family == CHIP_CAYMAN ||
 286                                            rctx->family == CHIP_ARUBA);
 287                 break;
 288         default:
 289                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 290                 goto fail;
 291         }
 292
 293         rctx->cs = rctx->ws->cs_create(rctx->ws);
 294         rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
 295         r600_emit_atom(rctx, &rctx->start_cs_cmd.atom);
 296
 297         rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
 298                                          PIPE_BIND_INDEX_BUFFER |
 299                                          PIPE_BIND_CONSTANT_BUFFER);
 300         if (!rctx->uploader)
 301                 goto fail;
 302
 303         rctx->blitter = util_blitter_create(&rctx->context);
 304         if (rctx->blitter == NULL)
 305                 goto fail;
 306
 307         r600_get_backend_mask(rctx); /* this emits commands and must be last */
 308
 309         if (rctx->chip_class == R600)
 310                 r600_set_max_scissor(rctx);
 311
 312         rctx->dummy_pixel_shader =
 313                 util_make_fragment_cloneinput_shader(&rctx->context, 0,
 314                                                      TGSI_SEMANTIC_GENERIC,
 315                                                      TGSI_INTERPOLATE_CONSTANT);
 316         rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 317
 318         return &rctx->context;
 319
 320 fail:
 321         r600_destroy_context(&rctx->context);
 322         return NULL;
 323 }
 324
 325 /*
 326  * pipe_screen
 327  */
 328 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 329 {
 330         return "X.Org";
 331 }
 332
 333 static const char *r600_get_family_name(enum radeon_family family)
 334 {
 335         switch(family) {
 336         case CHIP_R600: return "AMD R600";
 337         case CHIP_RV610: return "AMD RV610";
 338         case CHIP_RV630: return "AMD RV630";
 339         case CHIP_RV670: return "AMD RV670";
 340         case CHIP_RV620: return "AMD RV620";
 341         case CHIP_RV635: return "AMD RV635";
 342         case CHIP_RS780: return "AMD RS780";
 343         case CHIP_RS880: return "AMD RS880";
 344         case CHIP_RV770: return "AMD RV770";
 345         case CHIP_RV730: return "AMD RV730";
 346         case CHIP_RV710: return "AMD RV710";
 347         case CHIP_RV740: return "AMD RV740";
 348         case CHIP_CEDAR: return "AMD CEDAR";
 349         case CHIP_REDWOOD: return "AMD REDWOOD";
 350         case CHIP_JUNIPER: return "AMD JUNIPER";
 351         case CHIP_CYPRESS: return "AMD CYPRESS";
 352         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 353         case CHIP_PALM: return "AMD PALM";
 354         case CHIP_SUMO: return "AMD SUMO";
 355         case CHIP_SUMO2: return "AMD SUMO2";
 356         case CHIP_BARTS: return "AMD BARTS";
 357         case CHIP_TURKS: return "AMD TURKS";
 358         case CHIP_CAICOS: return "AMD CAICOS";
 359         case CHIP_CAYMAN: return "AMD CAYMAN";
 360         case CHIP_ARUBA: return "AMD ARUBA";
 361         default: return "AMD unknown";
 362         }
 363 }
 364
 365 static const char* r600_get_name(struct pipe_screen* pscreen)
 366 {
 367         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 368
 369         return r600_get_family_name(rscreen->family);
 370 }
 371
 372 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 373 {
 374         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 375         enum radeon_family family = rscreen->family;
 376
 377         switch (param) {
 378         /* Supported features (boolean caps). */
 379         case PIPE_CAP_NPOT_TEXTURES:
 380         case PIPE_CAP_TWO_SIDED_STENCIL:
 381         case PIPE_CAP_ANISOTROPIC_FILTER:
 382         case PIPE_CAP_POINT_SPRITE:
 383         case PIPE_CAP_OCCLUSION_QUERY:
 384         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 385         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 386         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 387         case PIPE_CAP_TEXTURE_SWIZZLE:
 388         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 389         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 390         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 391         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 392         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 393         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 394         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 395         case PIPE_CAP_SM3:
 396         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 397         case PIPE_CAP_PRIMITIVE_RESTART:
 398         case PIPE_CAP_CONDITIONAL_RENDER:
 399         case PIPE_CAP_TEXTURE_BARRIER:
 400         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 401         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 402         case PIPE_CAP_TGSI_INSTANCEID:
 403         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 404         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 405         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 406                 return 1;
 407
 408         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 409                 return rscreen->glsl_feature_level;
 410
 411         /* Supported except the original R600. */
 412         case PIPE_CAP_INDEP_BLEND_ENABLE:
 413         case PIPE_CAP_INDEP_BLEND_FUNC:
 414                 /* R600 doesn't support per-MRT blends */
 415                 return family == CHIP_R600 ? 0 : 1;
 416
 417         /* Supported on Evergreen. */
 418         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 419                 return family >= CHIP_CEDAR ? 1 : 0;
 420
 421         /* Unsupported features. */
 422         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 423         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 424         case PIPE_CAP_SCALED_RESOLVE:
 425         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 426         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 427         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 428         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 429         case PIPE_CAP_USER_VERTEX_BUFFERS:
 430                 return 0;
 431
 432         /* Stream output. */
 433         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 434                 return rscreen->info.r600_has_streamout ? 4 : 0;
 435         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 436                 return rscreen->info.r600_has_streamout ? 1 : 0;
 437         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 438         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 439                 return 16*4;
 440
 441         /* Texturing. */
 442         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 443         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 444         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 445                 if (family >= CHIP_CEDAR)
 446                         return 15;
 447                 else
 448                         return 14;
 449         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 450                 return rscreen->info.drm_minor >= 9 ?
 451                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 452         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 453                 return 32;
 454
 455         /* Render targets. */
 456         case PIPE_CAP_MAX_RENDER_TARGETS:
 457                 /* XXX some r6xx are buggy and can only do 4 */
 458                 return 8;
 459
 460         /* Timer queries, present when the clock frequency is non zero. */
 461         case PIPE_CAP_TIMER_QUERY:
 462                 return rscreen->info.r600_clock_crystal_freq != 0;
 463
 464         case PIPE_CAP_MIN_TEXEL_OFFSET:
 465                 return -8;
 466
 467         case PIPE_CAP_MAX_TEXEL_OFFSET:
 468                 return 7;
 469
 470         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 471                 return (family < CHIP_RV770) ?  1 : 0;
 472         }
 473         return 0;
 474 }
 475
 476 static float r600_get_paramf(struct pipe_screen* pscreen,
 477                              enum pipe_capf param)
 478 {
 479         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 480         enum radeon_family family = rscreen->family;
 481
 482         switch (param) {
 483         case PIPE_CAPF_MAX_LINE_WIDTH:
 484         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 485         case PIPE_CAPF_MAX_POINT_WIDTH:
 486         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 487                 if (family >= CHIP_CEDAR)
 488                         return 16384.0f;
 489                 else
 490                         return 8192.0f;
 491         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 492                 return 16.0f;
 493         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 494                 return 16.0f;
 495         case PIPE_CAPF_GUARD_BAND_LEFT:
 496         case PIPE_CAPF_GUARD_BAND_TOP:
 497         case PIPE_CAPF_GUARD_BAND_RIGHT:
 498         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 499                 return 0.0f;
 500         }
 501         return 0.0f;
 502 }
 503
 504 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 505 {
 506         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 507         switch(shader)
 508         {
 509         case PIPE_SHADER_FRAGMENT:
 510         case PIPE_SHADER_VERTEX:
 511                 break;
 512         case PIPE_SHADER_GEOMETRY:
 513                 /* XXX: support and enable geometry programs */
 514                 return 0;
 515         default:
 516                 /* XXX: support tessellation on Evergreen */
 517                 return 0;
 518         }
 519
 520         /* XXX: all these should be fixed, since r600 surely supports much more! */
 521         switch (param) {
 522         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 523         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 524         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 525         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 526                 return 16384;
 527         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 528                 return 8; /* XXX */
 529         case PIPE_SHADER_CAP_MAX_INPUTS:
 530                 if(shader == PIPE_SHADER_FRAGMENT)
 531                         return 34;
 532                 else
 533                         return 32;
 534         case PIPE_SHADER_CAP_MAX_TEMPS:
 535                 return 256; /* Max native temporaries. */
 536         case PIPE_SHADER_CAP_MAX_ADDRS:
 537                 /* XXX Isn't this equal to TEMPS? */
 538                 return 1; /* Max native address registers */
 539         case PIPE_SHADER_CAP_MAX_CONSTS:
 540                 return R600_MAX_CONST_BUFFER_SIZE;
 541         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 542                 return R600_MAX_CONST_BUFFERS-1;
 543         case PIPE_SHADER_CAP_MAX_PREDS:
 544                 return 0; /* nothing uses this */
 545         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 546                 return 1;
 547         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 548         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 549         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 550         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 551                 return 1;
 552         case PIPE_SHADER_CAP_SUBROUTINES:
 553                 return 0;
 554         case PIPE_SHADER_CAP_INTEGERS:
 555                 return rscreen->glsl_feature_level >= 130;
 556         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 557                 return 16;
 558         }
 559         return 0;
 560 }
 561
 562 static int r600_get_video_param(struct pipe_screen *screen,
 563                                 enum pipe_video_profile profile,
 564                                 enum pipe_video_cap param)
 565 {
 566         switch (param) {
 567         case PIPE_VIDEO_CAP_SUPPORTED:
 568                 return vl_profile_supported(screen, profile);
 569         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 570                 return 1;
 571         case PIPE_VIDEO_CAP_MAX_WIDTH:
 572         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 573                 return vl_video_buffer_max_size(screen);
 574         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 575                 return PIPE_FORMAT_NV12;
 576         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 577                 return false;
 578         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 579                 return false;
 580         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 581                 return true;
 582         default:
 583                 return 0;
 584         }
 585 }
 586
 587 static void r600_destroy_screen(struct pipe_screen* pscreen)
 588 {
 589         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 590
 591         if (rscreen == NULL)
 592                 return;
 593
 594         if (rscreen->fences.bo) {
 595                 struct r600_fence_block *entry, *tmp;
 596
 597                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 598                         LIST_DEL(&entry->head);
 599                         FREE(entry);
 600                 }
 601
 602                 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
 603                 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
 604         }
 605         pipe_mutex_destroy(rscreen->fences.mutex);
 606
 607         rscreen->ws->destroy(rscreen->ws);
 608
 609         util_slab_destroy(&rscreen->pool_buffers);
 610         pipe_mutex_destroy(rscreen->mutex_num_contexts);
 611         FREE(rscreen);
 612 }
 613
 614 static void r600_fence_reference(struct pipe_screen *pscreen,
 615                                  struct pipe_fence_handle **ptr,
 616                                  struct pipe_fence_handle *fence)
 617 {
 618         struct r600_fence **oldf = (struct r600_fence**)ptr;
 619         struct r600_fence *newf = (struct r600_fence*)fence;
 620
 621         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 622                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 623                 pipe_mutex_lock(rscreen->fences.mutex);
 624                 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
 625                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 626                 pipe_mutex_unlock(rscreen->fences.mutex);
 627         }
 628
 629         *ptr = fence;
 630 }
 631
 632 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 633                                     struct pipe_fence_handle *fence)
 634 {
 635         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 636         struct r600_fence *rfence = (struct r600_fence*)fence;
 637
 638         return rscreen->fences.data[rfence->index];
 639 }
 640
 641 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 642                                  struct pipe_fence_handle *fence,
 643                                  uint64_t timeout)
 644 {
 645         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 646         struct r600_fence *rfence = (struct r600_fence*)fence;
 647         int64_t start_time = 0;
 648         unsigned spins = 0;
 649
 650         if (timeout != PIPE_TIMEOUT_INFINITE) {
 651                 start_time = os_time_get();
 652
 653                 /* Convert to microseconds. */
 654                 timeout /= 1000;
 655         }
 656
 657         while (rscreen->fences.data[rfence->index] == 0) {
 658                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
 659                 if (timeout == PIPE_TIMEOUT_INFINITE) {
 660                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
 661                         break;
 662                 }
 663
 664                 /* The dummy BO will be busy until the CS including the fence has completed, or
 665                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
 666                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
 667                         break;
 668
 669                 if (++spins % 256)
 670                         continue;
 671 #ifdef PIPE_OS_UNIX
 672                 sched_yield();
 673 #else
 674                 os_time_sleep(10);
 675 #endif
 676                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 677                     os_time_get() - start_time >= timeout) {
 678                         break;
 679                 }
 680         }
 681
 682         return rscreen->fences.data[rfence->index] != 0;
 683 }
 684
 685 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 686 {
 687         switch ((tiling_config & 0xe) >> 1) {
 688         case 0:
 689                 rscreen->tiling_info.num_channels = 1;
 690                 break;
 691         case 1:
 692                 rscreen->tiling_info.num_channels = 2;
 693                 break;
 694         case 2:
 695                 rscreen->tiling_info.num_channels = 4;
 696                 break;
 697         case 3:
 698                 rscreen->tiling_info.num_channels = 8;
 699                 break;
 700         default:
 701                 return -EINVAL;
 702         }
 703
 704         switch ((tiling_config & 0x30) >> 4) {
 705         case 0:
 706                 rscreen->tiling_info.num_banks = 4;
 707                 break;
 708         case 1:
 709                 rscreen->tiling_info.num_banks = 8;
 710                 break;
 711         default:
 712                 return -EINVAL;
 713
 714         }
 715         switch ((tiling_config & 0xc0) >> 6) {
 716         case 0:
 717                 rscreen->tiling_info.group_bytes = 256;
 718                 break;
 719         case 1:
 720                 rscreen->tiling_info.group_bytes = 512;
 721                 break;
 722         default:
 723                 return -EINVAL;
 724         }
 725         return 0;
 726 }
 727
 728 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 729 {
 730         switch (tiling_config & 0xf) {
 731         case 0:
 732                 rscreen->tiling_info.num_channels = 1;
 733                 break;
 734         case 1:
 735                 rscreen->tiling_info.num_channels = 2;
 736                 break;
 737         case 2:
 738                 rscreen->tiling_info.num_channels = 4;
 739                 break;
 740         case 3:
 741                 rscreen->tiling_info.num_channels = 8;
 742                 break;
 743         default:
 744                 return -EINVAL;
 745         }
 746
 747         switch ((tiling_config & 0xf0) >> 4) {
 748         case 0:
 749                 rscreen->tiling_info.num_banks = 4;
 750                 break;
 751         case 1:
 752                 rscreen->tiling_info.num_banks = 8;
 753                 break;
 754         case 2:
 755                 rscreen->tiling_info.num_banks = 16;
 756                 break;
 757         default:
 758                 return -EINVAL;
 759         }
 760
 761         switch ((tiling_config & 0xf00) >> 8) {
 762         case 0:
 763                 rscreen->tiling_info.group_bytes = 256;
 764                 break;
 765         case 1:
 766                 rscreen->tiling_info.group_bytes = 512;
 767                 break;
 768         default:
 769                 return -EINVAL;
 770         }
 771         return 0;
 772 }
 773
 774 static int r600_init_tiling(struct r600_screen *rscreen)
 775 {
 776         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 777
 778         /* set default group bytes, overridden by tiling info ioctl */
 779         if (rscreen->chip_class <= R700) {
 780                 rscreen->tiling_info.group_bytes = 256;
 781         } else {
 782                 rscreen->tiling_info.group_bytes = 512;
 783         }
 784
 785         if (!tiling_config)
 786                 return 0;
 787
 788         if (rscreen->chip_class <= R700) {
 789                 return r600_interpret_tiling(rscreen, tiling_config);
 790         } else {
 791                 return evergreen_interpret_tiling(rscreen, tiling_config);
 792         }
 793 }
 794
 795 static unsigned radeon_family_from_device(unsigned device)
 796 {
 797         switch (device) {
 798 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 799 #include "pci_ids/r600_pci_ids.h"
 800 #undef CHIPSET
 801         default:
 802                 return CHIP_UNKNOWN;
 803         }
 804 }
 805
 806 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 807 {
 808         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 809
 810         if (rscreen == NULL) {
 811                 return NULL;
 812         }
 813
 814         rscreen->ws = ws;
 815         ws->query_info(ws, &rscreen->info);
 816
 817         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 818         if (rscreen->family == CHIP_UNKNOWN) {
 819                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 820                 FREE(rscreen);
 821                 return NULL;
 822         }
 823
 824         /* setup class */
 825         if (rscreen->family >= CHIP_CAYMAN) {
 826                 rscreen->chip_class = CAYMAN;
 827         } else if (rscreen->family >= CHIP_CEDAR) {
 828                 rscreen->chip_class = EVERGREEN;
 829         } else if (rscreen->family >= CHIP_RV770) {
 830                 rscreen->chip_class = R700;
 831         } else {
 832                 rscreen->chip_class = R600;
 833         }
 834
 835         /* XXX streamout is said to be broken on r700 and cayman */
 836         if ((rscreen->chip_class == R700 ||
 837              rscreen->chip_class == CAYMAN) &&
 838             !debug_get_bool_option("R600_STREAMOUT", FALSE)) {
 839                 rscreen->info.r600_has_streamout = false;
 840         }
 841
 842         if (r600_init_tiling(rscreen)) {
 843                 FREE(rscreen);
 844                 return NULL;
 845         }
 846
 847         rscreen->screen.destroy = r600_destroy_screen;
 848         rscreen->screen.get_name = r600_get_name;
 849         rscreen->screen.get_vendor = r600_get_vendor;
 850         rscreen->screen.get_param = r600_get_param;
 851         rscreen->screen.get_shader_param = r600_get_shader_param;
 852         rscreen->screen.get_paramf = r600_get_paramf;
 853         rscreen->screen.get_video_param = r600_get_video_param;
 854         if (rscreen->chip_class >= EVERGREEN) {
 855                 rscreen->screen.is_format_supported = evergreen_is_format_supported;
 856         } else {
 857                 rscreen->screen.is_format_supported = r600_is_format_supported;
 858         }
 859         rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 860         rscreen->screen.context_create = r600_create_context;
 861         rscreen->screen.fence_reference = r600_fence_reference;
 862         rscreen->screen.fence_signalled = r600_fence_signalled;
 863         rscreen->screen.fence_finish = r600_fence_finish;
 864         r600_init_screen_resource_functions(&rscreen->screen);
 865
 866         util_format_s3tc_init();
 867
 868         util_slab_create(&rscreen->pool_buffers,
 869                          sizeof(struct r600_resource), 64,
 870                          UTIL_SLAB_SINGLETHREADED);
 871
 872         pipe_mutex_init(rscreen->mutex_num_contexts);
 873
 874         rscreen->fences.bo = NULL;
 875         rscreen->fences.data = NULL;
 876         rscreen->fences.next_index = 0;
 877         LIST_INITHEAD(&rscreen->fences.pool);
 878         LIST_INITHEAD(&rscreen->fences.blocks);
 879         pipe_mutex_init(rscreen->fences.mutex);
 880
 881         rscreen->use_surface_alloc = debug_get_bool_option("R600_SURF", TRUE);
 882         rscreen->glsl_feature_level = debug_get_bool_option("R600_GLSL130", TRUE) ? 130 : 120;
 883
 884         return &rscreen->screen;
 885 }