2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_pipe.h"
24 #include "r600_public.h"
26 #include "evergreen_compute.h"
29 #include "sb/sb_public.h"
32 #include "pipe/p_shader_tokens.h"
33 #include "util/u_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_simple_shaders.h"
36 #include "util/u_upload_mgr.h"
37 #include "util/u_math.h"
38 #include "vl/vl_decoder.h"
39 #include "vl/vl_video_buffer.h"
40 #include "radeon/radeon_video.h"
41 #include "radeon/radeon_uvd.h"
42 #include "os/os_time.h"
44 static const struct debug_named_value r600_debug_options
[] = {
46 { "nocpdma", DBG_NO_CP_DMA
, "Disable CP DMA" },
49 { "nosb", DBG_NO_SB
, "Disable sb backend for graphics shaders" },
50 { "sbcl", DBG_SB_CS
, "Enable sb backend for compute shaders" },
51 { "sbdry", DBG_SB_DRY_RUN
, "Don't use optimized bytecode (just print the dumps)" },
52 { "sbstat", DBG_SB_STAT
, "Print optimization statistics for shaders" },
53 { "sbdump", DBG_SB_DUMP
, "Print IR dumps after some optimization passes" },
54 { "sbnofallback", DBG_SB_NO_FALLBACK
, "Abort on errors instead of fallback" },
55 { "sbdisasm", DBG_SB_DISASM
, "Use sb disassembler for shader dumps" },
56 { "sbsafemath", DBG_SB_SAFEMATH
, "Disable unsafe math optimizations" },
58 DEBUG_NAMED_VALUE_END
/* must be last */
65 static void r600_destroy_context(struct pipe_context
*context
)
67 struct r600_context
*rctx
= (struct r600_context
*)context
;
70 r600_isa_destroy(rctx
->isa
);
72 r600_sb_context_destroy(rctx
->sb_context
);
74 r600_resource_reference(&rctx
->dummy_cmask
, NULL
);
75 r600_resource_reference(&rctx
->dummy_fmask
, NULL
);
77 for (sh
= 0; sh
< PIPE_SHADER_TYPES
; sh
++) {
78 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, sh
, R600_BUFFER_INFO_CONST_BUFFER
, NULL
);
79 free(rctx
->driver_consts
[sh
].constants
);
82 if (rctx
->fixed_func_tcs_shader
)
83 rctx
->b
.b
.delete_tcs_state(&rctx
->b
.b
, rctx
->fixed_func_tcs_shader
);
85 if (rctx
->dummy_pixel_shader
) {
86 rctx
->b
.b
.delete_fs_state(&rctx
->b
.b
, rctx
->dummy_pixel_shader
);
88 if (rctx
->custom_dsa_flush
) {
89 rctx
->b
.b
.delete_depth_stencil_alpha_state(&rctx
->b
.b
, rctx
->custom_dsa_flush
);
91 if (rctx
->custom_blend_resolve
) {
92 rctx
->b
.b
.delete_blend_state(&rctx
->b
.b
, rctx
->custom_blend_resolve
);
94 if (rctx
->custom_blend_decompress
) {
95 rctx
->b
.b
.delete_blend_state(&rctx
->b
.b
, rctx
->custom_blend_decompress
);
97 if (rctx
->custom_blend_fastclear
) {
98 rctx
->b
.b
.delete_blend_state(&rctx
->b
.b
, rctx
->custom_blend_fastclear
);
100 util_unreference_framebuffer_state(&rctx
->framebuffer
.state
);
103 util_blitter_destroy(rctx
->blitter
);
105 if (rctx
->allocator_fetch_shader
) {
106 u_suballocator_destroy(rctx
->allocator_fetch_shader
);
109 r600_release_command_buffer(&rctx
->start_cs_cmd
);
111 FREE(rctx
->start_compute_cs_cmd
.buf
);
113 r600_common_context_cleanup(&rctx
->b
);
117 static struct pipe_context
*r600_create_context(struct pipe_screen
*screen
,
118 void *priv
, unsigned flags
)
120 struct r600_context
*rctx
= CALLOC_STRUCT(r600_context
);
121 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
122 struct radeon_winsys
*ws
= rscreen
->b
.ws
;
127 rctx
->b
.b
.screen
= screen
;
128 rctx
->b
.b
.priv
= priv
;
129 rctx
->b
.b
.destroy
= r600_destroy_context
;
130 rctx
->b
.set_atom_dirty
= (void *)r600_set_atom_dirty
;
132 if (!r600_common_context_init(&rctx
->b
, &rscreen
->b
, flags
))
135 rctx
->screen
= rscreen
;
136 LIST_INITHEAD(&rctx
->texture_buffers
);
138 r600_init_blit_functions(rctx
);
140 if (rscreen
->b
.info
.has_uvd
) {
141 rctx
->b
.b
.create_video_codec
= r600_uvd_create_decoder
;
142 rctx
->b
.b
.create_video_buffer
= r600_video_buffer_create
;
144 rctx
->b
.b
.create_video_codec
= vl_create_decoder
;
145 rctx
->b
.b
.create_video_buffer
= vl_video_buffer_create
;
148 r600_init_common_state_functions(rctx
);
150 switch (rctx
->b
.chip_class
) {
153 r600_init_state_functions(rctx
);
154 r600_init_atom_start_cs(rctx
);
155 rctx
->custom_dsa_flush
= r600_create_db_flush_dsa(rctx
);
156 rctx
->custom_blend_resolve
= rctx
->b
.chip_class
== R700
? r700_create_resolve_blend(rctx
)
157 : r600_create_resolve_blend(rctx
);
158 rctx
->custom_blend_decompress
= r600_create_decompress_blend(rctx
);
159 rctx
->has_vertex_cache
= !(rctx
->b
.family
== CHIP_RV610
||
160 rctx
->b
.family
== CHIP_RV620
||
161 rctx
->b
.family
== CHIP_RS780
||
162 rctx
->b
.family
== CHIP_RS880
||
163 rctx
->b
.family
== CHIP_RV710
);
167 evergreen_init_state_functions(rctx
);
168 evergreen_init_atom_start_cs(rctx
);
169 evergreen_init_atom_start_compute_cs(rctx
);
170 rctx
->custom_dsa_flush
= evergreen_create_db_flush_dsa(rctx
);
171 rctx
->custom_blend_resolve
= evergreen_create_resolve_blend(rctx
);
172 rctx
->custom_blend_decompress
= evergreen_create_decompress_blend(rctx
);
173 rctx
->custom_blend_fastclear
= evergreen_create_fastclear_blend(rctx
);
174 rctx
->has_vertex_cache
= !(rctx
->b
.family
== CHIP_CEDAR
||
175 rctx
->b
.family
== CHIP_PALM
||
176 rctx
->b
.family
== CHIP_SUMO
||
177 rctx
->b
.family
== CHIP_SUMO2
||
178 rctx
->b
.family
== CHIP_CAICOS
||
179 rctx
->b
.family
== CHIP_CAYMAN
||
180 rctx
->b
.family
== CHIP_ARUBA
);
183 R600_ERR("Unsupported chip class %d.\n", rctx
->b
.chip_class
);
187 rctx
->b
.gfx
.cs
= ws
->cs_create(rctx
->b
.ctx
, RING_GFX
,
188 r600_context_gfx_flush
, rctx
);
189 rctx
->b
.gfx
.flush
= r600_context_gfx_flush
;
191 rctx
->allocator_fetch_shader
=
192 u_suballocator_create(&rctx
->b
.b
, 64 * 1024,
193 0, PIPE_USAGE_DEFAULT
, 0, FALSE
);
194 if (!rctx
->allocator_fetch_shader
)
197 rctx
->isa
= calloc(1, sizeof(struct r600_isa
));
198 if (!rctx
->isa
|| r600_isa_init(rctx
, rctx
->isa
))
201 if (rscreen
->b
.debug_flags
& DBG_FORCE_DMA
)
202 rctx
->b
.b
.resource_copy_region
= rctx
->b
.dma_copy
;
204 rctx
->blitter
= util_blitter_create(&rctx
->b
.b
);
205 if (rctx
->blitter
== NULL
)
207 util_blitter_set_texture_multisample(rctx
->blitter
, rscreen
->has_msaa
);
208 rctx
->blitter
->draw_rectangle
= r600_draw_rectangle
;
210 r600_begin_new_cs(rctx
);
212 rctx
->dummy_pixel_shader
=
213 util_make_fragment_cloneinput_shader(&rctx
->b
.b
, 0,
214 TGSI_SEMANTIC_GENERIC
,
215 TGSI_INTERPOLATE_CONSTANT
);
216 rctx
->b
.b
.bind_fs_state(&rctx
->b
.b
, rctx
->dummy_pixel_shader
);
221 r600_destroy_context(&rctx
->b
.b
);
229 static int r600_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
231 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
232 enum radeon_family family
= rscreen
->b
.family
;
235 /* Supported features (boolean caps). */
236 case PIPE_CAP_NPOT_TEXTURES
:
237 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
238 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
239 case PIPE_CAP_TWO_SIDED_STENCIL
:
240 case PIPE_CAP_ANISOTROPIC_FILTER
:
241 case PIPE_CAP_POINT_SPRITE
:
242 case PIPE_CAP_OCCLUSION_QUERY
:
243 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
244 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
245 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
246 case PIPE_CAP_TEXTURE_SWIZZLE
:
247 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
248 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
249 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
250 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
251 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
252 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
254 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
255 case PIPE_CAP_PRIMITIVE_RESTART
:
256 case PIPE_CAP_CONDITIONAL_RENDER
:
257 case PIPE_CAP_TEXTURE_BARRIER
:
258 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
259 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
260 case PIPE_CAP_TGSI_INSTANCEID
:
261 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
262 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
263 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
264 case PIPE_CAP_USER_INDEX_BUFFERS
:
265 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
266 case PIPE_CAP_START_INSTANCE
:
267 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
268 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
269 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
270 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
271 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
272 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
273 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
274 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
275 case PIPE_CAP_SAMPLE_SHADING
:
276 case PIPE_CAP_CLIP_HALFZ
:
277 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
278 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
279 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
280 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
281 case PIPE_CAP_TGSI_TXQS
:
282 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
283 case PIPE_CAP_INVALIDATE_BUFFER
:
284 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
285 case PIPE_CAP_QUERY_MEMORY_INFO
:
286 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
287 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
288 case PIPE_CAP_CLEAR_TEXTURE
:
289 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
292 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
293 return rscreen
->b
.info
.drm_major
== 2 && rscreen
->b
.info
.drm_minor
>= 43;
295 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
296 return !R600_BIG_ENDIAN
&& rscreen
->b
.info
.has_userptr
;
298 case PIPE_CAP_COMPUTE
:
299 return rscreen
->b
.chip_class
> R700
;
301 case PIPE_CAP_TGSI_TEXCOORD
:
304 case PIPE_CAP_FAKE_SW_MSAA
:
307 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
308 return MIN2(rscreen
->b
.info
.max_alloc_size
, INT_MAX
);
310 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
311 return R600_MAP_BUFFER_ALIGNMENT
;
313 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
316 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
319 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
320 if (family
>= CHIP_CEDAR
)
322 /* pre-evergreen geom shaders need newer kernel */
323 if (rscreen
->b
.info
.drm_minor
>= 37)
327 /* Supported except the original R600. */
328 case PIPE_CAP_INDEP_BLEND_ENABLE
:
329 case PIPE_CAP_INDEP_BLEND_FUNC
:
330 /* R600 doesn't support per-MRT blends */
331 return family
== CHIP_R600
? 0 : 1;
333 /* Supported on Evergreen. */
334 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
335 case PIPE_CAP_CUBE_MAP_ARRAY
:
336 case PIPE_CAP_TEXTURE_GATHER_SM5
:
337 case PIPE_CAP_TEXTURE_QUERY_LOD
:
338 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
339 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
340 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
341 return family
>= CHIP_CEDAR
? 1 : 0;
342 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
343 return family
>= CHIP_CEDAR
? 4 : 0;
344 case PIPE_CAP_DRAW_INDIRECT
:
345 /* kernel command checker support is also required */
346 return family
>= CHIP_CEDAR
&& rscreen
->b
.info
.drm_minor
>= 41;
348 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
349 return family
>= CHIP_CEDAR
? 0 : 1;
351 /* Unsupported features. */
352 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
353 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
354 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
355 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
356 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
357 case PIPE_CAP_USER_VERTEX_BUFFERS
:
358 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
359 case PIPE_CAP_VERTEXID_NOBASE
:
360 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
361 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
362 case PIPE_CAP_SHAREABLE_SHADERS
:
363 case PIPE_CAP_DRAW_PARAMETERS
:
364 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
365 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
366 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
367 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
368 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
369 case PIPE_CAP_GENERATE_MIPMAP
:
370 case PIPE_CAP_STRING_MARKER
:
371 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
372 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
373 case PIPE_CAP_CULL_DISTANCE
:
374 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
375 case PIPE_CAP_TGSI_VOTE
:
376 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
377 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
378 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
379 case PIPE_CAP_NATIVE_FENCE_FD
:
380 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
381 case PIPE_CAP_TGSI_FS_FBFETCH
:
383 case PIPE_CAP_INT64_DIVMOD
:
386 case PIPE_CAP_DOUBLES
:
387 if (rscreen
->b
.family
== CHIP_ARUBA
||
388 rscreen
->b
.family
== CHIP_CAYMAN
||
389 rscreen
->b
.family
== CHIP_CYPRESS
||
390 rscreen
->b
.family
== CHIP_HEMLOCK
)
394 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
395 if (family
>= CHIP_CEDAR
)
400 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
401 return rscreen
->b
.has_streamout
? 4 : 0;
402 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
403 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
404 return rscreen
->b
.has_streamout
? 1 : 0;
405 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
406 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
409 /* Geometry shader output. */
410 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
412 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
414 case PIPE_CAP_MAX_VERTEX_STREAMS
:
415 return family
>= CHIP_CEDAR
? 4 : 1;
417 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
421 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
422 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
423 if (family
>= CHIP_CEDAR
)
427 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
428 /* textures support 8192, but layered rendering supports 2048 */
430 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
431 /* textures support 8192, but layered rendering supports 2048 */
434 /* Render targets. */
435 case PIPE_CAP_MAX_RENDER_TARGETS
:
436 /* XXX some r6xx are buggy and can only do 4 */
439 case PIPE_CAP_MAX_VIEWPORTS
:
440 return R600_MAX_VIEWPORTS
;
441 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
444 /* Timer queries, present when the clock frequency is non zero. */
445 case PIPE_CAP_QUERY_TIME_ELAPSED
:
446 return rscreen
->b
.info
.clock_crystal_freq
!= 0;
447 case PIPE_CAP_QUERY_TIMESTAMP
:
448 return rscreen
->b
.info
.drm_minor
>= 20 &&
449 rscreen
->b
.info
.clock_crystal_freq
!= 0;
451 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
452 case PIPE_CAP_MIN_TEXEL_OFFSET
:
455 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
456 case PIPE_CAP_MAX_TEXEL_OFFSET
:
459 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
460 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
;
461 case PIPE_CAP_ENDIANNESS
:
462 return PIPE_ENDIAN_LITTLE
;
464 case PIPE_CAP_VENDOR_ID
:
465 return ATI_VENDOR_ID
;
466 case PIPE_CAP_DEVICE_ID
:
467 return rscreen
->b
.info
.pci_id
;
468 case PIPE_CAP_ACCELERATED
:
470 case PIPE_CAP_VIDEO_MEMORY
:
471 return rscreen
->b
.info
.vram_size
>> 20;
474 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
475 return rscreen
->b
.chip_class
>= R700
;
476 case PIPE_CAP_PCI_GROUP
:
477 return rscreen
->b
.info
.pci_domain
;
478 case PIPE_CAP_PCI_BUS
:
479 return rscreen
->b
.info
.pci_bus
;
480 case PIPE_CAP_PCI_DEVICE
:
481 return rscreen
->b
.info
.pci_dev
;
482 case PIPE_CAP_PCI_FUNCTION
:
483 return rscreen
->b
.info
.pci_func
;
488 static int r600_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
490 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
494 case PIPE_SHADER_FRAGMENT
:
495 case PIPE_SHADER_VERTEX
:
496 case PIPE_SHADER_COMPUTE
:
498 case PIPE_SHADER_GEOMETRY
:
499 if (rscreen
->b
.family
>= CHIP_CEDAR
)
501 /* pre-evergreen geom shaders need newer kernel */
502 if (rscreen
->b
.info
.drm_minor
>= 37)
505 case PIPE_SHADER_TESS_CTRL
:
506 case PIPE_SHADER_TESS_EVAL
:
507 if (rscreen
->b
.family
>= CHIP_CEDAR
)
514 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
515 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
516 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
517 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
519 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
521 case PIPE_SHADER_CAP_MAX_INPUTS
:
522 return shader
== PIPE_SHADER_VERTEX
? 16 : 32;
523 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
524 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
525 case PIPE_SHADER_CAP_MAX_TEMPS
:
526 return 256; /* Max native temporaries. */
527 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
528 if (shader
== PIPE_SHADER_COMPUTE
) {
529 uint64_t max_const_buffer_size
;
530 pscreen
->get_compute_param(pscreen
, PIPE_SHADER_IR_TGSI
,
531 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
532 &max_const_buffer_size
);
533 return MIN2(max_const_buffer_size
, INT_MAX
);
536 return R600_MAX_CONST_BUFFER_SIZE
;
538 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
539 return R600_MAX_USER_CONST_BUFFERS
;
540 case PIPE_SHADER_CAP_MAX_PREDS
:
541 return 0; /* nothing uses this */
542 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
544 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
546 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
547 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
548 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
549 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
551 case PIPE_SHADER_CAP_SUBROUTINES
:
553 case PIPE_SHADER_CAP_INTEGERS
:
554 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
556 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
557 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
559 case PIPE_SHADER_CAP_PREFERRED_IR
:
560 if (shader
== PIPE_SHADER_COMPUTE
) {
561 return PIPE_SHADER_IR_NATIVE
;
563 return PIPE_SHADER_IR_TGSI
;
565 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
567 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
568 if (rscreen
->b
.family
== CHIP_ARUBA
||
569 rscreen
->b
.family
== CHIP_CAYMAN
||
570 rscreen
->b
.family
== CHIP_CYPRESS
||
571 rscreen
->b
.family
== CHIP_HEMLOCK
)
574 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
575 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
576 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
577 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
578 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
580 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
581 /* due to a bug in the shader compiler, some loops hang
582 * if they are not unrolled, see:
583 * https://bugs.freedesktop.org/show_bug.cgi?id=86720
590 static void r600_destroy_screen(struct pipe_screen
* pscreen
)
592 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
597 if (!rscreen
->b
.ws
->unref(rscreen
->b
.ws
))
600 if (rscreen
->global_pool
) {
601 compute_memory_pool_delete(rscreen
->global_pool
);
604 r600_destroy_common_screen(&rscreen
->b
);
607 static struct pipe_resource
*r600_resource_create(struct pipe_screen
*screen
,
608 const struct pipe_resource
*templ
)
610 if (templ
->target
== PIPE_BUFFER
&&
611 (templ
->bind
& PIPE_BIND_GLOBAL
))
612 return r600_compute_global_buffer_create(screen
, templ
);
614 return r600_resource_create_common(screen
, templ
);
617 struct pipe_screen
*r600_screen_create(struct radeon_winsys
*ws
)
619 struct r600_screen
*rscreen
= CALLOC_STRUCT(r600_screen
);
625 /* Set functions first. */
626 rscreen
->b
.b
.context_create
= r600_create_context
;
627 rscreen
->b
.b
.destroy
= r600_destroy_screen
;
628 rscreen
->b
.b
.get_param
= r600_get_param
;
629 rscreen
->b
.b
.get_shader_param
= r600_get_shader_param
;
630 rscreen
->b
.b
.resource_create
= r600_resource_create
;
632 if (!r600_common_screen_init(&rscreen
->b
, ws
)) {
637 if (rscreen
->b
.info
.chip_class
>= EVERGREEN
) {
638 rscreen
->b
.b
.is_format_supported
= evergreen_is_format_supported
;
640 rscreen
->b
.b
.is_format_supported
= r600_is_format_supported
;
643 rscreen
->b
.debug_flags
|= debug_get_flags_option("R600_DEBUG", r600_debug_options
, 0);
644 if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE
))
645 rscreen
->b
.debug_flags
|= DBG_COMPUTE
;
646 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE
))
647 rscreen
->b
.debug_flags
|= DBG_FS
| DBG_VS
| DBG_GS
| DBG_PS
| DBG_CS
| DBG_TCS
| DBG_TES
;
648 if (!debug_get_bool_option("R600_HYPERZ", TRUE
))
649 rscreen
->b
.debug_flags
|= DBG_NO_HYPERZ
;
651 if (rscreen
->b
.family
== CHIP_UNKNOWN
) {
652 fprintf(stderr
, "r600: Unknown chipset 0x%04X\n", rscreen
->b
.info
.pci_id
);
657 /* Figure out streamout kernel support. */
658 switch (rscreen
->b
.chip_class
) {
660 if (rscreen
->b
.family
< CHIP_RS780
) {
661 rscreen
->b
.has_streamout
= rscreen
->b
.info
.drm_minor
>= 14;
663 rscreen
->b
.has_streamout
= rscreen
->b
.info
.drm_minor
>= 23;
667 rscreen
->b
.has_streamout
= rscreen
->b
.info
.drm_minor
>= 17;
671 rscreen
->b
.has_streamout
= rscreen
->b
.info
.drm_minor
>= 14;
674 rscreen
->b
.has_streamout
= FALSE
;
679 switch (rscreen
->b
.chip_class
) {
682 rscreen
->has_msaa
= rscreen
->b
.info
.drm_minor
>= 22;
683 rscreen
->has_compressed_msaa_texturing
= false;
686 rscreen
->has_msaa
= rscreen
->b
.info
.drm_minor
>= 19;
687 rscreen
->has_compressed_msaa_texturing
= rscreen
->b
.info
.drm_minor
>= 24;
690 rscreen
->has_msaa
= rscreen
->b
.info
.drm_minor
>= 19;
691 rscreen
->has_compressed_msaa_texturing
= true;
694 rscreen
->has_msaa
= FALSE
;
695 rscreen
->has_compressed_msaa_texturing
= false;
698 rscreen
->b
.has_cp_dma
= rscreen
->b
.info
.drm_minor
>= 27 &&
699 !(rscreen
->b
.debug_flags
& DBG_NO_CP_DMA
);
701 rscreen
->b
.barrier_flags
.cp_to_L2
=
702 R600_CONTEXT_INV_VERTEX_CACHE
|
703 R600_CONTEXT_INV_TEX_CACHE
|
704 R600_CONTEXT_INV_CONST_CACHE
;
705 rscreen
->b
.barrier_flags
.compute_to_L2
= R600_CONTEXT_PS_PARTIAL_FLUSH
;
707 rscreen
->global_pool
= compute_memory_pool_new(rscreen
);
709 /* Create the auxiliary context. This must be done last. */
710 rscreen
->b
.aux_context
= rscreen
->b
.b
.context_create(&rscreen
->b
.b
, NULL
, 0);
712 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
713 struct pipe_resource templ
= {};
716 templ
.height0
= 2048;
718 templ
.array_size
= 1;
719 templ
.target
= PIPE_TEXTURE_2D
;
720 templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
721 templ
.usage
= PIPE_USAGE_DEFAULT
;
723 struct r600_resource
*res
= r600_resource(rscreen
->screen
.resource_create(&rscreen
->screen
, &templ
));
724 unsigned char *map
= ws
->buffer_map(res
->buf
, NULL
, PIPE_TRANSFER_WRITE
);
728 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 4, 4, 0xCC);
729 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 8, 4, 0xDD);
730 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 12, 4, 0xEE);
731 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 20, 4, 0xFF);
732 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 32, 20, 0x87);
734 ws
->buffer_wait(res
->buf
, RADEON_USAGE_WRITE
);
737 for (i
= 0; i
< 256; i
++) {
738 printf("%02X", map
[i
]);
744 if (rscreen
->b
.debug_flags
& DBG_TEST_DMA
)
745 r600_test_dma(&rscreen
->b
);
747 r600_query_fix_enabled_rb_mask(&rscreen
->b
);
748 return &rscreen
->b
.b
;