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2680396c3d608e8fbc23f03b105a0cf5fc797d5a
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_pipe.h"
24 #include "r600_public.h"
25 #include "r600_isa.h"
26 #include "evergreen_compute.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include <errno.h>
32 #include "pipe/p_shader_tokens.h"
33 #include "util/u_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_screen.h"
36 #include "util/u_simple_shaders.h"
37 #include "util/u_upload_mgr.h"
38 #include "util/u_math.h"
39 #include "vl/vl_decoder.h"
40 #include "vl/vl_video_buffer.h"
41 #include "radeon_video.h"
42 #include "radeon_uvd.h"
43 #include "util/os_time.h"
44
45 static const struct debug_named_value r600_debug_options[] = {
46 /* features */
47 { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
48
49 /* shader backend */
50 { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
51 { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
52 { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
53 { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
54 { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
55 { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
56 { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
57 { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
58
59 DEBUG_NAMED_VALUE_END /* must be last */
60 };
61
62 /*
63 * pipe_context
64 */
65
66 static void r600_destroy_context(struct pipe_context *context)
67 {
68 struct r600_context *rctx = (struct r600_context *)context;
69 unsigned sh, i;
70
71 r600_isa_destroy(rctx->isa);
72
73 r600_sb_context_destroy(rctx->sb_context);
74
75 for (sh = 0; sh < (rctx->b.chip_class < EVERGREEN ? R600_NUM_HW_STAGES : EG_NUM_HW_STAGES); sh++) {
76 r600_resource_reference(&rctx->scratch_buffers[sh].buffer, NULL);
77 }
78 r600_resource_reference(&rctx->dummy_cmask, NULL);
79 r600_resource_reference(&rctx->dummy_fmask, NULL);
80
81 if (rctx->append_fence)
82 pipe_resource_reference((struct pipe_resource**)&rctx->append_fence, NULL);
83 for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
84 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, NULL);
85 free(rctx->driver_consts[sh].constants);
86 }
87
88 if (rctx->fixed_func_tcs_shader)
89 rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
90
91 if (rctx->dummy_pixel_shader) {
92 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
93 }
94 if (rctx->custom_dsa_flush) {
95 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
96 }
97 if (rctx->custom_blend_resolve) {
98 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
99 }
100 if (rctx->custom_blend_decompress) {
101 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
102 }
103 if (rctx->custom_blend_fastclear) {
104 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
105 }
106 util_unreference_framebuffer_state(&rctx->framebuffer.state);
107
108 for (sh = 0; sh < PIPE_SHADER_TYPES; ++sh)
109 for (i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; ++i)
110 rctx->b.b.set_constant_buffer(context, sh, i, NULL);
111
112 if (rctx->blitter) {
113 util_blitter_destroy(rctx->blitter);
114 }
115 if (rctx->allocator_fetch_shader) {
116 u_suballocator_destroy(rctx->allocator_fetch_shader);
117 }
118
119 r600_release_command_buffer(&rctx->start_cs_cmd);
120
121 FREE(rctx->start_compute_cs_cmd.buf);
122
123 r600_common_context_cleanup(&rctx->b);
124
125 r600_resource_reference(&rctx->trace_buf, NULL);
126 r600_resource_reference(&rctx->last_trace_buf, NULL);
127 radeon_clear_saved_cs(&rctx->last_gfx);
128
129 FREE(rctx);
130 }
131
132 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
133 void *priv, unsigned flags)
134 {
135 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
136 struct r600_screen* rscreen = (struct r600_screen *)screen;
137 struct radeon_winsys *ws = rscreen->b.ws;
138
139 if (!rctx)
140 return NULL;
141
142 rctx->b.b.screen = screen;
143 assert(!priv);
144 rctx->b.b.priv = NULL; /* for threaded_context_unwrap_sync */
145 rctx->b.b.destroy = r600_destroy_context;
146 rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
147
148 if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
149 goto fail;
150
151 rctx->screen = rscreen;
152 LIST_INITHEAD(&rctx->texture_buffers);
153
154 r600_init_blit_functions(rctx);
155
156 if (rscreen->b.info.has_hw_decode) {
157 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
158 rctx->b.b.create_video_buffer = r600_video_buffer_create;
159 } else {
160 rctx->b.b.create_video_codec = vl_create_decoder;
161 rctx->b.b.create_video_buffer = vl_video_buffer_create;
162 }
163
164 if (getenv("R600_TRACE"))
165 rctx->is_debug = true;
166 r600_init_common_state_functions(rctx);
167
168 switch (rctx->b.chip_class) {
169 case R600:
170 case R700:
171 r600_init_state_functions(rctx);
172 r600_init_atom_start_cs(rctx);
173 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
174 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
175 : r600_create_resolve_blend(rctx);
176 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
177 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
178 rctx->b.family == CHIP_RV620 ||
179 rctx->b.family == CHIP_RS780 ||
180 rctx->b.family == CHIP_RS880 ||
181 rctx->b.family == CHIP_RV710);
182 break;
183 case EVERGREEN:
184 case CAYMAN:
185 evergreen_init_state_functions(rctx);
186 evergreen_init_atom_start_cs(rctx);
187 evergreen_init_atom_start_compute_cs(rctx);
188 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
189 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
190 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
191 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
192 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
193 rctx->b.family == CHIP_PALM ||
194 rctx->b.family == CHIP_SUMO ||
195 rctx->b.family == CHIP_SUMO2 ||
196 rctx->b.family == CHIP_CAICOS ||
197 rctx->b.family == CHIP_CAYMAN ||
198 rctx->b.family == CHIP_ARUBA);
199
200 rctx->append_fence = pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
201 PIPE_USAGE_DEFAULT, 32);
202 break;
203 default:
204 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
205 goto fail;
206 }
207
208 rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
209 r600_context_gfx_flush, rctx);
210 rctx->b.gfx.flush = r600_context_gfx_flush;
211
212 rctx->allocator_fetch_shader =
213 u_suballocator_create(&rctx->b.b, 64 * 1024,
214 0, PIPE_USAGE_DEFAULT, 0, FALSE);
215 if (!rctx->allocator_fetch_shader)
216 goto fail;
217
218 rctx->isa = calloc(1, sizeof(struct r600_isa));
219 if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
220 goto fail;
221
222 if (rscreen->b.debug_flags & DBG_FORCE_DMA)
223 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
224
225 rctx->blitter = util_blitter_create(&rctx->b.b);
226 if (rctx->blitter == NULL)
227 goto fail;
228 util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
229 rctx->blitter->draw_rectangle = r600_draw_rectangle;
230
231 r600_begin_new_cs(rctx);
232
233 rctx->dummy_pixel_shader =
234 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
235 TGSI_SEMANTIC_GENERIC,
236 TGSI_INTERPOLATE_CONSTANT);
237 rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
238
239 return &rctx->b.b;
240
241 fail:
242 r600_destroy_context(&rctx->b.b);
243 return NULL;
244 }
245
246 /*
247 * pipe_screen
248 */
249
250 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
251 {
252 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
253 enum radeon_family family = rscreen->b.family;
254
255 switch (param) {
256 /* Supported features (boolean caps). */
257 case PIPE_CAP_NPOT_TEXTURES:
258 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
259 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
260 case PIPE_CAP_ANISOTROPIC_FILTER:
261 case PIPE_CAP_POINT_SPRITE:
262 case PIPE_CAP_OCCLUSION_QUERY:
263 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
264 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
265 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
266 case PIPE_CAP_TEXTURE_SWIZZLE:
267 case PIPE_CAP_DEPTH_CLIP_DISABLE:
268 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
269 case PIPE_CAP_SHADER_STENCIL_EXPORT:
270 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
271 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
272 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
273 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
274 case PIPE_CAP_SM3:
275 case PIPE_CAP_SEAMLESS_CUBE_MAP:
276 case PIPE_CAP_PRIMITIVE_RESTART:
277 case PIPE_CAP_CONDITIONAL_RENDER:
278 case PIPE_CAP_TEXTURE_BARRIER:
279 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
280 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
281 case PIPE_CAP_TGSI_INSTANCEID:
282 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
283 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
284 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
285 case PIPE_CAP_START_INSTANCE:
286 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
287 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
288 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
289 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
290 case PIPE_CAP_TEXTURE_MULTISAMPLE:
291 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
292 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
293 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
294 case PIPE_CAP_SAMPLE_SHADING:
295 case PIPE_CAP_CLIP_HALFZ:
296 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
297 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
298 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
299 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
300 case PIPE_CAP_TGSI_TXQS:
301 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
302 case PIPE_CAP_INVALIDATE_BUFFER:
303 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
304 case PIPE_CAP_QUERY_MEMORY_INFO:
305 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
306 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
307 case PIPE_CAP_CLEAR_TEXTURE:
308 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
309 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
310 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
311 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
312 return 1;
313
314 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
315 /* Optimal number for good TexSubImage performance on Polaris10. */
316 return 64 * 1024 * 1024;
317
318 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
319 return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
320
321 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
322 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
323
324 case PIPE_CAP_COMPUTE:
325 return rscreen->b.chip_class > R700;
326
327 case PIPE_CAP_TGSI_TEXCOORD:
328 return 0;
329
330 case PIPE_CAP_FAKE_SW_MSAA:
331 return 0;
332
333 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
334 return MIN2(rscreen->b.info.max_alloc_size, INT_MAX);
335
336 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
337 return R600_MAP_BUFFER_ALIGNMENT;
338
339 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
340 return 256;
341
342 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
343 return 1;
344
345 case PIPE_CAP_GLSL_FEATURE_LEVEL:
346 if (family >= CHIP_CEDAR)
347 return 430;
348 /* pre-evergreen geom shaders need newer kernel */
349 if (rscreen->b.info.drm_minor >= 37)
350 return 330;
351 return 140;
352
353 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
354 return 140;
355
356 /* Supported except the original R600. */
357 case PIPE_CAP_INDEP_BLEND_ENABLE:
358 case PIPE_CAP_INDEP_BLEND_FUNC:
359 /* R600 doesn't support per-MRT blends */
360 return family == CHIP_R600 ? 0 : 1;
361
362 /* Supported on Evergreen. */
363 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
364 case PIPE_CAP_CUBE_MAP_ARRAY:
365 case PIPE_CAP_TEXTURE_GATHER_SM5:
366 case PIPE_CAP_TEXTURE_QUERY_LOD:
367 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
368 case PIPE_CAP_SAMPLER_VIEW_TARGET:
369 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
370 case PIPE_CAP_TGSI_CLOCK:
371 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
372 case PIPE_CAP_QUERY_BUFFER_OBJECT:
373 return family >= CHIP_CEDAR ? 1 : 0;
374 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
375 return family >= CHIP_CEDAR ? 4 : 0;
376 case PIPE_CAP_DRAW_INDIRECT:
377 /* kernel command checker support is also required */
378 return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
379
380 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
381 return family >= CHIP_CEDAR ? 0 : 1;
382
383 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
384 return 8;
385
386 case PIPE_CAP_MAX_GS_INVOCATIONS:
387 return 32;
388
389 /* shader buffer objects */
390 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
391 return 1 << 27;
392 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
393 return 8;
394
395 /* Unsupported features. */
396 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
397 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
398 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
399 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
400 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
401 case PIPE_CAP_USER_VERTEX_BUFFERS:
402 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
403 case PIPE_CAP_VERTEXID_NOBASE:
404 case PIPE_CAP_DEPTH_BOUNDS_TEST:
405 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
406 case PIPE_CAP_SHAREABLE_SHADERS:
407 case PIPE_CAP_DRAW_PARAMETERS:
408 case PIPE_CAP_MULTI_DRAW_INDIRECT:
409 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
410 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
411 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
412 case PIPE_CAP_GENERATE_MIPMAP:
413 case PIPE_CAP_STRING_MARKER:
414 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
415 case PIPE_CAP_TGSI_VOTE:
416 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
417 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
418 case PIPE_CAP_NATIVE_FENCE_FD:
419 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
420 case PIPE_CAP_TGSI_FS_FBFETCH:
421 case PIPE_CAP_INT64:
422 case PIPE_CAP_INT64_DIVMOD:
423 case PIPE_CAP_TGSI_TEX_TXF_LZ:
424 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
425 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
426 case PIPE_CAP_TGSI_BALLOT:
427 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
428 case PIPE_CAP_POST_DEPTH_COVERAGE:
429 case PIPE_CAP_BINDLESS_TEXTURE:
430 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
431 case PIPE_CAP_QUERY_SO_OVERFLOW:
432 case PIPE_CAP_MEMOBJ:
433 case PIPE_CAP_LOAD_CONSTBUF:
434 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
435 case PIPE_CAP_TILE_RASTER_ORDER:
436 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
437 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
438 case PIPE_CAP_FENCE_SIGNAL:
439 case PIPE_CAP_CONSTBUF0_FLAGS:
440 case PIPE_CAP_PACKED_UNIFORMS:
441 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
442 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
443 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
444 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
445 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
446 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
447 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
448 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
449 return 0;
450
451 case PIPE_CAP_DOUBLES:
452 if (rscreen->b.family == CHIP_ARUBA ||
453 rscreen->b.family == CHIP_CAYMAN ||
454 rscreen->b.family == CHIP_CYPRESS ||
455 rscreen->b.family == CHIP_HEMLOCK)
456 return 1;
457 return 0;
458 case PIPE_CAP_CULL_DISTANCE:
459 return 1;
460
461 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
462 if (family >= CHIP_CEDAR)
463 return 256;
464 return 0;
465
466 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
467 if (family >= CHIP_CEDAR)
468 return 30;
469 else
470 return 0;
471 /* Stream output. */
472 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
473 return rscreen->b.has_streamout ? 4 : 0;
474 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
475 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
476 return rscreen->b.has_streamout ? 1 : 0;
477 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
478 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
479 return 32*4;
480
481 /* Geometry shader output. */
482 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
483 return 1024;
484 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
485 return 16384;
486 case PIPE_CAP_MAX_VERTEX_STREAMS:
487 return family >= CHIP_CEDAR ? 4 : 1;
488
489 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
490 /* Should be 2047, but 2048 is a requirement for GL 4.4 */
491 return 2048;
492
493 /* Texturing. */
494 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
495 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
496 if (family >= CHIP_CEDAR)
497 return 15;
498 else
499 return 14;
500 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
501 /* textures support 8192, but layered rendering supports 2048 */
502 return 12;
503 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
504 /* textures support 8192, but layered rendering supports 2048 */
505 return 2048;
506
507 /* Render targets. */
508 case PIPE_CAP_MAX_RENDER_TARGETS:
509 /* XXX some r6xx are buggy and can only do 4 */
510 return 8;
511
512 case PIPE_CAP_MAX_VIEWPORTS:
513 return R600_MAX_VIEWPORTS;
514 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
515 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
516 return 8;
517
518 /* Timer queries, present when the clock frequency is non zero. */
519 case PIPE_CAP_QUERY_TIME_ELAPSED:
520 return rscreen->b.info.clock_crystal_freq != 0;
521 case PIPE_CAP_QUERY_TIMESTAMP:
522 return rscreen->b.info.drm_minor >= 20 &&
523 rscreen->b.info.clock_crystal_freq != 0;
524
525 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
526 case PIPE_CAP_MIN_TEXEL_OFFSET:
527 return -8;
528
529 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
530 case PIPE_CAP_MAX_TEXEL_OFFSET:
531 return 7;
532
533 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
534 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
535 case PIPE_CAP_ENDIANNESS:
536 return PIPE_ENDIAN_LITTLE;
537
538 case PIPE_CAP_VENDOR_ID:
539 return ATI_VENDOR_ID;
540 case PIPE_CAP_DEVICE_ID:
541 return rscreen->b.info.pci_id;
542 case PIPE_CAP_ACCELERATED:
543 return 1;
544 case PIPE_CAP_VIDEO_MEMORY:
545 return rscreen->b.info.vram_size >> 20;
546 case PIPE_CAP_UMA:
547 return 0;
548 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
549 return rscreen->b.chip_class >= R700;
550 case PIPE_CAP_PCI_GROUP:
551 return rscreen->b.info.pci_domain;
552 case PIPE_CAP_PCI_BUS:
553 return rscreen->b.info.pci_bus;
554 case PIPE_CAP_PCI_DEVICE:
555 return rscreen->b.info.pci_dev;
556 case PIPE_CAP_PCI_FUNCTION:
557 return rscreen->b.info.pci_func;
558
559 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
560 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
561 return 8;
562 return 0;
563 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
564 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
565 return EG_MAX_ATOMIC_BUFFERS;
566 return 0;
567
568 default:
569 return u_pipe_screen_get_param_defaults(pscreen, param);
570 }
571 }
572
573 static int r600_get_shader_param(struct pipe_screen* pscreen,
574 enum pipe_shader_type shader,
575 enum pipe_shader_cap param)
576 {
577 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
578
579 switch(shader)
580 {
581 case PIPE_SHADER_FRAGMENT:
582 case PIPE_SHADER_VERTEX:
583 case PIPE_SHADER_COMPUTE:
584 break;
585 case PIPE_SHADER_GEOMETRY:
586 if (rscreen->b.family >= CHIP_CEDAR)
587 break;
588 /* pre-evergreen geom shaders need newer kernel */
589 if (rscreen->b.info.drm_minor >= 37)
590 break;
591 return 0;
592 case PIPE_SHADER_TESS_CTRL:
593 case PIPE_SHADER_TESS_EVAL:
594 if (rscreen->b.family >= CHIP_CEDAR)
595 break;
596 default:
597 return 0;
598 }
599
600 switch (param) {
601 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
602 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
603 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
604 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
605 return 16384;
606 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
607 return 32;
608 case PIPE_SHADER_CAP_MAX_INPUTS:
609 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
610 case PIPE_SHADER_CAP_MAX_OUTPUTS:
611 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
612 case PIPE_SHADER_CAP_MAX_TEMPS:
613 return 256; /* Max native temporaries. */
614 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
615 if (shader == PIPE_SHADER_COMPUTE) {
616 uint64_t max_const_buffer_size;
617 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
618 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
619 &max_const_buffer_size);
620 return MIN2(max_const_buffer_size, INT_MAX);
621
622 } else {
623 return R600_MAX_CONST_BUFFER_SIZE;
624 }
625 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
626 return R600_MAX_USER_CONST_BUFFERS;
627 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
628 return 1;
629 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
630 return 1;
631 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
632 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
633 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
634 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
635 return 1;
636 case PIPE_SHADER_CAP_SUBROUTINES:
637 case PIPE_SHADER_CAP_INT64_ATOMICS:
638 case PIPE_SHADER_CAP_FP16:
639 return 0;
640 case PIPE_SHADER_CAP_INTEGERS:
641 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
642 return 1;
643 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
644 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
645 return 16;
646 case PIPE_SHADER_CAP_PREFERRED_IR:
647 return PIPE_SHADER_IR_TGSI;
648 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
649 int ir = 0;
650 if (shader == PIPE_SHADER_COMPUTE)
651 ir = 1 << PIPE_SHADER_IR_NATIVE;
652 if (rscreen->b.family >= CHIP_CEDAR)
653 ir |= 1 << PIPE_SHADER_IR_TGSI;
654 return ir;
655 }
656 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
657 if (rscreen->b.family == CHIP_ARUBA ||
658 rscreen->b.family == CHIP_CAYMAN ||
659 rscreen->b.family == CHIP_CYPRESS ||
660 rscreen->b.family == CHIP_HEMLOCK)
661 return 1;
662 return 0;
663 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
664 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
665 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
666 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
667 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
668 return 0;
669 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
670 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
671 if (rscreen->b.family >= CHIP_CEDAR &&
672 (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE))
673 return 8;
674 return 0;
675 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
676 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
677 return 8;
678 return 0;
679 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
680 /* having to allocate the atomics out amongst shaders stages is messy,
681 so give compute 8 buffers and all the others one */
682 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) {
683 return EG_MAX_ATOMIC_BUFFERS;
684 }
685 return 0;
686 case PIPE_SHADER_CAP_SCALAR_ISA:
687 return 0;
688 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
689 /* due to a bug in the shader compiler, some loops hang
690 * if they are not unrolled, see:
691 * https://bugs.freedesktop.org/show_bug.cgi?id=86720
692 */
693 return 255;
694 }
695 return 0;
696 }
697
698 static void r600_destroy_screen(struct pipe_screen* pscreen)
699 {
700 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
701
702 if (!rscreen)
703 return;
704
705 if (!rscreen->b.ws->unref(rscreen->b.ws))
706 return;
707
708 if (rscreen->global_pool) {
709 compute_memory_pool_delete(rscreen->global_pool);
710 }
711
712 r600_destroy_common_screen(&rscreen->b);
713 }
714
715 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
716 const struct pipe_resource *templ)
717 {
718 if (templ->target == PIPE_BUFFER &&
719 (templ->bind & PIPE_BIND_GLOBAL))
720 return r600_compute_global_buffer_create(screen, templ);
721
722 return r600_resource_create_common(screen, templ);
723 }
724
725 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws,
726 const struct pipe_screen_config *config)
727 {
728 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
729
730 if (!rscreen) {
731 return NULL;
732 }
733
734 /* Set functions first. */
735 rscreen->b.b.context_create = r600_create_context;
736 rscreen->b.b.destroy = r600_destroy_screen;
737 rscreen->b.b.get_param = r600_get_param;
738 rscreen->b.b.get_shader_param = r600_get_shader_param;
739 rscreen->b.b.resource_create = r600_resource_create;
740
741 if (!r600_common_screen_init(&rscreen->b, ws)) {
742 FREE(rscreen);
743 return NULL;
744 }
745
746 if (rscreen->b.info.chip_class >= EVERGREEN) {
747 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
748 } else {
749 rscreen->b.b.is_format_supported = r600_is_format_supported;
750 }
751
752 rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
753 if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
754 rscreen->b.debug_flags |= DBG_COMPUTE;
755 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
756 rscreen->b.debug_flags |= DBG_ALL_SHADERS | DBG_FS;
757 if (!debug_get_bool_option("R600_HYPERZ", TRUE))
758 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
759
760 if (rscreen->b.family == CHIP_UNKNOWN) {
761 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
762 FREE(rscreen);
763 return NULL;
764 }
765
766 /* Figure out streamout kernel support. */
767 switch (rscreen->b.chip_class) {
768 case R600:
769 if (rscreen->b.family < CHIP_RS780) {
770 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
771 } else {
772 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
773 }
774 break;
775 case R700:
776 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
777 break;
778 case EVERGREEN:
779 case CAYMAN:
780 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
781 break;
782 default:
783 rscreen->b.has_streamout = FALSE;
784 break;
785 }
786
787 /* MSAA support. */
788 switch (rscreen->b.chip_class) {
789 case R600:
790 case R700:
791 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
792 rscreen->has_compressed_msaa_texturing = false;
793 break;
794 case EVERGREEN:
795 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
796 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
797 break;
798 case CAYMAN:
799 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
800 rscreen->has_compressed_msaa_texturing = true;
801 break;
802 default:
803 rscreen->has_msaa = FALSE;
804 rscreen->has_compressed_msaa_texturing = false;
805 }
806
807 rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
808 !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
809
810 rscreen->b.barrier_flags.cp_to_L2 =
811 R600_CONTEXT_INV_VERTEX_CACHE |
812 R600_CONTEXT_INV_TEX_CACHE |
813 R600_CONTEXT_INV_CONST_CACHE;
814 rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_CS_PARTIAL_FLUSH | R600_CONTEXT_FLUSH_AND_INV;
815
816 rscreen->global_pool = compute_memory_pool_new(rscreen);
817
818 /* Create the auxiliary context. This must be done last. */
819 rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
820
821 rscreen->has_atomics = rscreen->b.info.drm_minor >= 44;
822 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
823 struct pipe_resource templ = {};
824
825 templ.width0 = 4;
826 templ.height0 = 2048;
827 templ.depth0 = 1;
828 templ.array_size = 1;
829 templ.target = PIPE_TEXTURE_2D;
830 templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
831 templ.usage = PIPE_USAGE_DEFAULT;
832
833 struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
834 unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_TRANSFER_WRITE);
835
836 memset(map, 0, 256);
837
838 r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
839 r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
840 r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
841 r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
842 r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
843
844 ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
845
846 int i;
847 for (i = 0; i < 256; i++) {
848 printf("%02X", map[i]);
849 if (i % 16 == 15)
850 printf("\n");
851 }
852 #endif
853
854 if (rscreen->b.debug_flags & DBG_TEST_DMA)
855 r600_test_dma(&rscreen->b);
856
857 r600_query_fix_enabled_rb_mask(&rscreen->b);
858 return &rscreen->b.b;
859 }