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296d4660182d28270dbea32fd0fcc59b6fb4d1e1
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_pipe.h"
24 #include "r600_public.h"
25 #include "r600_isa.h"
26 #include "evergreen_compute.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include <errno.h>
32 #include "pipe/p_shader_tokens.h"
33 #include "util/u_blitter.h"
34 #include "util/u_debug.h"
35 #include "util/u_memory.h"
36 #include "util/u_simple_shaders.h"
37 #include "util/u_upload_mgr.h"
38 #include "util/u_math.h"
39 #include "vl/vl_decoder.h"
40 #include "vl/vl_video_buffer.h"
41 #include "radeon/radeon_uvd.h"
42 #include "os/os_time.h"
43
44 static const struct debug_named_value r600_debug_options[] = {
45 /* features */
46 #if defined(R600_USE_LLVM)
47 { "nollvm", DBG_NO_LLVM, "Disable the LLVM shader compiler" },
48 #endif
49 { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
50 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
51
52 /* shader backend */
53 { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
54 { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
55 { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
56 { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
57 { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
58 { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
59 { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
60 { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
61
62 DEBUG_NAMED_VALUE_END /* must be last */
63 };
64
65 /*
66 * pipe_context
67 */
68
69 static void r600_flush(struct pipe_context *ctx, unsigned flags)
70 {
71 struct r600_context *rctx = (struct r600_context *)ctx;
72 struct pipe_query *render_cond = NULL;
73 unsigned render_cond_mode = 0;
74 boolean render_cond_cond = FALSE;
75
76 if (rctx->b.rings.gfx.cs->cdw == rctx->initial_gfx_cs_size)
77 return;
78
79 rctx->b.rings.gfx.flushing = true;
80 /* Disable render condition. */
81 if (rctx->current_render_cond) {
82 render_cond = rctx->current_render_cond;
83 render_cond_cond = rctx->current_render_cond_cond;
84 render_cond_mode = rctx->current_render_cond_mode;
85 ctx->render_condition(ctx, NULL, FALSE, 0);
86 }
87
88 r600_context_flush(rctx, flags);
89 rctx->b.rings.gfx.flushing = false;
90 r600_begin_new_cs(rctx);
91
92 /* Re-enable render condition. */
93 if (render_cond) {
94 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
95 }
96
97 rctx->initial_gfx_cs_size = rctx->b.rings.gfx.cs->cdw;
98 }
99
100 static void r600_flush_from_st(struct pipe_context *ctx,
101 struct pipe_fence_handle **fence,
102 unsigned flags)
103 {
104 struct r600_context *rctx = (struct r600_context *)ctx;
105 unsigned fflags;
106
107 fflags = flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0;
108 if (fence) {
109 *fence = rctx->b.ws->cs_create_fence(rctx->b.rings.gfx.cs);
110 }
111 /* flush gfx & dma ring, order does not matter as only one can be live */
112 if (rctx->b.rings.dma.cs) {
113 rctx->b.rings.dma.flush(rctx, fflags);
114 }
115 rctx->b.rings.gfx.flush(rctx, fflags);
116 }
117
118 static void r600_flush_gfx_ring(void *ctx, unsigned flags)
119 {
120 r600_flush((struct pipe_context*)ctx, flags);
121 }
122
123 static void r600_flush_dma_ring(void *ctx, unsigned flags)
124 {
125 struct r600_context *rctx = (struct r600_context *)ctx;
126 struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
127
128 if (!cs->cdw) {
129 return;
130 }
131
132 rctx->b.rings.dma.flushing = true;
133 rctx->b.ws->cs_flush(cs, flags, 0);
134 rctx->b.rings.dma.flushing = false;
135 }
136
137 static void r600_flush_from_winsys(void *ctx, unsigned flags)
138 {
139 struct r600_context *rctx = (struct r600_context *)ctx;
140
141 rctx->b.rings.gfx.flush(rctx, flags);
142 }
143
144 static void r600_flush_dma_from_winsys(void *ctx, unsigned flags)
145 {
146 struct r600_context *rctx = (struct r600_context *)ctx;
147
148 rctx->b.rings.dma.flush(rctx, flags);
149 }
150
151 static void r600_destroy_context(struct pipe_context *context)
152 {
153 struct r600_context *rctx = (struct r600_context *)context;
154
155 r600_isa_destroy(rctx->isa);
156
157 r600_sb_context_destroy(rctx->sb_context);
158
159 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
160 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
161
162 if (rctx->dummy_pixel_shader) {
163 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
164 }
165 if (rctx->custom_dsa_flush) {
166 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
167 }
168 if (rctx->custom_blend_resolve) {
169 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
170 }
171 if (rctx->custom_blend_decompress) {
172 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
173 }
174 if (rctx->custom_blend_fastclear) {
175 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
176 }
177 util_unreference_framebuffer_state(&rctx->framebuffer.state);
178
179 if (rctx->blitter) {
180 util_blitter_destroy(rctx->blitter);
181 }
182 if (rctx->uploader) {
183 u_upload_destroy(rctx->uploader);
184 }
185 if (rctx->allocator_fetch_shader) {
186 u_suballocator_destroy(rctx->allocator_fetch_shader);
187 }
188 util_slab_destroy(&rctx->pool_transfers);
189
190 r600_release_command_buffer(&rctx->start_cs_cmd);
191
192 if (rctx->b.rings.gfx.cs) {
193 rctx->b.ws->cs_destroy(rctx->b.rings.gfx.cs);
194 }
195 if (rctx->b.rings.dma.cs) {
196 rctx->b.ws->cs_destroy(rctx->b.rings.dma.cs);
197 }
198
199 r600_common_context_cleanup(&rctx->b);
200 FREE(rctx);
201 }
202
203 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
204 {
205 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
206 struct r600_screen* rscreen = (struct r600_screen *)screen;
207
208 if (rctx == NULL)
209 return NULL;
210
211 util_slab_create(&rctx->pool_transfers,
212 sizeof(struct r600_transfer), 64,
213 UTIL_SLAB_SINGLETHREADED);
214
215 rctx->b.b.screen = screen;
216 rctx->b.b.priv = priv;
217 rctx->b.b.destroy = r600_destroy_context;
218 rctx->b.b.flush = r600_flush_from_st;
219
220 if (!r600_common_context_init(&rctx->b, &rscreen->b))
221 goto fail;
222
223 rctx->screen = rscreen;
224 rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
225
226 LIST_INITHEAD(&rctx->active_nontimer_queries);
227
228 r600_init_blit_functions(rctx);
229 r600_init_query_functions(rctx);
230 r600_init_context_resource_functions(rctx);
231
232 if (rscreen->b.info.has_uvd) {
233 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
234 rctx->b.b.create_video_buffer = r600_video_buffer_create;
235 } else {
236 rctx->b.b.create_video_codec = vl_create_decoder;
237 rctx->b.b.create_video_buffer = vl_video_buffer_create;
238 }
239
240 r600_init_common_state_functions(rctx);
241
242 switch (rctx->b.chip_class) {
243 case R600:
244 case R700:
245 r600_init_state_functions(rctx);
246 r600_init_atom_start_cs(rctx);
247 rctx->max_db = 4;
248 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
249 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
250 : r600_create_resolve_blend(rctx);
251 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
252 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
253 rctx->b.family == CHIP_RV620 ||
254 rctx->b.family == CHIP_RS780 ||
255 rctx->b.family == CHIP_RS880 ||
256 rctx->b.family == CHIP_RV710);
257 break;
258 case EVERGREEN:
259 case CAYMAN:
260 evergreen_init_state_functions(rctx);
261 evergreen_init_atom_start_cs(rctx);
262 evergreen_init_atom_start_compute_cs(rctx);
263 rctx->max_db = 8;
264 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
265 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
266 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
267 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
268 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
269 rctx->b.family == CHIP_PALM ||
270 rctx->b.family == CHIP_SUMO ||
271 rctx->b.family == CHIP_SUMO2 ||
272 rctx->b.family == CHIP_CAICOS ||
273 rctx->b.family == CHIP_CAYMAN ||
274 rctx->b.family == CHIP_ARUBA);
275 break;
276 default:
277 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
278 goto fail;
279 }
280
281 if (rscreen->trace_bo) {
282 rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, rscreen->trace_bo->cs_buf);
283 } else {
284 rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, NULL);
285 }
286 rctx->b.rings.gfx.flush = r600_flush_gfx_ring;
287 rctx->b.ws->cs_set_flush_callback(rctx->b.rings.gfx.cs, r600_flush_from_winsys, rctx);
288 rctx->b.rings.gfx.flushing = false;
289
290 rctx->b.rings.dma.cs = NULL;
291 if (rscreen->b.info.r600_has_dma && !(rscreen->b.debug_flags & DBG_NO_ASYNC_DMA)) {
292 rctx->b.rings.dma.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_DMA, NULL);
293 rctx->b.rings.dma.flush = r600_flush_dma_ring;
294 rctx->b.ws->cs_set_flush_callback(rctx->b.rings.dma.cs, r600_flush_dma_from_winsys, rctx);
295 rctx->b.rings.dma.flushing = false;
296 }
297
298 rctx->uploader = u_upload_create(&rctx->b.b, 1024 * 1024, 256,
299 PIPE_BIND_INDEX_BUFFER |
300 PIPE_BIND_CONSTANT_BUFFER);
301 if (!rctx->uploader)
302 goto fail;
303
304 rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
305 0, PIPE_USAGE_STATIC, FALSE);
306 if (!rctx->allocator_fetch_shader)
307 goto fail;
308
309 rctx->isa = calloc(1, sizeof(struct r600_isa));
310 if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
311 goto fail;
312
313 rctx->blitter = util_blitter_create(&rctx->b.b);
314 if (rctx->blitter == NULL)
315 goto fail;
316 util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
317 rctx->blitter->draw_rectangle = r600_draw_rectangle;
318
319 r600_begin_new_cs(rctx);
320 r600_get_backend_mask(rctx); /* this emits commands and must be last */
321
322 rctx->dummy_pixel_shader =
323 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
324 TGSI_SEMANTIC_GENERIC,
325 TGSI_INTERPOLATE_CONSTANT);
326 rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
327
328 return &rctx->b.b;
329
330 fail:
331 r600_destroy_context(&rctx->b.b);
332 return NULL;
333 }
334
335 /*
336 * pipe_screen
337 */
338 static const char* r600_get_vendor(struct pipe_screen* pscreen)
339 {
340 return "X.Org";
341 }
342
343 static const char *r600_get_family_name(enum radeon_family family)
344 {
345 switch(family) {
346 case CHIP_R600: return "AMD R600";
347 case CHIP_RV610: return "AMD RV610";
348 case CHIP_RV630: return "AMD RV630";
349 case CHIP_RV670: return "AMD RV670";
350 case CHIP_RV620: return "AMD RV620";
351 case CHIP_RV635: return "AMD RV635";
352 case CHIP_RS780: return "AMD RS780";
353 case CHIP_RS880: return "AMD RS880";
354 case CHIP_RV770: return "AMD RV770";
355 case CHIP_RV730: return "AMD RV730";
356 case CHIP_RV710: return "AMD RV710";
357 case CHIP_RV740: return "AMD RV740";
358 case CHIP_CEDAR: return "AMD CEDAR";
359 case CHIP_REDWOOD: return "AMD REDWOOD";
360 case CHIP_JUNIPER: return "AMD JUNIPER";
361 case CHIP_CYPRESS: return "AMD CYPRESS";
362 case CHIP_HEMLOCK: return "AMD HEMLOCK";
363 case CHIP_PALM: return "AMD PALM";
364 case CHIP_SUMO: return "AMD SUMO";
365 case CHIP_SUMO2: return "AMD SUMO2";
366 case CHIP_BARTS: return "AMD BARTS";
367 case CHIP_TURKS: return "AMD TURKS";
368 case CHIP_CAICOS: return "AMD CAICOS";
369 case CHIP_CAYMAN: return "AMD CAYMAN";
370 case CHIP_ARUBA: return "AMD ARUBA";
371 default: return "AMD unknown";
372 }
373 }
374
375 static const char* r600_get_name(struct pipe_screen* pscreen)
376 {
377 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
378
379 return r600_get_family_name(rscreen->b.family);
380 }
381
382 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
383 {
384 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
385 enum radeon_family family = rscreen->b.family;
386
387 switch (param) {
388 /* Supported features (boolean caps). */
389 case PIPE_CAP_NPOT_TEXTURES:
390 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
391 case PIPE_CAP_TWO_SIDED_STENCIL:
392 case PIPE_CAP_ANISOTROPIC_FILTER:
393 case PIPE_CAP_POINT_SPRITE:
394 case PIPE_CAP_OCCLUSION_QUERY:
395 case PIPE_CAP_TEXTURE_SHADOW_MAP:
396 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
397 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
398 case PIPE_CAP_TEXTURE_SWIZZLE:
399 case PIPE_CAP_DEPTH_CLIP_DISABLE:
400 case PIPE_CAP_SHADER_STENCIL_EXPORT:
401 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
402 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
403 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
404 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
405 case PIPE_CAP_SM3:
406 case PIPE_CAP_SEAMLESS_CUBE_MAP:
407 case PIPE_CAP_PRIMITIVE_RESTART:
408 case PIPE_CAP_CONDITIONAL_RENDER:
409 case PIPE_CAP_TEXTURE_BARRIER:
410 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
411 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
412 case PIPE_CAP_TGSI_INSTANCEID:
413 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
414 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
415 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
416 case PIPE_CAP_USER_INDEX_BUFFERS:
417 case PIPE_CAP_USER_CONSTANT_BUFFERS:
418 case PIPE_CAP_COMPUTE:
419 case PIPE_CAP_START_INSTANCE:
420 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
421 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
422 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
423 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
424 case PIPE_CAP_TEXTURE_MULTISAMPLE:
425 return 1;
426
427 case PIPE_CAP_TGSI_TEXCOORD:
428 return 0;
429
430 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
431 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
432
433 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
434 return R600_MAP_BUFFER_ALIGNMENT;
435
436 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
437 return 256;
438
439 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
440 return 1;
441
442 case PIPE_CAP_GLSL_FEATURE_LEVEL:
443 return 140;
444
445 /* Supported except the original R600. */
446 case PIPE_CAP_INDEP_BLEND_ENABLE:
447 case PIPE_CAP_INDEP_BLEND_FUNC:
448 /* R600 doesn't support per-MRT blends */
449 return family == CHIP_R600 ? 0 : 1;
450
451 /* Supported on Evergreen. */
452 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
453 case PIPE_CAP_CUBE_MAP_ARRAY:
454 return family >= CHIP_CEDAR ? 1 : 0;
455
456 /* Unsupported features. */
457 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
458 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
459 case PIPE_CAP_SCALED_RESOLVE:
460 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
461 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
462 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
463 case PIPE_CAP_USER_VERTEX_BUFFERS:
464 case PIPE_CAP_TGSI_VS_LAYER:
465 return 0;
466
467 /* Stream output. */
468 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
469 return rscreen->b.has_streamout ? 4 : 0;
470 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
471 return rscreen->b.has_streamout ? 1 : 0;
472 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
473 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
474 return 32*4;
475
476 /* Texturing. */
477 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
478 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
479 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
480 if (family >= CHIP_CEDAR)
481 return 15;
482 else
483 return 14;
484 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
485 return rscreen->b.info.drm_minor >= 9 ?
486 (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
487 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
488 return 32;
489
490 /* Render targets. */
491 case PIPE_CAP_MAX_RENDER_TARGETS:
492 /* XXX some r6xx are buggy and can only do 4 */
493 return 8;
494
495 case PIPE_CAP_MAX_VIEWPORTS:
496 return 1;
497
498 /* Timer queries, present when the clock frequency is non zero. */
499 case PIPE_CAP_QUERY_TIME_ELAPSED:
500 return rscreen->b.info.r600_clock_crystal_freq != 0;
501 case PIPE_CAP_QUERY_TIMESTAMP:
502 return rscreen->b.info.drm_minor >= 20 &&
503 rscreen->b.info.r600_clock_crystal_freq != 0;
504
505 case PIPE_CAP_MIN_TEXEL_OFFSET:
506 return -8;
507
508 case PIPE_CAP_MAX_TEXEL_OFFSET:
509 return 7;
510
511 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
512 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
513 case PIPE_CAP_ENDIANNESS:
514 return PIPE_ENDIAN_LITTLE;
515 }
516 return 0;
517 }
518
519 static float r600_get_paramf(struct pipe_screen* pscreen,
520 enum pipe_capf param)
521 {
522 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
523 enum radeon_family family = rscreen->b.family;
524
525 switch (param) {
526 case PIPE_CAPF_MAX_LINE_WIDTH:
527 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
528 case PIPE_CAPF_MAX_POINT_WIDTH:
529 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
530 if (family >= CHIP_CEDAR)
531 return 16384.0f;
532 else
533 return 8192.0f;
534 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
535 return 16.0f;
536 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
537 return 16.0f;
538 case PIPE_CAPF_GUARD_BAND_LEFT:
539 case PIPE_CAPF_GUARD_BAND_TOP:
540 case PIPE_CAPF_GUARD_BAND_RIGHT:
541 case PIPE_CAPF_GUARD_BAND_BOTTOM:
542 return 0.0f;
543 }
544 return 0.0f;
545 }
546
547 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
548 {
549 switch(shader)
550 {
551 case PIPE_SHADER_FRAGMENT:
552 case PIPE_SHADER_VERTEX:
553 case PIPE_SHADER_COMPUTE:
554 break;
555 case PIPE_SHADER_GEOMETRY:
556 /* XXX: support and enable geometry programs */
557 return 0;
558 default:
559 /* XXX: support tessellation on Evergreen */
560 return 0;
561 }
562
563 switch (param) {
564 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
565 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
566 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
567 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
568 return 16384;
569 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
570 return 32;
571 case PIPE_SHADER_CAP_MAX_INPUTS:
572 return 32;
573 case PIPE_SHADER_CAP_MAX_TEMPS:
574 return 256; /* Max native temporaries. */
575 case PIPE_SHADER_CAP_MAX_ADDRS:
576 /* XXX Isn't this equal to TEMPS? */
577 return 1; /* Max native address registers */
578 case PIPE_SHADER_CAP_MAX_CONSTS:
579 return R600_MAX_CONST_BUFFER_SIZE;
580 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
581 return R600_MAX_USER_CONST_BUFFERS;
582 case PIPE_SHADER_CAP_MAX_PREDS:
583 return 0; /* nothing uses this */
584 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
585 return 1;
586 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
587 return 0;
588 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
589 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
590 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
591 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
592 return 1;
593 case PIPE_SHADER_CAP_SUBROUTINES:
594 return 0;
595 case PIPE_SHADER_CAP_INTEGERS:
596 return 1;
597 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
598 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
599 return 16;
600 case PIPE_SHADER_CAP_PREFERRED_IR:
601 if (shader == PIPE_SHADER_COMPUTE) {
602 return PIPE_SHADER_IR_LLVM;
603 } else {
604 return PIPE_SHADER_IR_TGSI;
605 }
606 }
607 return 0;
608 }
609
610 static int r600_get_video_param(struct pipe_screen *screen,
611 enum pipe_video_profile profile,
612 enum pipe_video_entrypoint entrypoint,
613 enum pipe_video_cap param)
614 {
615 switch (param) {
616 case PIPE_VIDEO_CAP_SUPPORTED:
617 return vl_profile_supported(screen, profile, entrypoint);
618 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
619 return 1;
620 case PIPE_VIDEO_CAP_MAX_WIDTH:
621 case PIPE_VIDEO_CAP_MAX_HEIGHT:
622 return vl_video_buffer_max_size(screen);
623 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
624 return PIPE_FORMAT_NV12;
625 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
626 return false;
627 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
628 return false;
629 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
630 return true;
631 case PIPE_VIDEO_CAP_MAX_LEVEL:
632 return vl_level_supported(screen, profile);
633 default:
634 return 0;
635 }
636 }
637
638 const char * r600_llvm_gpu_string(enum radeon_family family)
639 {
640 const char * gpu_family;
641
642 switch (family) {
643 case CHIP_R600:
644 case CHIP_RV630:
645 case CHIP_RV635:
646 case CHIP_RV670:
647 gpu_family = "r600";
648 break;
649 case CHIP_RV610:
650 case CHIP_RV620:
651 case CHIP_RS780:
652 case CHIP_RS880:
653 gpu_family = "rs880";
654 break;
655 case CHIP_RV710:
656 gpu_family = "rv710";
657 break;
658 case CHIP_RV730:
659 gpu_family = "rv730";
660 break;
661 case CHIP_RV740:
662 case CHIP_RV770:
663 gpu_family = "rv770";
664 break;
665 case CHIP_PALM:
666 case CHIP_CEDAR:
667 gpu_family = "cedar";
668 break;
669 case CHIP_SUMO:
670 case CHIP_SUMO2:
671 gpu_family = "sumo";
672 break;
673 case CHIP_REDWOOD:
674 gpu_family = "redwood";
675 break;
676 case CHIP_JUNIPER:
677 gpu_family = "juniper";
678 break;
679 case CHIP_HEMLOCK:
680 case CHIP_CYPRESS:
681 gpu_family = "cypress";
682 break;
683 case CHIP_BARTS:
684 gpu_family = "barts";
685 break;
686 case CHIP_TURKS:
687 gpu_family = "turks";
688 break;
689 case CHIP_CAICOS:
690 gpu_family = "caicos";
691 break;
692 case CHIP_CAYMAN:
693 case CHIP_ARUBA:
694 gpu_family = "cayman";
695 break;
696 default:
697 gpu_family = "";
698 fprintf(stderr, "Chip not supported by r600 llvm "
699 "backend, please file a bug at " PACKAGE_BUGREPORT "\n");
700 break;
701 }
702 return gpu_family;
703 }
704
705
706 static int r600_get_compute_param(struct pipe_screen *screen,
707 enum pipe_compute_cap param,
708 void *ret)
709 {
710 struct r600_screen *rscreen = (struct r600_screen *)screen;
711 //TODO: select these params by asic
712 switch (param) {
713 case PIPE_COMPUTE_CAP_IR_TARGET: {
714 const char *gpu = r600_llvm_gpu_string(rscreen->b.family);
715 if (ret) {
716 sprintf(ret, "%s-r600--", gpu);
717 }
718 return (8 + strlen(gpu)) * sizeof(char);
719 }
720 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
721 if (ret) {
722 uint64_t * grid_dimension = ret;
723 grid_dimension[0] = 3;
724 }
725 return 1 * sizeof(uint64_t);
726
727 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
728 if (ret) {
729 uint64_t * grid_size = ret;
730 grid_size[0] = 65535;
731 grid_size[1] = 65535;
732 grid_size[2] = 1;
733 }
734 return 3 * sizeof(uint64_t) ;
735
736 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
737 if (ret) {
738 uint64_t * block_size = ret;
739 block_size[0] = 256;
740 block_size[1] = 256;
741 block_size[2] = 256;
742 }
743 return 3 * sizeof(uint64_t);
744
745 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
746 if (ret) {
747 uint64_t * max_threads_per_block = ret;
748 *max_threads_per_block = 256;
749 }
750 return sizeof(uint64_t);
751
752 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
753 if (ret) {
754 uint64_t * max_global_size = ret;
755 /* XXX: This is what the proprietary driver reports, we
756 * may want to use a different value. */
757 *max_global_size = 201326592;
758 }
759 return sizeof(uint64_t);
760
761 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
762 if (ret) {
763 uint64_t * max_input_size = ret;
764 *max_input_size = 1024;
765 }
766 return sizeof(uint64_t);
767
768 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
769 if (ret) {
770 uint64_t * max_local_size = ret;
771 /* XXX: This is what the proprietary driver reports, we
772 * may want to use a different value. */
773 *max_local_size = 32768;
774 }
775 return sizeof(uint64_t);
776
777 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
778 if (ret) {
779 uint64_t max_global_size;
780 uint64_t * max_mem_alloc_size = ret;
781 r600_get_compute_param(screen,
782 PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
783 &max_global_size);
784 /* OpenCL requres this value be at least
785 * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
786 * I'm really not sure what value to report here, but
787 * MAX_GLOBAL_SIZE / 4 seems resonable.
788 */
789 *max_mem_alloc_size = max_global_size / 4;
790 }
791 return sizeof(uint64_t);
792
793 default:
794 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
795 return 0;
796 }
797 }
798
799 static void r600_destroy_screen(struct pipe_screen* pscreen)
800 {
801 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
802
803 if (rscreen == NULL)
804 return;
805
806 if (!radeon_winsys_unref(rscreen->b.ws))
807 return;
808
809 r600_common_screen_cleanup(&rscreen->b);
810
811 if (rscreen->global_pool) {
812 compute_memory_pool_delete(rscreen->global_pool);
813 }
814
815 if (rscreen->trace_bo) {
816 rscreen->b.ws->buffer_unmap(rscreen->trace_bo->cs_buf);
817 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
818 }
819
820 rscreen->b.ws->destroy(rscreen->b.ws);
821 FREE(rscreen);
822 }
823
824 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
825 {
826 struct r600_screen *rscreen = (struct r600_screen*)screen;
827
828 return 1000000 * rscreen->b.ws->query_value(rscreen->b.ws, RADEON_TIMESTAMP) /
829 rscreen->b.info.r600_clock_crystal_freq;
830 }
831
832 static int r600_get_driver_query_info(struct pipe_screen *screen,
833 unsigned index,
834 struct pipe_driver_query_info *info)
835 {
836 struct r600_screen *rscreen = (struct r600_screen*)screen;
837 struct pipe_driver_query_info list[] = {
838 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
839 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->b.info.vram_size, TRUE},
840 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->b.info.gart_size, TRUE},
841 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE}
842 };
843
844 if (!info)
845 return Elements(list);
846
847 if (index >= Elements(list))
848 return 0;
849
850 *info = list[index];
851 return 1;
852 }
853
854 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
855 {
856 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
857
858 if (rscreen == NULL) {
859 return NULL;
860 }
861
862 ws->query_info(ws, &rscreen->b.info);
863
864 /* Set functions first. */
865 rscreen->b.b.context_create = r600_create_context;
866 rscreen->b.b.destroy = r600_destroy_screen;
867 rscreen->b.b.get_name = r600_get_name;
868 rscreen->b.b.get_vendor = r600_get_vendor;
869 rscreen->b.b.get_param = r600_get_param;
870 rscreen->b.b.get_shader_param = r600_get_shader_param;
871 rscreen->b.b.get_paramf = r600_get_paramf;
872 rscreen->b.b.get_compute_param = r600_get_compute_param;
873 rscreen->b.b.get_timestamp = r600_get_timestamp;
874 if (rscreen->b.info.chip_class >= EVERGREEN) {
875 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
876 } else {
877 rscreen->b.b.is_format_supported = r600_is_format_supported;
878 }
879 rscreen->b.b.get_driver_query_info = r600_get_driver_query_info;
880 if (rscreen->b.info.has_uvd) {
881 rscreen->b.b.get_video_param = ruvd_get_video_param;
882 rscreen->b.b.is_video_format_supported = ruvd_is_format_supported;
883 } else {
884 rscreen->b.b.get_video_param = r600_get_video_param;
885 rscreen->b.b.is_video_format_supported = vl_video_buffer_is_format_supported;
886 }
887 r600_init_screen_resource_functions(&rscreen->b.b);
888
889 if (!r600_common_screen_init(&rscreen->b, ws)) {
890 FREE(rscreen);
891 return NULL;
892 }
893
894 rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
895 if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
896 rscreen->b.debug_flags |= DBG_COMPUTE;
897 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
898 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
899 if (!debug_get_bool_option("R600_HYPERZ", TRUE))
900 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
901 if (!debug_get_bool_option("R600_LLVM", TRUE))
902 rscreen->b.debug_flags |= DBG_NO_LLVM;
903
904 if (rscreen->b.family == CHIP_UNKNOWN) {
905 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
906 FREE(rscreen);
907 return NULL;
908 }
909
910 /* Figure out streamout kernel support. */
911 switch (rscreen->b.chip_class) {
912 case R600:
913 if (rscreen->b.family < CHIP_RS780) {
914 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
915 } else {
916 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
917 }
918 break;
919 case R700:
920 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
921 break;
922 case EVERGREEN:
923 case CAYMAN:
924 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
925 break;
926 default:
927 rscreen->b.has_streamout = FALSE;
928 break;
929 }
930
931 /* MSAA support. */
932 switch (rscreen->b.chip_class) {
933 case R600:
934 case R700:
935 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
936 rscreen->has_compressed_msaa_texturing = false;
937 break;
938 case EVERGREEN:
939 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
940 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
941 break;
942 case CAYMAN:
943 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
944 rscreen->has_compressed_msaa_texturing = true;
945 break;
946 default:
947 rscreen->has_msaa = FALSE;
948 rscreen->has_compressed_msaa_texturing = false;
949 }
950
951 rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
952 !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
953
954 rscreen->global_pool = compute_memory_pool_new(rscreen);
955
956 rscreen->cs_count = 0;
957 if (rscreen->b.info.drm_minor >= 28 && (rscreen->b.debug_flags & DBG_TRACE_CS)) {
958 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b.b,
959 PIPE_BIND_CUSTOM,
960 PIPE_USAGE_STAGING,
961 4096);
962 if (rscreen->trace_bo) {
963 rscreen->trace_ptr = rscreen->b.ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
964 PIPE_TRANSFER_UNSYNCHRONIZED);
965 }
966 }
967
968 /* Create the auxiliary context. This must be done last. */
969 rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
970
971 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
972 struct pipe_resource templ = {};
973
974 templ.width0 = 4;
975 templ.height0 = 2048;
976 templ.depth0 = 1;
977 templ.array_size = 1;
978 templ.target = PIPE_TEXTURE_2D;
979 templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
980 templ.usage = PIPE_USAGE_STATIC;
981
982 struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
983 unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
984
985 memset(map, 0, 256);
986
987 r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
988 r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
989 r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
990 r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
991 r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
992
993 ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
994
995 int i;
996 for (i = 0; i < 256; i++) {
997 printf("%02X", map[i]);
998 if (i % 16 == 15)
999 printf("\n");
1000 }
1001 #endif
1002
1003 return &rscreen->b.b;
1004 }