src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_blitter.h"
  34 #include "util/u_debug.h"
  35 #include "util/u_memory.h"
  36 #include "util/u_simple_shaders.h"
  37 #include "util/u_upload_mgr.h"
  38 #include "util/u_math.h"
  39 #include "vl/vl_decoder.h"
  40 #include "vl/vl_video_buffer.h"
  41 #include "radeon/radeon_uvd.h"
  42 #include "os/os_time.h"
  43
  44 static const struct debug_named_value r600_debug_options[] = {
  45         /* features */
  46 #if defined(R600_USE_LLVM)
  47         { "nollvm", DBG_NO_LLVM, "Disable the LLVM shader compiler" },
  48 #endif
  49         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  50         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
  51
  52         /* shader backend */
  53         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  54         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  55         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  56         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  57         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  58         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  59         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  60         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  61
  62         DEBUG_NAMED_VALUE_END /* must be last */
  63 };
  64
  65 /*
  66  * pipe_context
  67  */
  68
  69 static void r600_flush(struct pipe_context *ctx, unsigned flags)
  70 {
  71         struct r600_context *rctx = (struct r600_context *)ctx;
  72         struct pipe_query *render_cond = NULL;
  73         unsigned render_cond_mode = 0;
  74         boolean render_cond_cond = FALSE;
  75
  76         if (rctx->b.rings.gfx.cs->cdw == rctx->initial_gfx_cs_size)
  77                 return;
  78
  79         rctx->b.rings.gfx.flushing = true;
  80         /* Disable render condition. */
  81         if (rctx->current_render_cond) {
  82                 render_cond = rctx->current_render_cond;
  83                 render_cond_cond = rctx->current_render_cond_cond;
  84                 render_cond_mode = rctx->current_render_cond_mode;
  85                 ctx->render_condition(ctx, NULL, FALSE, 0);
  86         }
  87
  88         r600_context_flush(rctx, flags);
  89         rctx->b.rings.gfx.flushing = false;
  90         r600_begin_new_cs(rctx);
  91
  92         /* Re-enable render condition. */
  93         if (render_cond) {
  94                 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
  95         }
  96
  97         rctx->initial_gfx_cs_size = rctx->b.rings.gfx.cs->cdw;
  98 }
  99
 100 static void r600_flush_from_st(struct pipe_context *ctx,
 101                                struct pipe_fence_handle **fence,
 102                                unsigned flags)
 103 {
 104         struct r600_context *rctx = (struct r600_context *)ctx;
 105         unsigned fflags;
 106
 107         fflags = flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0;
 108         if (fence) {
 109                 *fence = rctx->b.ws->cs_create_fence(rctx->b.rings.gfx.cs);
 110         }
 111         /* flush gfx & dma ring, order does not matter as only one can be live */
 112         if (rctx->b.rings.dma.cs) {
 113                 rctx->b.rings.dma.flush(rctx, fflags);
 114         }
 115         rctx->b.rings.gfx.flush(rctx, fflags);
 116 }
 117
 118 static void r600_flush_gfx_ring(void *ctx, unsigned flags)
 119 {
 120         r600_flush((struct pipe_context*)ctx, flags);
 121 }
 122
 123 static void r600_flush_dma_ring(void *ctx, unsigned flags)
 124 {
 125         struct r600_context *rctx = (struct r600_context *)ctx;
 126         struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
 127
 128         if (!cs->cdw) {
 129                 return;
 130         }
 131
 132         rctx->b.rings.dma.flushing = true;
 133         rctx->b.ws->cs_flush(cs, flags, 0);
 134         rctx->b.rings.dma.flushing = false;
 135 }
 136
 137 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 138 {
 139         struct r600_context *rctx = (struct r600_context *)ctx;
 140
 141         rctx->b.rings.gfx.flush(rctx, flags);
 142 }
 143
 144 static void r600_flush_dma_from_winsys(void *ctx, unsigned flags)
 145 {
 146         struct r600_context *rctx = (struct r600_context *)ctx;
 147
 148         rctx->b.rings.dma.flush(rctx, flags);
 149 }
 150
 151 static void r600_destroy_context(struct pipe_context *context)
 152 {
 153         struct r600_context *rctx = (struct r600_context *)context;
 154
 155         r600_isa_destroy(rctx->isa);
 156
 157         r600_sb_context_destroy(rctx->sb_context);
 158
 159         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
 160         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
 161
 162         if (rctx->dummy_pixel_shader) {
 163                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 164         }
 165         if (rctx->custom_dsa_flush) {
 166                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
 167         }
 168         if (rctx->custom_blend_resolve) {
 169                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
 170         }
 171         if (rctx->custom_blend_decompress) {
 172                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
 173         }
 174         if (rctx->custom_blend_fastclear) {
 175                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
 176         }
 177         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 178
 179         if (rctx->blitter) {
 180                 util_blitter_destroy(rctx->blitter);
 181         }
 182         if (rctx->allocator_fetch_shader) {
 183                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 184         }
 185
 186         r600_release_command_buffer(&rctx->start_cs_cmd);
 187
 188         if (rctx->b.rings.gfx.cs) {
 189                 rctx->b.ws->cs_destroy(rctx->b.rings.gfx.cs);
 190         }
 191         if (rctx->b.rings.dma.cs) {
 192                 rctx->b.ws->cs_destroy(rctx->b.rings.dma.cs);
 193         }
 194
 195         r600_common_context_cleanup(&rctx->b);
 196         FREE(rctx);
 197 }
 198
 199 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 200 {
 201         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 202         struct r600_screen* rscreen = (struct r600_screen *)screen;
 203
 204         if (rctx == NULL)
 205                 return NULL;
 206
 207         rctx->b.b.screen = screen;
 208         rctx->b.b.priv = priv;
 209         rctx->b.b.destroy = r600_destroy_context;
 210         rctx->b.b.flush = r600_flush_from_st;
 211
 212         if (!r600_common_context_init(&rctx->b, &rscreen->b))
 213                 goto fail;
 214
 215         rctx->screen = rscreen;
 216         rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
 217
 218         LIST_INITHEAD(&rctx->active_nontimer_queries);
 219
 220         r600_init_blit_functions(rctx);
 221         r600_init_query_functions(rctx);
 222         r600_init_context_resource_functions(rctx);
 223
 224         if (rscreen->b.info.has_uvd) {
 225                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 226                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 227         } else {
 228                 rctx->b.b.create_video_codec = vl_create_decoder;
 229                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 230         }
 231
 232         r600_init_common_state_functions(rctx);
 233
 234         switch (rctx->b.chip_class) {
 235         case R600:
 236         case R700:
 237                 r600_init_state_functions(rctx);
 238                 r600_init_atom_start_cs(rctx);
 239                 rctx->max_db = 4;
 240                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 241                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 242                                                                       : r600_create_resolve_blend(rctx);
 243                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 244                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 245                                            rctx->b.family == CHIP_RV620 ||
 246                                            rctx->b.family == CHIP_RS780 ||
 247                                            rctx->b.family == CHIP_RS880 ||
 248                                            rctx->b.family == CHIP_RV710);
 249                 break;
 250         case EVERGREEN:
 251         case CAYMAN:
 252                 evergreen_init_state_functions(rctx);
 253                 evergreen_init_atom_start_cs(rctx);
 254                 evergreen_init_atom_start_compute_cs(rctx);
 255                 rctx->max_db = 8;
 256                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 257                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 258                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 259                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 260                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 261                                            rctx->b.family == CHIP_PALM ||
 262                                            rctx->b.family == CHIP_SUMO ||
 263                                            rctx->b.family == CHIP_SUMO2 ||
 264                                            rctx->b.family == CHIP_CAICOS ||
 265                                            rctx->b.family == CHIP_CAYMAN ||
 266                                            rctx->b.family == CHIP_ARUBA);
 267                 break;
 268         default:
 269                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 270                 goto fail;
 271         }
 272
 273         if (rscreen->trace_bo) {
 274                 rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, rscreen->trace_bo->cs_buf);
 275         } else {
 276                 rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, NULL);
 277         }
 278         rctx->b.rings.gfx.flush = r600_flush_gfx_ring;
 279         rctx->b.ws->cs_set_flush_callback(rctx->b.rings.gfx.cs, r600_flush_from_winsys, rctx);
 280         rctx->b.rings.gfx.flushing = false;
 281
 282         rctx->b.rings.dma.cs = NULL;
 283         if (rscreen->b.info.r600_has_dma && !(rscreen->b.debug_flags & DBG_NO_ASYNC_DMA)) {
 284                 rctx->b.rings.dma.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_DMA, NULL);
 285                 rctx->b.rings.dma.flush = r600_flush_dma_ring;
 286                 rctx->b.ws->cs_set_flush_callback(rctx->b.rings.dma.cs, r600_flush_dma_from_winsys, rctx);
 287                 rctx->b.rings.dma.flushing = false;
 288         }
 289
 290         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
 291                                                              0, PIPE_USAGE_STATIC, FALSE);
 292         if (!rctx->allocator_fetch_shader)
 293                 goto fail;
 294
 295         rctx->isa = calloc(1, sizeof(struct r600_isa));
 296         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 297                 goto fail;
 298
 299         rctx->blitter = util_blitter_create(&rctx->b.b);
 300         if (rctx->blitter == NULL)
 301                 goto fail;
 302         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 303         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 304
 305         r600_begin_new_cs(rctx);
 306         r600_get_backend_mask(rctx); /* this emits commands and must be last */
 307
 308         rctx->dummy_pixel_shader =
 309                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 310                                                      TGSI_SEMANTIC_GENERIC,
 311                                                      TGSI_INTERPOLATE_CONSTANT);
 312         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 313
 314         return &rctx->b.b;
 315
 316 fail:
 317         r600_destroy_context(&rctx->b.b);
 318         return NULL;
 319 }
 320
 321 /*
 322  * pipe_screen
 323  */
 324 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 325 {
 326         return "X.Org";
 327 }
 328
 329 static const char *r600_get_family_name(enum radeon_family family)
 330 {
 331         switch(family) {
 332         case CHIP_R600: return "AMD R600";
 333         case CHIP_RV610: return "AMD RV610";
 334         case CHIP_RV630: return "AMD RV630";
 335         case CHIP_RV670: return "AMD RV670";
 336         case CHIP_RV620: return "AMD RV620";
 337         case CHIP_RV635: return "AMD RV635";
 338         case CHIP_RS780: return "AMD RS780";
 339         case CHIP_RS880: return "AMD RS880";
 340         case CHIP_RV770: return "AMD RV770";
 341         case CHIP_RV730: return "AMD RV730";
 342         case CHIP_RV710: return "AMD RV710";
 343         case CHIP_RV740: return "AMD RV740";
 344         case CHIP_CEDAR: return "AMD CEDAR";
 345         case CHIP_REDWOOD: return "AMD REDWOOD";
 346         case CHIP_JUNIPER: return "AMD JUNIPER";
 347         case CHIP_CYPRESS: return "AMD CYPRESS";
 348         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 349         case CHIP_PALM: return "AMD PALM";
 350         case CHIP_SUMO: return "AMD SUMO";
 351         case CHIP_SUMO2: return "AMD SUMO2";
 352         case CHIP_BARTS: return "AMD BARTS";
 353         case CHIP_TURKS: return "AMD TURKS";
 354         case CHIP_CAICOS: return "AMD CAICOS";
 355         case CHIP_CAYMAN: return "AMD CAYMAN";
 356         case CHIP_ARUBA: return "AMD ARUBA";
 357         default: return "AMD unknown";
 358         }
 359 }
 360
 361 static const char* r600_get_name(struct pipe_screen* pscreen)
 362 {
 363         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 364
 365         return r600_get_family_name(rscreen->b.family);
 366 }
 367
 368 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 369 {
 370         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 371         enum radeon_family family = rscreen->b.family;
 372
 373         switch (param) {
 374         /* Supported features (boolean caps). */
 375         case PIPE_CAP_NPOT_TEXTURES:
 376         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 377         case PIPE_CAP_TWO_SIDED_STENCIL:
 378         case PIPE_CAP_ANISOTROPIC_FILTER:
 379         case PIPE_CAP_POINT_SPRITE:
 380         case PIPE_CAP_OCCLUSION_QUERY:
 381         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 382         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 383         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 384         case PIPE_CAP_TEXTURE_SWIZZLE:
 385         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 386         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 387         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 388         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 389         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 390         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 391         case PIPE_CAP_SM3:
 392         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 393         case PIPE_CAP_PRIMITIVE_RESTART:
 394         case PIPE_CAP_CONDITIONAL_RENDER:
 395         case PIPE_CAP_TEXTURE_BARRIER:
 396         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 397         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 398         case PIPE_CAP_TGSI_INSTANCEID:
 399         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 400         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 401         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 402         case PIPE_CAP_USER_INDEX_BUFFERS:
 403         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 404         case PIPE_CAP_COMPUTE:
 405         case PIPE_CAP_START_INSTANCE:
 406         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 407         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 408         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 409         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 410         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 411                 return 1;
 412
 413         case PIPE_CAP_TGSI_TEXCOORD:
 414                 return 0;
 415
 416         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 417                 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
 418
 419         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 420                 return R600_MAP_BUFFER_ALIGNMENT;
 421
 422         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 423                 return 256;
 424
 425         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 426                 return 1;
 427
 428         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 429                 return 140;
 430
 431         /* Supported except the original R600. */
 432         case PIPE_CAP_INDEP_BLEND_ENABLE:
 433         case PIPE_CAP_INDEP_BLEND_FUNC:
 434                 /* R600 doesn't support per-MRT blends */
 435                 return family == CHIP_R600 ? 0 : 1;
 436
 437         /* Supported on Evergreen. */
 438         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 439         case PIPE_CAP_CUBE_MAP_ARRAY:
 440                 return family >= CHIP_CEDAR ? 1 : 0;
 441
 442         /* Unsupported features. */
 443         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 444         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 445         case PIPE_CAP_SCALED_RESOLVE:
 446         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 447         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 448         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 449         case PIPE_CAP_USER_VERTEX_BUFFERS:
 450         case PIPE_CAP_TGSI_VS_LAYER:
 451                 return 0;
 452
 453         /* Stream output. */
 454         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 455                 return rscreen->b.has_streamout ? 4 : 0;
 456         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 457                 return rscreen->b.has_streamout ? 1 : 0;
 458         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 459         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 460                 return 32*4;
 461
 462         /* Texturing. */
 463         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 464         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 465         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 466                 if (family >= CHIP_CEDAR)
 467                         return 15;
 468                 else
 469                         return 14;
 470         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 471                 return rscreen->b.info.drm_minor >= 9 ?
 472                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 473         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 474                 return 32;
 475
 476         /* Render targets. */
 477         case PIPE_CAP_MAX_RENDER_TARGETS:
 478                 /* XXX some r6xx are buggy and can only do 4 */
 479                 return 8;
 480
 481         case PIPE_CAP_MAX_VIEWPORTS:
 482                 return 1;
 483
 484         /* Timer queries, present when the clock frequency is non zero. */
 485         case PIPE_CAP_QUERY_TIME_ELAPSED:
 486                 return rscreen->b.info.r600_clock_crystal_freq != 0;
 487         case PIPE_CAP_QUERY_TIMESTAMP:
 488                 return rscreen->b.info.drm_minor >= 20 &&
 489                        rscreen->b.info.r600_clock_crystal_freq != 0;
 490
 491         case PIPE_CAP_MIN_TEXEL_OFFSET:
 492                 return -8;
 493
 494         case PIPE_CAP_MAX_TEXEL_OFFSET:
 495                 return 7;
 496
 497         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 498                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 499         case PIPE_CAP_ENDIANNESS:
 500                 return PIPE_ENDIAN_LITTLE;
 501         }
 502         return 0;
 503 }
 504
 505 static float r600_get_paramf(struct pipe_screen* pscreen,
 506                              enum pipe_capf param)
 507 {
 508         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 509         enum radeon_family family = rscreen->b.family;
 510
 511         switch (param) {
 512         case PIPE_CAPF_MAX_LINE_WIDTH:
 513         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 514         case PIPE_CAPF_MAX_POINT_WIDTH:
 515         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 516                 if (family >= CHIP_CEDAR)
 517                         return 16384.0f;
 518                 else
 519                         return 8192.0f;
 520         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 521                 return 16.0f;
 522         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 523                 return 16.0f;
 524         case PIPE_CAPF_GUARD_BAND_LEFT:
 525         case PIPE_CAPF_GUARD_BAND_TOP:
 526         case PIPE_CAPF_GUARD_BAND_RIGHT:
 527         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 528                 return 0.0f;
 529         }
 530         return 0.0f;
 531 }
 532
 533 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 534 {
 535         switch(shader)
 536         {
 537         case PIPE_SHADER_FRAGMENT:
 538         case PIPE_SHADER_VERTEX:
 539         case PIPE_SHADER_COMPUTE:
 540                 break;
 541         case PIPE_SHADER_GEOMETRY:
 542                 /* XXX: support and enable geometry programs */
 543                 return 0;
 544         default:
 545                 /* XXX: support tessellation on Evergreen */
 546                 return 0;
 547         }
 548
 549         switch (param) {
 550         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 551         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 552         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 553         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 554                 return 16384;
 555         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 556                 return 32;
 557         case PIPE_SHADER_CAP_MAX_INPUTS:
 558                 return 32;
 559         case PIPE_SHADER_CAP_MAX_TEMPS:
 560                 return 256; /* Max native temporaries. */
 561         case PIPE_SHADER_CAP_MAX_ADDRS:
 562                 /* XXX Isn't this equal to TEMPS? */
 563                 return 1; /* Max native address registers */
 564         case PIPE_SHADER_CAP_MAX_CONSTS:
 565                 return R600_MAX_CONST_BUFFER_SIZE;
 566         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 567                 return R600_MAX_USER_CONST_BUFFERS;
 568         case PIPE_SHADER_CAP_MAX_PREDS:
 569                 return 0; /* nothing uses this */
 570         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 571                 return 1;
 572         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 573                 return 0;
 574         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 575         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 576         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 577         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 578                 return 1;
 579         case PIPE_SHADER_CAP_SUBROUTINES:
 580                 return 0;
 581         case PIPE_SHADER_CAP_INTEGERS:
 582                 return 1;
 583         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 584         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 585                 return 16;
 586         case PIPE_SHADER_CAP_PREFERRED_IR:
 587                 if (shader == PIPE_SHADER_COMPUTE) {
 588                         return PIPE_SHADER_IR_LLVM;
 589                 } else {
 590                         return PIPE_SHADER_IR_TGSI;
 591                 }
 592         }
 593         return 0;
 594 }
 595
 596 static int r600_get_video_param(struct pipe_screen *screen,
 597                                 enum pipe_video_profile profile,
 598                                 enum pipe_video_entrypoint entrypoint,
 599                                 enum pipe_video_cap param)
 600 {
 601         switch (param) {
 602         case PIPE_VIDEO_CAP_SUPPORTED:
 603                 return vl_profile_supported(screen, profile, entrypoint);
 604         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 605                 return 1;
 606         case PIPE_VIDEO_CAP_MAX_WIDTH:
 607         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 608                 return vl_video_buffer_max_size(screen);
 609         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 610                 return PIPE_FORMAT_NV12;
 611         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 612                 return false;
 613         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 614                 return false;
 615         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 616                 return true;
 617         case PIPE_VIDEO_CAP_MAX_LEVEL:
 618                 return vl_level_supported(screen, profile);
 619         default:
 620                 return 0;
 621         }
 622 }
 623
 624 const char * r600_llvm_gpu_string(enum radeon_family family)
 625 {
 626         const char * gpu_family;
 627
 628         switch (family) {
 629         case CHIP_R600:
 630         case CHIP_RV630:
 631         case CHIP_RV635:
 632         case CHIP_RV670:
 633                 gpu_family = "r600";
 634                 break;
 635         case CHIP_RV610:
 636         case CHIP_RV620:
 637         case CHIP_RS780:
 638         case CHIP_RS880:
 639                 gpu_family = "rs880";
 640                 break;
 641         case CHIP_RV710:
 642                 gpu_family = "rv710";
 643                 break;
 644         case CHIP_RV730:
 645                 gpu_family = "rv730";
 646                 break;
 647         case CHIP_RV740:
 648         case CHIP_RV770:
 649                 gpu_family = "rv770";
 650                 break;
 651         case CHIP_PALM:
 652         case CHIP_CEDAR:
 653                 gpu_family = "cedar";
 654                 break;
 655         case CHIP_SUMO:
 656         case CHIP_SUMO2:
 657                 gpu_family = "sumo";
 658                 break;
 659         case CHIP_REDWOOD:
 660                 gpu_family = "redwood";
 661                 break;
 662         case CHIP_JUNIPER:
 663                 gpu_family = "juniper";
 664                 break;
 665         case CHIP_HEMLOCK:
 666         case CHIP_CYPRESS:
 667                 gpu_family = "cypress";
 668                 break;
 669         case CHIP_BARTS:
 670                 gpu_family = "barts";
 671                 break;
 672         case CHIP_TURKS:
 673                 gpu_family = "turks";
 674                 break;
 675         case CHIP_CAICOS:
 676                 gpu_family = "caicos";
 677                 break;
 678         case CHIP_CAYMAN:
 679         case CHIP_ARUBA:
 680                 gpu_family = "cayman";
 681                 break;
 682         default:
 683                 gpu_family = "";
 684                 fprintf(stderr, "Chip not supported by r600 llvm "
 685                         "backend, please file a bug at " PACKAGE_BUGREPORT "\n");
 686                 break;
 687         }
 688         return gpu_family;
 689 }
 690
 691
 692 static int r600_get_compute_param(struct pipe_screen *screen,
 693         enum pipe_compute_cap param,
 694         void *ret)
 695 {
 696         struct r600_screen *rscreen = (struct r600_screen *)screen;
 697         //TODO: select these params by asic
 698         switch (param) {
 699         case PIPE_COMPUTE_CAP_IR_TARGET: {
 700                 const char *gpu = r600_llvm_gpu_string(rscreen->b.family);
 701                 if (ret) {
 702                         sprintf(ret, "%s-r600--", gpu);
 703                 }
 704                 return (8 + strlen(gpu)) * sizeof(char);
 705         }
 706         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 707                 if (ret) {
 708                         uint64_t * grid_dimension = ret;
 709                         grid_dimension[0] = 3;
 710                 }
 711                 return 1 * sizeof(uint64_t);
 712
 713         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 714                 if (ret) {
 715                         uint64_t * grid_size = ret;
 716                         grid_size[0] = 65535;
 717                         grid_size[1] = 65535;
 718                         grid_size[2] = 1;
 719                 }
 720                 return 3 * sizeof(uint64_t) ;
 721
 722         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 723                 if (ret) {
 724                         uint64_t * block_size = ret;
 725                         block_size[0] = 256;
 726                         block_size[1] = 256;
 727                         block_size[2] = 256;
 728                 }
 729                 return 3 * sizeof(uint64_t);
 730
 731         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 732                 if (ret) {
 733                         uint64_t * max_threads_per_block = ret;
 734                         *max_threads_per_block = 256;
 735                 }
 736                 return sizeof(uint64_t);
 737
 738         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 739                 if (ret) {
 740                         uint64_t * max_global_size = ret;
 741                         /* XXX: This is what the proprietary driver reports, we
 742                          * may want to use a different value. */
 743                         *max_global_size = 201326592;
 744                 }
 745                 return sizeof(uint64_t);
 746
 747         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 748                 if (ret) {
 749                         uint64_t * max_input_size = ret;
 750                         *max_input_size = 1024;
 751                 }
 752                 return sizeof(uint64_t);
 753
 754         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 755                 if (ret) {
 756                         uint64_t * max_local_size = ret;
 757                         /* XXX: This is what the proprietary driver reports, we
 758                          * may want to use a different value. */
 759                         *max_local_size = 32768;
 760                 }
 761                 return sizeof(uint64_t);
 762
 763         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 764                 if (ret) {
 765                         uint64_t max_global_size;
 766                         uint64_t * max_mem_alloc_size = ret;
 767                         r600_get_compute_param(screen,
 768                                         PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
 769                                         &max_global_size);
 770                         /* OpenCL requres this value be at least
 771                          * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
 772                          * I'm really not sure what value to report here, but
 773                          * MAX_GLOBAL_SIZE / 4 seems resonable.
 774                          */
 775                         *max_mem_alloc_size = max_global_size / 4;
 776                 }
 777                 return sizeof(uint64_t);
 778
 779         default:
 780                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 781                 return 0;
 782         }
 783 }
 784
 785 static void r600_destroy_screen(struct pipe_screen* pscreen)
 786 {
 787         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 788
 789         if (rscreen == NULL)
 790                 return;
 791
 792         if (!radeon_winsys_unref(rscreen->b.ws))
 793                 return;
 794
 795         r600_common_screen_cleanup(&rscreen->b);
 796
 797         if (rscreen->global_pool) {
 798                 compute_memory_pool_delete(rscreen->global_pool);
 799         }
 800
 801         if (rscreen->trace_bo) {
 802                 rscreen->b.ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 803                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 804         }
 805
 806         rscreen->b.ws->destroy(rscreen->b.ws);
 807         FREE(rscreen);
 808 }
 809
 810 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 811 {
 812         struct r600_screen *rscreen = (struct r600_screen*)screen;
 813
 814         return 1000000 * rscreen->b.ws->query_value(rscreen->b.ws, RADEON_TIMESTAMP) /
 815                         rscreen->b.info.r600_clock_crystal_freq;
 816 }
 817
 818 static int r600_get_driver_query_info(struct pipe_screen *screen,
 819                                       unsigned index,
 820                                       struct pipe_driver_query_info *info)
 821 {
 822         struct r600_screen *rscreen = (struct r600_screen*)screen;
 823         struct pipe_driver_query_info list[] = {
 824                 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
 825                 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->b.info.vram_size, TRUE},
 826                 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->b.info.gart_size, TRUE},
 827                 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE}
 828         };
 829
 830         if (!info)
 831                 return Elements(list);
 832
 833         if (index >= Elements(list))
 834                 return 0;
 835
 836         *info = list[index];
 837         return 1;
 838 }
 839
 840 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 841 {
 842         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 843
 844         if (rscreen == NULL) {
 845                 return NULL;
 846         }
 847
 848         ws->query_info(ws, &rscreen->b.info);
 849
 850         /* Set functions first. */
 851         rscreen->b.b.context_create = r600_create_context;
 852         rscreen->b.b.destroy = r600_destroy_screen;
 853         rscreen->b.b.get_name = r600_get_name;
 854         rscreen->b.b.get_vendor = r600_get_vendor;
 855         rscreen->b.b.get_param = r600_get_param;
 856         rscreen->b.b.get_shader_param = r600_get_shader_param;
 857         rscreen->b.b.get_paramf = r600_get_paramf;
 858         rscreen->b.b.get_compute_param = r600_get_compute_param;
 859         rscreen->b.b.get_timestamp = r600_get_timestamp;
 860         if (rscreen->b.info.chip_class >= EVERGREEN) {
 861                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 862         } else {
 863                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 864         }
 865         rscreen->b.b.get_driver_query_info = r600_get_driver_query_info;
 866         if (rscreen->b.info.has_uvd) {
 867                 rscreen->b.b.get_video_param = ruvd_get_video_param;
 868                 rscreen->b.b.is_video_format_supported = ruvd_is_format_supported;
 869         } else {
 870                 rscreen->b.b.get_video_param = r600_get_video_param;
 871                 rscreen->b.b.is_video_format_supported = vl_video_buffer_is_format_supported;
 872         }
 873         r600_init_screen_resource_functions(&rscreen->b.b);
 874
 875         if (!r600_common_screen_init(&rscreen->b, ws)) {
 876                 FREE(rscreen);
 877                 return NULL;
 878         }
 879
 880         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 881         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 882                 rscreen->b.debug_flags |= DBG_COMPUTE;
 883         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 884                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 885         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
 886                 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
 887         if (!debug_get_bool_option("R600_LLVM", TRUE))
 888                 rscreen->b.debug_flags |= DBG_NO_LLVM;
 889
 890         if (rscreen->b.family == CHIP_UNKNOWN) {
 891                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 892                 FREE(rscreen);
 893                 return NULL;
 894         }
 895
 896         /* Figure out streamout kernel support. */
 897         switch (rscreen->b.chip_class) {
 898         case R600:
 899                 if (rscreen->b.family < CHIP_RS780) {
 900                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 901                 } else {
 902                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 903                 }
 904                 break;
 905         case R700:
 906                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 907                 break;
 908         case EVERGREEN:
 909         case CAYMAN:
 910                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 911                 break;
 912         default:
 913                 rscreen->b.has_streamout = FALSE;
 914                 break;
 915         }
 916
 917         /* MSAA support. */
 918         switch (rscreen->b.chip_class) {
 919         case R600:
 920         case R700:
 921                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 922                 rscreen->has_compressed_msaa_texturing = false;
 923                 break;
 924         case EVERGREEN:
 925                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 926                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 927                 break;
 928         case CAYMAN:
 929                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 930                 rscreen->has_compressed_msaa_texturing = true;
 931                 break;
 932         default:
 933                 rscreen->has_msaa = FALSE;
 934                 rscreen->has_compressed_msaa_texturing = false;
 935         }
 936
 937         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 938                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 939
 940         rscreen->global_pool = compute_memory_pool_new(rscreen);
 941
 942         rscreen->cs_count = 0;
 943         if (rscreen->b.info.drm_minor >= 28 && (rscreen->b.debug_flags & DBG_TRACE_CS)) {
 944                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b.b,
 945                                                                                 PIPE_BIND_CUSTOM,
 946                                                                                 PIPE_USAGE_STAGING,
 947                                                                                 4096);
 948                 if (rscreen->trace_bo) {
 949                         rscreen->trace_ptr = rscreen->b.ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 950                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 951                 }
 952         }
 953
 954         /* Create the auxiliary context. This must be done last. */
 955         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
 956
 957 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 958         struct pipe_resource templ = {};
 959
 960         templ.width0 = 4;
 961         templ.height0 = 2048;
 962         templ.depth0 = 1;
 963         templ.array_size = 1;
 964         templ.target = PIPE_TEXTURE_2D;
 965         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 966         templ.usage = PIPE_USAGE_STATIC;
 967
 968         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 969         unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
 970
 971         memset(map, 0, 256);
 972
 973         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 974         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 975         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 976         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 977         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 978
 979         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 980
 981         int i;
 982         for (i = 0; i < 256; i++) {
 983                 printf("%02X", map[i]);
 984                 if (i % 16 == 15)
 985                         printf("\n");
 986         }
 987 #endif
 988
 989         return &rscreen->b.b;
 990 }