src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25
  26 #include <errno.h>
  27 #include "pipe/p_shader_tokens.h"
  28 #include "util/u_blitter.h"
  29 #include "util/u_format_s3tc.h"
  30 #include "util/u_simple_shaders.h"
  31 #include "vl/vl_decoder.h"
  32 #include "vl/vl_video_buffer.h"
  33 #include "os/os_time.h"
  34
  35 /*
  36  * pipe_context
  37  */
  38 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  39 {
  40         struct r600_screen *rscreen = rctx->screen;
  41         struct r600_fence *fence = NULL;
  42
  43         pipe_mutex_lock(rscreen->fences.mutex);
  44
  45         if (!rscreen->fences.bo) {
  46                 /* Create the shared buffer object */
  47                 rscreen->fences.bo = (struct r600_resource*)
  48                         pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
  49                                            PIPE_USAGE_STAGING, 4096);
  50                 if (!rscreen->fences.bo) {
  51                         R600_ERR("r600: failed to create bo for fence objects\n");
  52                         goto out;
  53                 }
  54                 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->buf,
  55                                                            rctx->cs,
  56                                                            PIPE_TRANSFER_READ_WRITE);
  57         }
  58
  59         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  60                 struct r600_fence *entry;
  61
  62                 /* Try to find a freed fence that has been signalled */
  63                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  64                         if (rscreen->fences.data[entry->index] != 0) {
  65                                 LIST_DELINIT(&entry->head);
  66                                 fence = entry;
  67                                 break;
  68                         }
  69                 }
  70         }
  71
  72         if (!fence) {
  73                 /* Allocate a new fence */
  74                 struct r600_fence_block *block;
  75                 unsigned index;
  76
  77                 if ((rscreen->fences.next_index + 1) >= 1024) {
  78                         R600_ERR("r600: too many concurrent fences\n");
  79                         goto out;
  80                 }
  81
  82                 index = rscreen->fences.next_index++;
  83
  84                 if (!(index % FENCE_BLOCK_SIZE)) {
  85                         /* Allocate a new block */
  86                         block = CALLOC_STRUCT(r600_fence_block);
  87                         if (block == NULL)
  88                                 goto out;
  89
  90                         LIST_ADD(&block->head, &rscreen->fences.blocks);
  91                 } else {
  92                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
  93                 }
  94
  95                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
  96                 fence->index = index;
  97         }
  98
  99         pipe_reference_init(&fence->reference, 1);
 100
 101         rscreen->fences.data[fence->index] = 0;
 102         r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 103
 104         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 105         fence->sleep_bo = (struct r600_resource*)
 106                         pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
 107                                            PIPE_USAGE_STAGING, 1);
 108         /* Add the fence as a dummy relocation. */
 109         r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 110
 111 out:
 112         pipe_mutex_unlock(rscreen->fences.mutex);
 113         return fence;
 114 }
 115
 116
 117 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 118                 unsigned flags)
 119 {
 120         struct r600_context *rctx = (struct r600_context *)ctx;
 121         struct r600_fence **rfence = (struct r600_fence**)fence;
 122         struct pipe_query *render_cond = NULL;
 123         unsigned render_cond_mode = 0;
 124
 125         if (rfence)
 126                 *rfence = r600_create_fence(rctx);
 127
 128         /* Disable render condition. */
 129         if (rctx->current_render_cond) {
 130                 render_cond = rctx->current_render_cond;
 131                 render_cond_mode = rctx->current_render_cond_mode;
 132                 ctx->render_condition(ctx, NULL, 0);
 133         }
 134
 135         r600_context_flush(rctx, flags);
 136
 137         /* Re-enable render condition. */
 138         if (render_cond) {
 139                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 140         }
 141 }
 142
 143 static void r600_flush_from_st(struct pipe_context *ctx,
 144                                struct pipe_fence_handle **fence)
 145 {
 146         r600_flush(ctx, fence, 0);
 147 }
 148
 149 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 150 {
 151         r600_flush((struct pipe_context*)ctx, NULL, flags);
 152 }
 153
 154 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
 155 {
 156         pipe_mutex_lock(rscreen->mutex_num_contexts);
 157         if (diff > 0) {
 158                 rscreen->num_contexts++;
 159
 160                 if (rscreen->num_contexts > 1)
 161                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 162                                                     UTIL_SLAB_MULTITHREADED);
 163         } else {
 164                 rscreen->num_contexts--;
 165
 166                 if (rscreen->num_contexts <= 1)
 167                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 168                                                     UTIL_SLAB_SINGLETHREADED);
 169         }
 170         pipe_mutex_unlock(rscreen->mutex_num_contexts);
 171 }
 172
 173 static void r600_destroy_context(struct pipe_context *context)
 174 {
 175         struct r600_context *rctx = (struct r600_context *)context;
 176
 177         if (rctx->dummy_pixel_shader) {
 178                 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 179         }
 180         if (rctx->custom_dsa_flush) {
 181                 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 182         }
 183         util_unreference_framebuffer_state(&rctx->framebuffer);
 184
 185         r600_context_fini(rctx);
 186
 187         if (rctx->blitter) {
 188                 util_blitter_destroy(rctx->blitter);
 189         }
 190         for (int i = 0; i < R600_PIPE_NSTATES; i++) {
 191                 free(rctx->states[i]);
 192         }
 193
 194         if (rctx->vbuf_mgr) {
 195                 u_vbuf_destroy(rctx->vbuf_mgr);
 196         }
 197         util_slab_destroy(&rctx->pool_transfers);
 198
 199         r600_update_num_contexts(rctx->screen, -1);
 200
 201         r600_release_command_buffer(&rctx->atom_start_cs);
 202
 203         if (rctx->cs) {
 204                 rctx->ws->cs_destroy(rctx->cs);
 205         }
 206
 207         FREE(rctx->range);
 208         FREE(rctx);
 209 }
 210
 211 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 212 {
 213         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 214         struct r600_screen* rscreen = (struct r600_screen *)screen;
 215
 216         if (rctx == NULL)
 217                 return NULL;
 218
 219         util_slab_create(&rctx->pool_transfers,
 220                          sizeof(struct pipe_transfer), 64,
 221                          UTIL_SLAB_SINGLETHREADED);
 222
 223         r600_update_num_contexts(rscreen, 1);
 224
 225         rctx->context.screen = screen;
 226         rctx->context.priv = priv;
 227         rctx->context.destroy = r600_destroy_context;
 228         rctx->context.flush = r600_flush_from_st;
 229
 230         /* Easy accessing of screen/winsys. */
 231         rctx->screen = rscreen;
 232         rctx->ws = rscreen->ws;
 233         rctx->family = rscreen->family;
 234         rctx->chip_class = rscreen->chip_class;
 235
 236         LIST_INITHEAD(&rctx->dirty_states);
 237         LIST_INITHEAD(&rctx->active_timer_queries);
 238         LIST_INITHEAD(&rctx->active_nontimer_queries);
 239         LIST_INITHEAD(&rctx->dirty);
 240         LIST_INITHEAD(&rctx->resource_dirty);
 241         LIST_INITHEAD(&rctx->enable_list);
 242
 243         rctx->range = CALLOC(NUM_RANGES, sizeof(struct r600_range));
 244         if (!rctx->range)
 245                 goto fail;
 246
 247         r600_init_blit_functions(rctx);
 248         r600_init_query_functions(rctx);
 249         r600_init_context_resource_functions(rctx);
 250         r600_init_surface_functions(rctx);
 251         rctx->context.draw_vbo = r600_draw_vbo;
 252
 253         rctx->context.create_video_decoder = vl_create_decoder;
 254         rctx->context.create_video_buffer = vl_video_buffer_create;
 255
 256         r600_init_common_atoms(rctx);
 257
 258         switch (rctx->chip_class) {
 259         case R600:
 260         case R700:
 261                 r600_init_state_functions(rctx);
 262                 r600_init_atom_start_cs(rctx);
 263                 if (r600_context_init(rctx))
 264                         goto fail;
 265                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 266                 break;
 267         case EVERGREEN:
 268         case CAYMAN:
 269                 evergreen_init_state_functions(rctx);
 270                 evergreen_init_atom_start_cs(rctx);
 271                 if (evergreen_context_init(rctx))
 272                         goto fail;
 273                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 274                 break;
 275         default:
 276                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 277                 goto fail;
 278         }
 279
 280         rctx->cs = rctx->ws->cs_create(rctx->ws);
 281         rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
 282         r600_emit_atom(rctx, &rctx->atom_start_cs.atom);
 283
 284         rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256,
 285                                            PIPE_BIND_VERTEX_BUFFER |
 286                                            PIPE_BIND_INDEX_BUFFER |
 287                                            PIPE_BIND_CONSTANT_BUFFER,
 288                                            U_VERTEX_FETCH_DWORD_ALIGNED);
 289         if (!rctx->vbuf_mgr)
 290                 goto fail;
 291         rctx->vbuf_mgr->caps.format_fixed32 = 0;
 292
 293         rctx->blitter = util_blitter_create(&rctx->context);
 294         if (rctx->blitter == NULL)
 295                 goto fail;
 296
 297         r600_get_backend_mask(rctx); /* this emits commands and must be last */
 298
 299         if (rctx->chip_class == R600)
 300                 r600_set_max_scissor(rctx);
 301
 302         rctx->dummy_pixel_shader =
 303                 util_make_fragment_cloneinput_shader(&rctx->context, 0,
 304                                                      TGSI_SEMANTIC_GENERIC,
 305                                                      TGSI_INTERPOLATE_CONSTANT);
 306         rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 307
 308         return &rctx->context;
 309
 310 fail:
 311         r600_destroy_context(&rctx->context);
 312         return NULL;
 313 }
 314
 315 /*
 316  * pipe_screen
 317  */
 318 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 319 {
 320         return "X.Org";
 321 }
 322
 323 static const char *r600_get_family_name(enum radeon_family family)
 324 {
 325         switch(family) {
 326         case CHIP_R600: return "AMD R600";
 327         case CHIP_RV610: return "AMD RV610";
 328         case CHIP_RV630: return "AMD RV630";
 329         case CHIP_RV670: return "AMD RV670";
 330         case CHIP_RV620: return "AMD RV620";
 331         case CHIP_RV635: return "AMD RV635";
 332         case CHIP_RS780: return "AMD RS780";
 333         case CHIP_RS880: return "AMD RS880";
 334         case CHIP_RV770: return "AMD RV770";
 335         case CHIP_RV730: return "AMD RV730";
 336         case CHIP_RV710: return "AMD RV710";
 337         case CHIP_RV740: return "AMD RV740";
 338         case CHIP_CEDAR: return "AMD CEDAR";
 339         case CHIP_REDWOOD: return "AMD REDWOOD";
 340         case CHIP_JUNIPER: return "AMD JUNIPER";
 341         case CHIP_CYPRESS: return "AMD CYPRESS";
 342         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 343         case CHIP_PALM: return "AMD PALM";
 344         case CHIP_SUMO: return "AMD SUMO";
 345         case CHIP_SUMO2: return "AMD SUMO2";
 346         case CHIP_BARTS: return "AMD BARTS";
 347         case CHIP_TURKS: return "AMD TURKS";
 348         case CHIP_CAICOS: return "AMD CAICOS";
 349         case CHIP_CAYMAN: return "AMD CAYMAN";
 350         default: return "AMD unknown";
 351         }
 352 }
 353
 354 static const char* r600_get_name(struct pipe_screen* pscreen)
 355 {
 356         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 357
 358         return r600_get_family_name(rscreen->family);
 359 }
 360
 361 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 362 {
 363         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 364         enum radeon_family family = rscreen->family;
 365
 366         switch (param) {
 367         /* Supported features (boolean caps). */
 368         case PIPE_CAP_NPOT_TEXTURES:
 369         case PIPE_CAP_TWO_SIDED_STENCIL:
 370         case PIPE_CAP_DUAL_SOURCE_BLEND:
 371         case PIPE_CAP_ANISOTROPIC_FILTER:
 372         case PIPE_CAP_POINT_SPRITE:
 373         case PIPE_CAP_OCCLUSION_QUERY:
 374         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 375         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 376         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 377         case PIPE_CAP_TEXTURE_SWIZZLE:
 378         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 379         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 380         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 381         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 382         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 383         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 384         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 385         case PIPE_CAP_SM3:
 386         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 387         case PIPE_CAP_PRIMITIVE_RESTART:
 388         case PIPE_CAP_CONDITIONAL_RENDER:
 389         case PIPE_CAP_TEXTURE_BARRIER:
 390         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 391         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 392                 return 1;
 393
 394         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 395                 return debug_get_bool_option("R600_GLSL130", FALSE) ? 130 : 120;
 396
 397         /* Supported except the original R600. */
 398         case PIPE_CAP_INDEP_BLEND_ENABLE:
 399         case PIPE_CAP_INDEP_BLEND_FUNC:
 400                 /* R600 doesn't support per-MRT blends */
 401                 return family == CHIP_R600 ? 0 : 1;
 402
 403         /* Supported on Evergreen. */
 404         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 405                 return family >= CHIP_CEDAR ? 1 : 0;
 406
 407         /* Unsupported features. */
 408         case PIPE_CAP_TGSI_INSTANCEID:
 409         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 410         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 411         case PIPE_CAP_SCALED_RESOLVE:
 412         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 413         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 414         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 415         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 416                 return 0;
 417
 418         /* Stream output. */
 419         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 420                 return rscreen->info.r600_has_streamout ? 4 : 0;
 421         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 422                 return rscreen->info.r600_has_streamout ? 1 : 0;
 423         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 424         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 425                 return 16*4;
 426
 427         /* Texturing. */
 428         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 429         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 430         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 431                 if (family >= CHIP_CEDAR)
 432                         return 15;
 433                 else
 434                         return 14;
 435         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 436                 return rscreen->info.drm_minor >= 9 ?
 437                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 438         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 439                 return 32;
 440
 441         /* Render targets. */
 442         case PIPE_CAP_MAX_RENDER_TARGETS:
 443                 /* XXX some r6xx are buggy and can only do 4 */
 444                 return 8;
 445
 446         /* Timer queries, present when the clock frequency is non zero. */
 447         case PIPE_CAP_TIMER_QUERY:
 448                 return rscreen->info.r600_clock_crystal_freq != 0;
 449
 450         case PIPE_CAP_MIN_TEXEL_OFFSET:
 451                 return -8;
 452
 453         case PIPE_CAP_MAX_TEXEL_OFFSET:
 454                 return 7;
 455         }
 456         return 0;
 457 }
 458
 459 static float r600_get_paramf(struct pipe_screen* pscreen,
 460                              enum pipe_capf param)
 461 {
 462         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 463         enum radeon_family family = rscreen->family;
 464
 465         switch (param) {
 466         case PIPE_CAPF_MAX_LINE_WIDTH:
 467         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 468         case PIPE_CAPF_MAX_POINT_WIDTH:
 469         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 470                 if (family >= CHIP_CEDAR)
 471                         return 16384.0f;
 472                 else
 473                         return 8192.0f;
 474         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 475                 return 16.0f;
 476         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 477                 return 16.0f;
 478         case PIPE_CAPF_GUARD_BAND_LEFT:
 479         case PIPE_CAPF_GUARD_BAND_TOP:
 480         case PIPE_CAPF_GUARD_BAND_RIGHT:
 481         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 482                 return 0.0f;
 483         }
 484         return 0.0f;
 485 }
 486
 487 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 488 {
 489         switch(shader)
 490         {
 491         case PIPE_SHADER_FRAGMENT:
 492         case PIPE_SHADER_VERTEX:
 493                 break;
 494         case PIPE_SHADER_GEOMETRY:
 495                 /* XXX: support and enable geometry programs */
 496                 return 0;
 497         default:
 498                 /* XXX: support tessellation on Evergreen */
 499                 return 0;
 500         }
 501
 502         /* XXX: all these should be fixed, since r600 surely supports much more! */
 503         switch (param) {
 504         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 505         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 506         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 507         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 508                 return 16384;
 509         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 510                 return 8; /* XXX */
 511         case PIPE_SHADER_CAP_MAX_INPUTS:
 512                 if(shader == PIPE_SHADER_FRAGMENT)
 513                         return 34;
 514                 else
 515                         return 32;
 516         case PIPE_SHADER_CAP_MAX_TEMPS:
 517                 return 256; /* Max native temporaries. */
 518         case PIPE_SHADER_CAP_MAX_ADDRS:
 519                 /* XXX Isn't this equal to TEMPS? */
 520                 return 1; /* Max native address registers */
 521         case PIPE_SHADER_CAP_MAX_CONSTS:
 522                 return R600_MAX_CONST_BUFFER_SIZE;
 523         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 524                 return R600_MAX_CONST_BUFFERS-1;
 525         case PIPE_SHADER_CAP_MAX_PREDS:
 526                 return 0; /* nothing uses this */
 527         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 528                 return 1;
 529         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 530         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 531         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 532         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 533                 return 1;
 534         case PIPE_SHADER_CAP_SUBROUTINES:
 535                 return 0;
 536         case PIPE_SHADER_CAP_INTEGERS:
 537                 return 0;
 538         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 539                 return 16;
 540         }
 541         return 0;
 542 }
 543
 544 static int r600_get_video_param(struct pipe_screen *screen,
 545                                 enum pipe_video_profile profile,
 546                                 enum pipe_video_cap param)
 547 {
 548         switch (param) {
 549         case PIPE_VIDEO_CAP_SUPPORTED:
 550                 return vl_profile_supported(screen, profile);
 551         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 552                 return 1;
 553         case PIPE_VIDEO_CAP_MAX_WIDTH:
 554         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 555                 return vl_video_buffer_max_size(screen);
 556         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 557                 return PIPE_FORMAT_NV12;
 558         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 559                 return false;
 560         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 561                 return false;
 562         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 563                 return true;
 564         default:
 565                 return 0;
 566         }
 567 }
 568
 569 static void r600_destroy_screen(struct pipe_screen* pscreen)
 570 {
 571         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 572
 573         if (rscreen == NULL)
 574                 return;
 575
 576         if (rscreen->fences.bo) {
 577                 struct r600_fence_block *entry, *tmp;
 578
 579                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 580                         LIST_DEL(&entry->head);
 581                         FREE(entry);
 582                 }
 583
 584                 rscreen->ws->buffer_unmap(rscreen->fences.bo->buf);
 585                 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
 586         }
 587         pipe_mutex_destroy(rscreen->fences.mutex);
 588
 589         rscreen->ws->destroy(rscreen->ws);
 590
 591         util_slab_destroy(&rscreen->pool_buffers);
 592         pipe_mutex_destroy(rscreen->mutex_num_contexts);
 593         FREE(rscreen);
 594 }
 595
 596 static void r600_fence_reference(struct pipe_screen *pscreen,
 597                                  struct pipe_fence_handle **ptr,
 598                                  struct pipe_fence_handle *fence)
 599 {
 600         struct r600_fence **oldf = (struct r600_fence**)ptr;
 601         struct r600_fence *newf = (struct r600_fence*)fence;
 602
 603         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 604                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 605                 pipe_mutex_lock(rscreen->fences.mutex);
 606                 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
 607                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 608                 pipe_mutex_unlock(rscreen->fences.mutex);
 609         }
 610
 611         *ptr = fence;
 612 }
 613
 614 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 615                                     struct pipe_fence_handle *fence)
 616 {
 617         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 618         struct r600_fence *rfence = (struct r600_fence*)fence;
 619
 620         return rscreen->fences.data[rfence->index];
 621 }
 622
 623 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 624                                  struct pipe_fence_handle *fence,
 625                                  uint64_t timeout)
 626 {
 627         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 628         struct r600_fence *rfence = (struct r600_fence*)fence;
 629         int64_t start_time = 0;
 630         unsigned spins = 0;
 631
 632         if (timeout != PIPE_TIMEOUT_INFINITE) {
 633                 start_time = os_time_get();
 634
 635                 /* Convert to microseconds. */
 636                 timeout /= 1000;
 637         }
 638
 639         while (rscreen->fences.data[rfence->index] == 0) {
 640                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
 641                 if (timeout == PIPE_TIMEOUT_INFINITE) {
 642                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
 643                         break;
 644                 }
 645
 646                 /* The dummy BO will be busy until the CS including the fence has completed, or
 647                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
 648                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
 649                         break;
 650
 651                 if (++spins % 256)
 652                         continue;
 653 #ifdef PIPE_OS_UNIX
 654                 sched_yield();
 655 #else
 656                 os_time_sleep(10);
 657 #endif
 658                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 659                     os_time_get() - start_time >= timeout) {
 660                         break;
 661                 }
 662         }
 663
 664         return rscreen->fences.data[rfence->index] != 0;
 665 }
 666
 667 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 668 {
 669         switch ((tiling_config & 0xe) >> 1) {
 670         case 0:
 671                 rscreen->tiling_info.num_channels = 1;
 672                 break;
 673         case 1:
 674                 rscreen->tiling_info.num_channels = 2;
 675                 break;
 676         case 2:
 677                 rscreen->tiling_info.num_channels = 4;
 678                 break;
 679         case 3:
 680                 rscreen->tiling_info.num_channels = 8;
 681                 break;
 682         default:
 683                 return -EINVAL;
 684         }
 685
 686         switch ((tiling_config & 0x30) >> 4) {
 687         case 0:
 688                 rscreen->tiling_info.num_banks = 4;
 689                 break;
 690         case 1:
 691                 rscreen->tiling_info.num_banks = 8;
 692                 break;
 693         default:
 694                 return -EINVAL;
 695
 696         }
 697         switch ((tiling_config & 0xc0) >> 6) {
 698         case 0:
 699                 rscreen->tiling_info.group_bytes = 256;
 700                 break;
 701         case 1:
 702                 rscreen->tiling_info.group_bytes = 512;
 703                 break;
 704         default:
 705                 return -EINVAL;
 706         }
 707         return 0;
 708 }
 709
 710 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 711 {
 712         switch (tiling_config & 0xf) {
 713         case 0:
 714                 rscreen->tiling_info.num_channels = 1;
 715                 break;
 716         case 1:
 717                 rscreen->tiling_info.num_channels = 2;
 718                 break;
 719         case 2:
 720                 rscreen->tiling_info.num_channels = 4;
 721                 break;
 722         case 3:
 723                 rscreen->tiling_info.num_channels = 8;
 724                 break;
 725         default:
 726                 return -EINVAL;
 727         }
 728
 729         switch ((tiling_config & 0xf0) >> 4) {
 730         case 0:
 731                 rscreen->tiling_info.num_banks = 4;
 732                 break;
 733         case 1:
 734                 rscreen->tiling_info.num_banks = 8;
 735                 break;
 736         case 2:
 737                 rscreen->tiling_info.num_banks = 16;
 738                 break;
 739         default:
 740                 return -EINVAL;
 741         }
 742
 743         switch ((tiling_config & 0xf00) >> 8) {
 744         case 0:
 745                 rscreen->tiling_info.group_bytes = 256;
 746                 break;
 747         case 1:
 748                 rscreen->tiling_info.group_bytes = 512;
 749                 break;
 750         default:
 751                 return -EINVAL;
 752         }
 753         return 0;
 754 }
 755
 756 static int r600_init_tiling(struct r600_screen *rscreen)
 757 {
 758         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 759
 760         /* set default group bytes, overridden by tiling info ioctl */
 761         if (rscreen->chip_class <= R700) {
 762                 rscreen->tiling_info.group_bytes = 256;
 763         } else {
 764                 rscreen->tiling_info.group_bytes = 512;
 765         }
 766
 767         if (!tiling_config)
 768                 return 0;
 769
 770         if (rscreen->chip_class <= R700) {
 771                 return r600_interpret_tiling(rscreen, tiling_config);
 772         } else {
 773                 return evergreen_interpret_tiling(rscreen, tiling_config);
 774         }
 775 }
 776
 777 static unsigned radeon_family_from_device(unsigned device)
 778 {
 779         switch (device) {
 780 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 781 #include "pci_ids/r600_pci_ids.h"
 782 #undef CHIPSET
 783         default:
 784                 return CHIP_UNKNOWN;
 785         }
 786 }
 787
 788 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 789 {
 790         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 791         if (rscreen == NULL) {
 792                 return NULL;
 793         }
 794
 795         rscreen->ws = ws;
 796         ws->query_info(ws, &rscreen->info);
 797
 798         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 799         if (rscreen->family == CHIP_UNKNOWN) {
 800                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 801                 FREE(rscreen);
 802                 return NULL;
 803         }
 804
 805         /* setup class */
 806         if (rscreen->family == CHIP_CAYMAN) {
 807                 rscreen->chip_class = CAYMAN;
 808         } else if (rscreen->family >= CHIP_CEDAR) {
 809                 rscreen->chip_class = EVERGREEN;
 810         } else if (rscreen->family >= CHIP_RV770) {
 811                 rscreen->chip_class = R700;
 812         } else {
 813                 rscreen->chip_class = R600;
 814         }
 815
 816         if (r600_init_tiling(rscreen)) {
 817                 FREE(rscreen);
 818                 return NULL;
 819         }
 820
 821         rscreen->screen.destroy = r600_destroy_screen;
 822         rscreen->screen.get_name = r600_get_name;
 823         rscreen->screen.get_vendor = r600_get_vendor;
 824         rscreen->screen.get_param = r600_get_param;
 825         rscreen->screen.get_shader_param = r600_get_shader_param;
 826         rscreen->screen.get_paramf = r600_get_paramf;
 827         rscreen->screen.get_video_param = r600_get_video_param;
 828         if (rscreen->chip_class >= EVERGREEN) {
 829                 rscreen->screen.is_format_supported = evergreen_is_format_supported;
 830         } else {
 831                 rscreen->screen.is_format_supported = r600_is_format_supported;
 832         }
 833         rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 834         rscreen->screen.context_create = r600_create_context;
 835         rscreen->screen.fence_reference = r600_fence_reference;
 836         rscreen->screen.fence_signalled = r600_fence_signalled;
 837         rscreen->screen.fence_finish = r600_fence_finish;
 838         r600_init_screen_resource_functions(&rscreen->screen);
 839
 840         util_format_s3tc_init();
 841
 842         util_slab_create(&rscreen->pool_buffers,
 843                          sizeof(struct r600_resource), 64,
 844                          UTIL_SLAB_SINGLETHREADED);
 845
 846         pipe_mutex_init(rscreen->mutex_num_contexts);
 847
 848         rscreen->fences.bo = NULL;
 849         rscreen->fences.data = NULL;
 850         rscreen->fences.next_index = 0;
 851         LIST_INITHEAD(&rscreen->fences.pool);
 852         LIST_INITHEAD(&rscreen->fences.blocks);
 853         pipe_mutex_init(rscreen->fences.mutex);
 854
 855         rscreen->use_surface_alloc = debug_get_bool_option("R600_SURF", TRUE);
 856
 857         return &rscreen->screen;
 858 }