r600g: Fix the PIPE_FORMAT_A8_UNORM color swap for Evergreen as well.
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include <pipe/p_defines.h>
26 #include <pipe/p_state.h>
27 #include <pipe/p_context.h>
28 #include <tgsi/tgsi_scan.h>
29 #include <tgsi/tgsi_parse.h>
30 #include <tgsi/tgsi_util.h>
31 #include <util/u_blitter.h>
32 #include <util/u_double_list.h>
33 #include <util/u_transfer.h>
34 #include <util/u_surface.h>
35 #include <util/u_pack_color.h>
36 #include <util/u_memory.h>
37 #include <util/u_inlines.h>
38 #include <util/u_upload_mgr.h>
39 #include <pipebuffer/pb_buffer.h>
40 #include "r600.h"
41 #include "r600d.h"
42 #include "r600_resource.h"
43 #include "r600_shader.h"
44 #include "r600_pipe.h"
45 #include "r600_state_inlines.h"
46
47 /*
48 * pipe_context
49 */
50 static void r600_flush(struct pipe_context *ctx, unsigned flags,
51 struct pipe_fence_handle **fence)
52 {
53 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
54 #if 0
55 static int dc = 0;
56 char dname[256];
57 #endif
58
59 if (!rctx->ctx.pm4_cdwords)
60 return;
61
62 u_upload_flush(rctx->upload_vb);
63 u_upload_flush(rctx->upload_ib);
64
65 #if 0
66 sprintf(dname, "gallium-%08d.bof", dc);
67 if (dc < 20) {
68 r600_context_dump_bof(&rctx->ctx, dname);
69 R600_ERR("dumped %s\n", dname);
70 }
71 dc++;
72 #endif
73 r600_context_flush(&rctx->ctx);
74 }
75
76 static void r600_destroy_context(struct pipe_context *context)
77 {
78 struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
79
80 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
81
82 r600_context_fini(&rctx->ctx);
83
84 util_blitter_destroy(rctx->blitter);
85
86 for (int i = 0; i < R600_PIPE_NSTATES; i++) {
87 free(rctx->states[i]);
88 }
89
90 u_upload_destroy(rctx->upload_vb);
91 u_upload_destroy(rctx->upload_ib);
92
93 if (rctx->tran.translate_cache)
94 translate_cache_destroy(rctx->tran.translate_cache);
95
96 FREE(rctx->ps_resource);
97 FREE(rctx->vs_resource);
98 FREE(rctx);
99 }
100
101 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
102 {
103 struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
104 struct r600_screen* rscreen = (struct r600_screen *)screen;
105 enum chip_class class;
106
107 if (rctx == NULL)
108 return NULL;
109 rctx->context.winsys = rscreen->screen.winsys;
110 rctx->context.screen = screen;
111 rctx->context.priv = priv;
112 rctx->context.destroy = r600_destroy_context;
113 rctx->context.flush = r600_flush;
114
115 /* Easy accessing of screen/winsys. */
116 rctx->screen = rscreen;
117 rctx->radeon = rscreen->radeon;
118 rctx->family = r600_get_family(rctx->radeon);
119
120 r600_init_blit_functions(rctx);
121 r600_init_query_functions(rctx);
122 r600_init_context_resource_functions(rctx);
123
124 switch (r600_get_family(rctx->radeon)) {
125 case CHIP_R600:
126 case CHIP_RV610:
127 case CHIP_RV630:
128 case CHIP_RV670:
129 case CHIP_RV620:
130 case CHIP_RV635:
131 case CHIP_RS780:
132 case CHIP_RS880:
133 case CHIP_RV770:
134 case CHIP_RV730:
135 case CHIP_RV710:
136 case CHIP_RV740:
137 rctx->context.draw_vbo = r600_draw_vbo;
138 r600_init_state_functions(rctx);
139 if (r600_context_init(&rctx->ctx, rctx->radeon)) {
140 r600_destroy_context(&rctx->context);
141 return NULL;
142 }
143 r600_init_config(rctx);
144 break;
145 case CHIP_CEDAR:
146 case CHIP_REDWOOD:
147 case CHIP_JUNIPER:
148 case CHIP_CYPRESS:
149 case CHIP_HEMLOCK:
150 case CHIP_PALM:
151 rctx->context.draw_vbo = evergreen_draw;
152 evergreen_init_state_functions(rctx);
153 if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
154 r600_destroy_context(&rctx->context);
155 return NULL;
156 }
157 evergreen_init_config(rctx);
158 break;
159 default:
160 R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
161 r600_destroy_context(&rctx->context);
162 return NULL;
163 }
164
165 rctx->upload_ib = u_upload_create(&rctx->context, 32 * 1024, 16,
166 PIPE_BIND_INDEX_BUFFER);
167 if (rctx->upload_ib == NULL) {
168 r600_destroy_context(&rctx->context);
169 return NULL;
170 }
171
172 rctx->upload_vb = u_upload_create(&rctx->context, 128 * 1024, 16,
173 PIPE_BIND_VERTEX_BUFFER);
174 if (rctx->upload_vb == NULL) {
175 r600_destroy_context(&rctx->context);
176 return NULL;
177 }
178
179 rctx->blitter = util_blitter_create(&rctx->context);
180 if (rctx->blitter == NULL) {
181 FREE(rctx);
182 return NULL;
183 }
184
185 rctx->tran.translate_cache = translate_cache_create();
186 if (rctx->tran.translate_cache == NULL) {
187 FREE(rctx);
188 return NULL;
189 }
190
191 rctx->vs_resource = CALLOC(R600_RESOURCE_ARRAY_SIZE, sizeof(struct r600_pipe_state));
192 if (!rctx->vs_resource) {
193 FREE(rctx);
194 return NULL;
195 }
196
197 rctx->ps_resource = CALLOC(R600_RESOURCE_ARRAY_SIZE, sizeof(struct r600_pipe_state));
198 if (!rctx->ps_resource) {
199 FREE(rctx);
200 return NULL;
201 }
202
203 class = r600_get_family_class(rctx->radeon);
204 if (class == R600 || class == R700)
205 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
206 else
207 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
208
209 r600_blit_uncompress_depth_ptr = r600_blit_uncompress_depth;
210
211 return &rctx->context;
212 }
213
214 /*
215 * pipe_screen
216 */
217 static const char* r600_get_vendor(struct pipe_screen* pscreen)
218 {
219 return "X.Org";
220 }
221
222 static const char *r600_get_family_name(enum radeon_family family)
223 {
224 switch(family) {
225 case CHIP_R600: return "AMD R600";
226 case CHIP_RV610: return "AMD RV610";
227 case CHIP_RV630: return "AMD RV630";
228 case CHIP_RV670: return "AMD RV670";
229 case CHIP_RV620: return "AMD RV620";
230 case CHIP_RV635: return "AMD RV635";
231 case CHIP_RS780: return "AMD RS780";
232 case CHIP_RS880: return "AMD RS880";
233 case CHIP_RV770: return "AMD RV770";
234 case CHIP_RV730: return "AMD RV730";
235 case CHIP_RV710: return "AMD RV710";
236 case CHIP_RV740: return "AMD RV740";
237 case CHIP_CEDAR: return "AMD CEDAR";
238 case CHIP_REDWOOD: return "AMD REDWOOD";
239 case CHIP_JUNIPER: return "AMD JUNIPER";
240 case CHIP_CYPRESS: return "AMD CYPRESS";
241 case CHIP_HEMLOCK: return "AMD HEMLOCK";
242 case CHIP_PALM: return "AMD PALM";
243 default: return "AMD unknown";
244 }
245 }
246
247 static const char* r600_get_name(struct pipe_screen* pscreen)
248 {
249 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
250 enum radeon_family family = r600_get_family(rscreen->radeon);
251
252 return r600_get_family_name(family);
253 }
254
255 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
256 {
257 switch (param) {
258 /* Supported features (boolean caps). */
259 case PIPE_CAP_NPOT_TEXTURES:
260 case PIPE_CAP_TWO_SIDED_STENCIL:
261 case PIPE_CAP_GLSL:
262 case PIPE_CAP_DUAL_SOURCE_BLEND:
263 case PIPE_CAP_ANISOTROPIC_FILTER:
264 case PIPE_CAP_POINT_SPRITE:
265 case PIPE_CAP_OCCLUSION_QUERY:
266 case PIPE_CAP_TEXTURE_SHADOW_MAP:
267 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
268 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
269 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
270 case PIPE_CAP_SM3:
271 case PIPE_CAP_TEXTURE_SWIZZLE:
272 case PIPE_CAP_INDEP_BLEND_ENABLE:
273 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
274 case PIPE_CAP_DEPTH_CLAMP:
275 case PIPE_CAP_SHADER_STENCIL_EXPORT:
276 return 1;
277
278 /* Unsupported features (boolean caps). */
279 case PIPE_CAP_TIMER_QUERY:
280 case PIPE_CAP_STREAM_OUTPUT:
281 case PIPE_CAP_PRIMITIVE_RESTART:
282 case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */
283 return 0;
284
285 /* Texturing. */
286 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
287 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
288 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
289 return 14;
290 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
291 /* FIXME allow this once infrastructure is there */
292 return 16;
293 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
294 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
295 return 16;
296
297 /* Render targets. */
298 case PIPE_CAP_MAX_RENDER_TARGETS:
299 /* FIXME some r6xx are buggy and can only do 4 */
300 return 8;
301
302 /* Fragment coordinate conventions. */
303 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
304 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
305 return 1;
306 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
307 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
308 return 0;
309
310 default:
311 R600_ERR("r600: unknown param %d\n", param);
312 return 0;
313 }
314 }
315
316 static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
317 {
318 switch (param) {
319 case PIPE_CAP_MAX_LINE_WIDTH:
320 case PIPE_CAP_MAX_LINE_WIDTH_AA:
321 case PIPE_CAP_MAX_POINT_WIDTH:
322 case PIPE_CAP_MAX_POINT_WIDTH_AA:
323 return 8192.0f;
324 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
325 return 16.0f;
326 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
327 return 16.0f;
328 default:
329 R600_ERR("r600: unsupported paramf %d\n", param);
330 return 0.0f;
331 }
332 }
333
334 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
335 {
336 switch(shader)
337 {
338 case PIPE_SHADER_FRAGMENT:
339 case PIPE_SHADER_VERTEX:
340 break;
341 case PIPE_SHADER_GEOMETRY:
342 /* TODO: support and enable geometry programs */
343 return 0;
344 default:
345 /* TODO: support tessellation on Evergreen */
346 return 0;
347 }
348
349 /* TODO: all these should be fixed, since r600 surely supports much more! */
350 switch (param) {
351 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
352 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
353 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
354 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
355 return 16384;
356 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
357 return 8; /* FIXME */
358 case PIPE_SHADER_CAP_MAX_INPUTS:
359 if(shader == PIPE_SHADER_FRAGMENT)
360 return 10;
361 else
362 return 16;
363 case PIPE_SHADER_CAP_MAX_TEMPS:
364 return 256; //max native temporaries
365 case PIPE_SHADER_CAP_MAX_ADDRS:
366 return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */
367 case PIPE_SHADER_CAP_MAX_CONSTS:
368 return 256; //max native parameters
369 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
370 return 1;
371 case PIPE_SHADER_CAP_MAX_PREDS:
372 return 0; /* FIXME */
373 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
374 return 1;
375 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
376 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
377 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
378 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
379 return 1;
380 case PIPE_SHADER_CAP_SUBROUTINES:
381 return 0;
382 default:
383 return 0;
384 }
385 }
386
387 static boolean r600_is_format_supported(struct pipe_screen* screen,
388 enum pipe_format format,
389 enum pipe_texture_target target,
390 unsigned sample_count,
391 unsigned usage,
392 unsigned geom_flags)
393 {
394 unsigned retval = 0;
395 if (target >= PIPE_MAX_TEXTURE_TYPES) {
396 R600_ERR("r600: unsupported texture type %d\n", target);
397 return FALSE;
398 }
399
400 /* Multisample */
401 if (sample_count > 1)
402 return FALSE;
403
404 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
405 r600_is_sampler_format_supported(format)) {
406 retval |= PIPE_BIND_SAMPLER_VIEW;
407 }
408
409 if ((usage & (PIPE_BIND_RENDER_TARGET |
410 PIPE_BIND_DISPLAY_TARGET |
411 PIPE_BIND_SCANOUT |
412 PIPE_BIND_SHARED)) &&
413 r600_is_colorbuffer_format_supported(format)) {
414 retval |= usage &
415 (PIPE_BIND_RENDER_TARGET |
416 PIPE_BIND_DISPLAY_TARGET |
417 PIPE_BIND_SCANOUT |
418 PIPE_BIND_SHARED);
419 }
420
421 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
422 r600_is_zs_format_supported(format)) {
423 retval |= PIPE_BIND_DEPTH_STENCIL;
424 }
425
426 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
427 r600_is_vertex_format_supported(format))
428 retval |= PIPE_BIND_VERTEX_BUFFER;
429
430 if (usage & PIPE_BIND_TRANSFER_READ)
431 retval |= PIPE_BIND_TRANSFER_READ;
432 if (usage & PIPE_BIND_TRANSFER_WRITE)
433 retval |= PIPE_BIND_TRANSFER_WRITE;
434
435 return retval == usage;
436 }
437
438 static void r600_destroy_screen(struct pipe_screen* pscreen)
439 {
440 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
441
442 if (rscreen == NULL)
443 return;
444
445 radeon_decref(rscreen->radeon);
446
447 FREE(rscreen);
448 }
449
450
451 struct pipe_screen *r600_screen_create(struct radeon *radeon)
452 {
453 struct r600_screen *rscreen;
454
455 rscreen = CALLOC_STRUCT(r600_screen);
456 if (rscreen == NULL) {
457 return NULL;
458 }
459
460 rscreen->radeon = radeon;
461 rscreen->screen.winsys = (struct pipe_winsys*)radeon;
462 rscreen->screen.destroy = r600_destroy_screen;
463 rscreen->screen.get_name = r600_get_name;
464 rscreen->screen.get_vendor = r600_get_vendor;
465 rscreen->screen.get_param = r600_get_param;
466 rscreen->screen.get_shader_param = r600_get_shader_param;
467 rscreen->screen.get_paramf = r600_get_paramf;
468 rscreen->screen.is_format_supported = r600_is_format_supported;
469 rscreen->screen.context_create = r600_create_context;
470 r600_init_screen_texture_functions(&rscreen->screen);
471 r600_init_screen_resource_functions(&rscreen->screen);
472
473 rscreen->tiling_info = r600_get_tiling_info(radeon);
474
475 return &rscreen->screen;
476 }