2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_pipe.h"
24 #include "r600_public.h"
26 #include "evergreen_compute.h"
29 #include "sb/sb_public.h"
32 #include "pipe/p_shader_tokens.h"
33 #include "util/u_blitter.h"
34 #include "util/u_debug.h"
35 #include "util/u_memory.h"
36 #include "util/u_simple_shaders.h"
37 #include "util/u_upload_mgr.h"
38 #include "util/u_math.h"
39 #include "vl/vl_decoder.h"
40 #include "vl/vl_video_buffer.h"
41 #include "radeon/radeon_uvd.h"
42 #include "os/os_time.h"
44 static const struct debug_named_value r600_debug_options
[] = {
46 { "nohyperz", DBG_NO_HYPERZ
, "Disable Hyper-Z" },
47 #if defined(R600_USE_LLVM)
48 { "nollvm", DBG_NO_LLVM
, "Disable the LLVM shader compiler" },
50 { "nocpdma", DBG_NO_CP_DMA
, "Disable CP DMA" },
51 { "nodma", DBG_NO_ASYNC_DMA
, "Disable asynchronous DMA" },
52 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
53 { "noinvalrange", DBG_NO_DISCARD_RANGE
, "Disable handling of INVALIDATE_RANGE map flags" },
56 { "nosb", DBG_NO_SB
, "Disable sb backend for graphics shaders" },
57 { "sbcl", DBG_SB_CS
, "Enable sb backend for compute shaders" },
58 { "sbdry", DBG_SB_DRY_RUN
, "Don't use optimized bytecode (just print the dumps)" },
59 { "sbstat", DBG_SB_STAT
, "Print optimization statistics for shaders" },
60 { "sbdump", DBG_SB_DUMP
, "Print IR dumps after some optimization passes" },
61 { "sbnofallback", DBG_SB_NO_FALLBACK
, "Abort on errors instead of fallback" },
62 { "sbdisasm", DBG_SB_DISASM
, "Use sb disassembler for shader dumps" },
63 { "sbsafemath", DBG_SB_SAFEMATH
, "Disable unsafe math optimizations" },
65 DEBUG_NAMED_VALUE_END
/* must be last */
72 static void r600_flush(struct pipe_context
*ctx
, unsigned flags
)
74 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
75 struct pipe_query
*render_cond
= NULL
;
76 unsigned render_cond_mode
= 0;
77 boolean render_cond_cond
= FALSE
;
79 if (rctx
->b
.rings
.gfx
.cs
->cdw
== rctx
->initial_gfx_cs_size
)
82 rctx
->b
.rings
.gfx
.flushing
= true;
83 /* Disable render condition. */
84 if (rctx
->current_render_cond
) {
85 render_cond
= rctx
->current_render_cond
;
86 render_cond_cond
= rctx
->current_render_cond_cond
;
87 render_cond_mode
= rctx
->current_render_cond_mode
;
88 ctx
->render_condition(ctx
, NULL
, FALSE
, 0);
91 r600_context_flush(rctx
, flags
);
92 rctx
->b
.rings
.gfx
.flushing
= false;
93 r600_begin_new_cs(rctx
);
95 /* Re-enable render condition. */
97 ctx
->render_condition(ctx
, render_cond
, render_cond_cond
, render_cond_mode
);
100 rctx
->initial_gfx_cs_size
= rctx
->b
.rings
.gfx
.cs
->cdw
;
103 static void r600_flush_from_st(struct pipe_context
*ctx
,
104 struct pipe_fence_handle
**fence
,
107 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
110 fflags
= flags
& PIPE_FLUSH_END_OF_FRAME
? RADEON_FLUSH_END_OF_FRAME
: 0;
112 *fence
= rctx
->b
.ws
->cs_create_fence(rctx
->b
.rings
.gfx
.cs
);
114 /* flush gfx & dma ring, order does not matter as only one can be live */
115 if (rctx
->b
.rings
.dma
.cs
) {
116 rctx
->b
.rings
.dma
.flush(rctx
, fflags
);
118 rctx
->b
.rings
.gfx
.flush(rctx
, fflags
);
121 static void r600_flush_gfx_ring(void *ctx
, unsigned flags
)
123 r600_flush((struct pipe_context
*)ctx
, flags
);
126 static void r600_flush_dma_ring(void *ctx
, unsigned flags
)
128 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
129 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.dma
.cs
;
135 rctx
->b
.rings
.dma
.flushing
= true;
136 rctx
->b
.ws
->cs_flush(cs
, flags
, 0);
137 rctx
->b
.rings
.dma
.flushing
= false;
140 static void r600_flush_from_winsys(void *ctx
, unsigned flags
)
142 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
144 rctx
->b
.rings
.gfx
.flush(rctx
, flags
);
147 static void r600_flush_dma_from_winsys(void *ctx
, unsigned flags
)
149 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
151 rctx
->b
.rings
.dma
.flush(rctx
, flags
);
154 static void r600_destroy_context(struct pipe_context
*context
)
156 struct r600_context
*rctx
= (struct r600_context
*)context
;
158 r600_isa_destroy(rctx
->isa
);
160 r600_sb_context_destroy(rctx
->sb_context
);
162 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_cmask
, NULL
);
163 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_fmask
, NULL
);
165 if (rctx
->dummy_pixel_shader
) {
166 rctx
->b
.b
.delete_fs_state(&rctx
->b
.b
, rctx
->dummy_pixel_shader
);
168 if (rctx
->custom_dsa_flush
) {
169 rctx
->b
.b
.delete_depth_stencil_alpha_state(&rctx
->b
.b
, rctx
->custom_dsa_flush
);
171 if (rctx
->custom_blend_resolve
) {
172 rctx
->b
.b
.delete_blend_state(&rctx
->b
.b
, rctx
->custom_blend_resolve
);
174 if (rctx
->custom_blend_decompress
) {
175 rctx
->b
.b
.delete_blend_state(&rctx
->b
.b
, rctx
->custom_blend_decompress
);
177 if (rctx
->custom_blend_fastclear
) {
178 rctx
->b
.b
.delete_blend_state(&rctx
->b
.b
, rctx
->custom_blend_fastclear
);
180 util_unreference_framebuffer_state(&rctx
->framebuffer
.state
);
183 util_blitter_destroy(rctx
->blitter
);
185 if (rctx
->uploader
) {
186 u_upload_destroy(rctx
->uploader
);
188 if (rctx
->allocator_fetch_shader
) {
189 u_suballocator_destroy(rctx
->allocator_fetch_shader
);
191 util_slab_destroy(&rctx
->pool_transfers
);
193 r600_release_command_buffer(&rctx
->start_cs_cmd
);
195 if (rctx
->b
.rings
.gfx
.cs
) {
196 rctx
->b
.ws
->cs_destroy(rctx
->b
.rings
.gfx
.cs
);
198 if (rctx
->b
.rings
.dma
.cs
) {
199 rctx
->b
.ws
->cs_destroy(rctx
->b
.rings
.dma
.cs
);
202 r600_common_context_cleanup(&rctx
->b
);
206 static struct pipe_context
*r600_create_context(struct pipe_screen
*screen
, void *priv
)
208 struct r600_context
*rctx
= CALLOC_STRUCT(r600_context
);
209 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
214 util_slab_create(&rctx
->pool_transfers
,
215 sizeof(struct r600_transfer
), 64,
216 UTIL_SLAB_SINGLETHREADED
);
218 rctx
->b
.b
.screen
= screen
;
219 rctx
->b
.b
.priv
= priv
;
220 rctx
->b
.b
.destroy
= r600_destroy_context
;
221 rctx
->b
.b
.flush
= r600_flush_from_st
;
223 if (!r600_common_context_init(&rctx
->b
, &rscreen
->b
))
226 rctx
->screen
= rscreen
;
227 rctx
->keep_tiling_flags
= rscreen
->b
.info
.drm_minor
>= 12;
229 LIST_INITHEAD(&rctx
->active_nontimer_queries
);
231 r600_init_blit_functions(rctx
);
232 r600_init_query_functions(rctx
);
233 r600_init_context_resource_functions(rctx
);
235 if (rscreen
->b
.info
.has_uvd
) {
236 rctx
->b
.b
.create_video_codec
= r600_uvd_create_decoder
;
237 rctx
->b
.b
.create_video_buffer
= r600_video_buffer_create
;
239 rctx
->b
.b
.create_video_codec
= vl_create_decoder
;
240 rctx
->b
.b
.create_video_buffer
= vl_video_buffer_create
;
243 r600_init_common_state_functions(rctx
);
245 switch (rctx
->b
.chip_class
) {
248 r600_init_state_functions(rctx
);
249 r600_init_atom_start_cs(rctx
);
251 rctx
->custom_dsa_flush
= r600_create_db_flush_dsa(rctx
);
252 rctx
->custom_blend_resolve
= rctx
->b
.chip_class
== R700
? r700_create_resolve_blend(rctx
)
253 : r600_create_resolve_blend(rctx
);
254 rctx
->custom_blend_decompress
= r600_create_decompress_blend(rctx
);
255 rctx
->has_vertex_cache
= !(rctx
->b
.family
== CHIP_RV610
||
256 rctx
->b
.family
== CHIP_RV620
||
257 rctx
->b
.family
== CHIP_RS780
||
258 rctx
->b
.family
== CHIP_RS880
||
259 rctx
->b
.family
== CHIP_RV710
);
263 evergreen_init_state_functions(rctx
);
264 evergreen_init_atom_start_cs(rctx
);
265 evergreen_init_atom_start_compute_cs(rctx
);
267 rctx
->custom_dsa_flush
= evergreen_create_db_flush_dsa(rctx
);
268 rctx
->custom_blend_resolve
= evergreen_create_resolve_blend(rctx
);
269 rctx
->custom_blend_decompress
= evergreen_create_decompress_blend(rctx
);
270 rctx
->custom_blend_fastclear
= evergreen_create_fastclear_blend(rctx
);
271 rctx
->has_vertex_cache
= !(rctx
->b
.family
== CHIP_CEDAR
||
272 rctx
->b
.family
== CHIP_PALM
||
273 rctx
->b
.family
== CHIP_SUMO
||
274 rctx
->b
.family
== CHIP_SUMO2
||
275 rctx
->b
.family
== CHIP_CAICOS
||
276 rctx
->b
.family
== CHIP_CAYMAN
||
277 rctx
->b
.family
== CHIP_ARUBA
);
280 R600_ERR("Unsupported chip class %d.\n", rctx
->b
.chip_class
);
284 if (rscreen
->trace_bo
) {
285 rctx
->b
.rings
.gfx
.cs
= rctx
->b
.ws
->cs_create(rctx
->b
.ws
, RING_GFX
, rscreen
->trace_bo
->cs_buf
);
287 rctx
->b
.rings
.gfx
.cs
= rctx
->b
.ws
->cs_create(rctx
->b
.ws
, RING_GFX
, NULL
);
289 rctx
->b
.rings
.gfx
.flush
= r600_flush_gfx_ring
;
290 rctx
->b
.ws
->cs_set_flush_callback(rctx
->b
.rings
.gfx
.cs
, r600_flush_from_winsys
, rctx
);
291 rctx
->b
.rings
.gfx
.flushing
= false;
293 rctx
->b
.rings
.dma
.cs
= NULL
;
294 if (rscreen
->b
.info
.r600_has_dma
&& !(rscreen
->b
.debug_flags
& DBG_NO_ASYNC_DMA
)) {
295 rctx
->b
.rings
.dma
.cs
= rctx
->b
.ws
->cs_create(rctx
->b
.ws
, RING_DMA
, NULL
);
296 rctx
->b
.rings
.dma
.flush
= r600_flush_dma_ring
;
297 rctx
->b
.ws
->cs_set_flush_callback(rctx
->b
.rings
.dma
.cs
, r600_flush_dma_from_winsys
, rctx
);
298 rctx
->b
.rings
.dma
.flushing
= false;
301 rctx
->uploader
= u_upload_create(&rctx
->b
.b
, 1024 * 1024, 256,
302 PIPE_BIND_INDEX_BUFFER
|
303 PIPE_BIND_CONSTANT_BUFFER
);
307 rctx
->allocator_fetch_shader
= u_suballocator_create(&rctx
->b
.b
, 64 * 1024, 256,
308 0, PIPE_USAGE_STATIC
, FALSE
);
309 if (!rctx
->allocator_fetch_shader
)
312 rctx
->isa
= calloc(1, sizeof(struct r600_isa
));
313 if (!rctx
->isa
|| r600_isa_init(rctx
, rctx
->isa
))
316 rctx
->blitter
= util_blitter_create(&rctx
->b
.b
);
317 if (rctx
->blitter
== NULL
)
319 util_blitter_set_texture_multisample(rctx
->blitter
, rscreen
->has_msaa
);
320 rctx
->blitter
->draw_rectangle
= r600_draw_rectangle
;
322 r600_begin_new_cs(rctx
);
323 r600_get_backend_mask(rctx
); /* this emits commands and must be last */
325 rctx
->dummy_pixel_shader
=
326 util_make_fragment_cloneinput_shader(&rctx
->b
.b
, 0,
327 TGSI_SEMANTIC_GENERIC
,
328 TGSI_INTERPOLATE_CONSTANT
);
329 rctx
->b
.b
.bind_fs_state(&rctx
->b
.b
, rctx
->dummy_pixel_shader
);
334 r600_destroy_context(&rctx
->b
.b
);
341 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
346 static const char *r600_get_family_name(enum radeon_family family
)
349 case CHIP_R600
: return "AMD R600";
350 case CHIP_RV610
: return "AMD RV610";
351 case CHIP_RV630
: return "AMD RV630";
352 case CHIP_RV670
: return "AMD RV670";
353 case CHIP_RV620
: return "AMD RV620";
354 case CHIP_RV635
: return "AMD RV635";
355 case CHIP_RS780
: return "AMD RS780";
356 case CHIP_RS880
: return "AMD RS880";
357 case CHIP_RV770
: return "AMD RV770";
358 case CHIP_RV730
: return "AMD RV730";
359 case CHIP_RV710
: return "AMD RV710";
360 case CHIP_RV740
: return "AMD RV740";
361 case CHIP_CEDAR
: return "AMD CEDAR";
362 case CHIP_REDWOOD
: return "AMD REDWOOD";
363 case CHIP_JUNIPER
: return "AMD JUNIPER";
364 case CHIP_CYPRESS
: return "AMD CYPRESS";
365 case CHIP_HEMLOCK
: return "AMD HEMLOCK";
366 case CHIP_PALM
: return "AMD PALM";
367 case CHIP_SUMO
: return "AMD SUMO";
368 case CHIP_SUMO2
: return "AMD SUMO2";
369 case CHIP_BARTS
: return "AMD BARTS";
370 case CHIP_TURKS
: return "AMD TURKS";
371 case CHIP_CAICOS
: return "AMD CAICOS";
372 case CHIP_CAYMAN
: return "AMD CAYMAN";
373 case CHIP_ARUBA
: return "AMD ARUBA";
374 default: return "AMD unknown";
378 static const char* r600_get_name(struct pipe_screen
* pscreen
)
380 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
382 return r600_get_family_name(rscreen
->b
.family
);
385 static int r600_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
387 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
388 enum radeon_family family
= rscreen
->b
.family
;
391 /* Supported features (boolean caps). */
392 case PIPE_CAP_NPOT_TEXTURES
:
393 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
394 case PIPE_CAP_TWO_SIDED_STENCIL
:
395 case PIPE_CAP_ANISOTROPIC_FILTER
:
396 case PIPE_CAP_POINT_SPRITE
:
397 case PIPE_CAP_OCCLUSION_QUERY
:
398 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
399 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
400 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
401 case PIPE_CAP_TEXTURE_SWIZZLE
:
402 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
403 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
404 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
405 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
406 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
407 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
409 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
410 case PIPE_CAP_PRIMITIVE_RESTART
:
411 case PIPE_CAP_CONDITIONAL_RENDER
:
412 case PIPE_CAP_TEXTURE_BARRIER
:
413 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
414 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
415 case PIPE_CAP_TGSI_INSTANCEID
:
416 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
417 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
418 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
419 case PIPE_CAP_USER_INDEX_BUFFERS
:
420 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
421 case PIPE_CAP_COMPUTE
:
422 case PIPE_CAP_START_INSTANCE
:
423 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
424 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
425 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
426 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
427 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
430 case PIPE_CAP_TGSI_TEXCOORD
:
433 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
434 return MIN2(rscreen
->b
.info
.vram_size
, 0xFFFFFFFF);
436 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
437 return R600_MAP_BUFFER_ALIGNMENT
;
439 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
442 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
445 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
448 /* Supported except the original R600. */
449 case PIPE_CAP_INDEP_BLEND_ENABLE
:
450 case PIPE_CAP_INDEP_BLEND_FUNC
:
451 /* R600 doesn't support per-MRT blends */
452 return family
== CHIP_R600
? 0 : 1;
454 /* Supported on Evergreen. */
455 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
456 case PIPE_CAP_CUBE_MAP_ARRAY
:
457 return family
>= CHIP_CEDAR
? 1 : 0;
459 /* Unsupported features. */
460 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
461 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
462 case PIPE_CAP_SCALED_RESOLVE
:
463 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
464 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
465 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
466 case PIPE_CAP_USER_VERTEX_BUFFERS
:
470 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
471 return rscreen
->has_streamout
? 4 : 0;
472 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
473 return rscreen
->has_streamout
? 1 : 0;
474 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
475 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
479 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
480 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
481 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
482 if (family
>= CHIP_CEDAR
)
486 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
487 return rscreen
->b
.info
.drm_minor
>= 9 ?
488 (family
>= CHIP_CEDAR
? 16384 : 8192) : 0;
489 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
492 /* Render targets. */
493 case PIPE_CAP_MAX_RENDER_TARGETS
:
494 /* XXX some r6xx are buggy and can only do 4 */
497 case PIPE_CAP_MAX_VIEWPORTS
:
500 /* Timer queries, present when the clock frequency is non zero. */
501 case PIPE_CAP_QUERY_TIME_ELAPSED
:
502 return rscreen
->b
.info
.r600_clock_crystal_freq
!= 0;
503 case PIPE_CAP_QUERY_TIMESTAMP
:
504 return rscreen
->b
.info
.drm_minor
>= 20 &&
505 rscreen
->b
.info
.r600_clock_crystal_freq
!= 0;
507 case PIPE_CAP_MIN_TEXEL_OFFSET
:
510 case PIPE_CAP_MAX_TEXEL_OFFSET
:
513 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
514 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
;
515 case PIPE_CAP_ENDIANNESS
:
516 return PIPE_ENDIAN_LITTLE
;
521 static float r600_get_paramf(struct pipe_screen
* pscreen
,
522 enum pipe_capf param
)
524 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
525 enum radeon_family family
= rscreen
->b
.family
;
528 case PIPE_CAPF_MAX_LINE_WIDTH
:
529 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
530 case PIPE_CAPF_MAX_POINT_WIDTH
:
531 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
532 if (family
>= CHIP_CEDAR
)
536 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
538 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
540 case PIPE_CAPF_GUARD_BAND_LEFT
:
541 case PIPE_CAPF_GUARD_BAND_TOP
:
542 case PIPE_CAPF_GUARD_BAND_RIGHT
:
543 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
549 static int r600_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
553 case PIPE_SHADER_FRAGMENT
:
554 case PIPE_SHADER_VERTEX
:
555 case PIPE_SHADER_COMPUTE
:
557 case PIPE_SHADER_GEOMETRY
:
558 /* XXX: support and enable geometry programs */
561 /* XXX: support tessellation on Evergreen */
566 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
567 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
568 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
569 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
571 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
573 case PIPE_SHADER_CAP_MAX_INPUTS
:
575 case PIPE_SHADER_CAP_MAX_TEMPS
:
576 return 256; /* Max native temporaries. */
577 case PIPE_SHADER_CAP_MAX_ADDRS
:
578 /* XXX Isn't this equal to TEMPS? */
579 return 1; /* Max native address registers */
580 case PIPE_SHADER_CAP_MAX_CONSTS
:
581 return R600_MAX_CONST_BUFFER_SIZE
;
582 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
583 return R600_MAX_USER_CONST_BUFFERS
;
584 case PIPE_SHADER_CAP_MAX_PREDS
:
585 return 0; /* nothing uses this */
586 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
588 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
590 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
591 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
592 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
593 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
595 case PIPE_SHADER_CAP_SUBROUTINES
:
597 case PIPE_SHADER_CAP_INTEGERS
:
599 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
600 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
602 case PIPE_SHADER_CAP_PREFERRED_IR
:
603 if (shader
== PIPE_SHADER_COMPUTE
) {
604 return PIPE_SHADER_IR_LLVM
;
606 return PIPE_SHADER_IR_TGSI
;
612 static int r600_get_video_param(struct pipe_screen
*screen
,
613 enum pipe_video_profile profile
,
614 enum pipe_video_entrypoint entrypoint
,
615 enum pipe_video_cap param
)
618 case PIPE_VIDEO_CAP_SUPPORTED
:
619 return vl_profile_supported(screen
, profile
, entrypoint
);
620 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
622 case PIPE_VIDEO_CAP_MAX_WIDTH
:
623 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
624 return vl_video_buffer_max_size(screen
);
625 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
626 return PIPE_FORMAT_NV12
;
627 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
629 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
631 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
633 case PIPE_VIDEO_CAP_MAX_LEVEL
:
634 return vl_level_supported(screen
, profile
);
640 const char * r600_llvm_gpu_string(enum radeon_family family
)
642 const char * gpu_family
;
655 gpu_family
= "rs880";
658 gpu_family
= "rv710";
661 gpu_family
= "rv730";
665 gpu_family
= "rv770";
669 gpu_family
= "cedar";
676 gpu_family
= "redwood";
679 gpu_family
= "juniper";
683 gpu_family
= "cypress";
686 gpu_family
= "barts";
689 gpu_family
= "turks";
692 gpu_family
= "caicos";
696 gpu_family
= "cayman";
700 fprintf(stderr
, "Chip not supported by r600 llvm "
701 "backend, please file a bug at " PACKAGE_BUGREPORT
"\n");
708 static int r600_get_compute_param(struct pipe_screen
*screen
,
709 enum pipe_compute_cap param
,
712 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
713 //TODO: select these params by asic
715 case PIPE_COMPUTE_CAP_IR_TARGET
: {
716 const char *gpu
= r600_llvm_gpu_string(rscreen
->b
.family
);
718 sprintf(ret
, "%s-r600--", gpu
);
720 return (8 + strlen(gpu
)) * sizeof(char);
722 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
724 uint64_t * grid_dimension
= ret
;
725 grid_dimension
[0] = 3;
727 return 1 * sizeof(uint64_t);
729 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
731 uint64_t * grid_size
= ret
;
732 grid_size
[0] = 65535;
733 grid_size
[1] = 65535;
736 return 3 * sizeof(uint64_t) ;
738 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
740 uint64_t * block_size
= ret
;
745 return 3 * sizeof(uint64_t);
747 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
749 uint64_t * max_threads_per_block
= ret
;
750 *max_threads_per_block
= 256;
752 return sizeof(uint64_t);
754 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
756 uint64_t * max_global_size
= ret
;
757 /* XXX: This is what the proprietary driver reports, we
758 * may want to use a different value. */
759 *max_global_size
= 201326592;
761 return sizeof(uint64_t);
763 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
765 uint64_t * max_input_size
= ret
;
766 *max_input_size
= 1024;
768 return sizeof(uint64_t);
770 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
772 uint64_t * max_local_size
= ret
;
773 /* XXX: This is what the proprietary driver reports, we
774 * may want to use a different value. */
775 *max_local_size
= 32768;
777 return sizeof(uint64_t);
779 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
781 uint64_t max_global_size
;
782 uint64_t * max_mem_alloc_size
= ret
;
783 r600_get_compute_param(screen
,
784 PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
,
786 /* OpenCL requres this value be at least
787 * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
788 * I'm really not sure what value to report here, but
789 * MAX_GLOBAL_SIZE / 4 seems resonable.
791 *max_mem_alloc_size
= max_global_size
/ 4;
793 return sizeof(uint64_t);
796 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
801 static void r600_destroy_screen(struct pipe_screen
* pscreen
)
803 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
808 if (!radeon_winsys_unref(rscreen
->b
.ws
))
811 r600_common_screen_cleanup(&rscreen
->b
);
813 if (rscreen
->global_pool
) {
814 compute_memory_pool_delete(rscreen
->global_pool
);
817 if (rscreen
->trace_bo
) {
818 rscreen
->b
.ws
->buffer_unmap(rscreen
->trace_bo
->cs_buf
);
819 pipe_resource_reference((struct pipe_resource
**)&rscreen
->trace_bo
, NULL
);
822 rscreen
->b
.ws
->destroy(rscreen
->b
.ws
);
826 static uint64_t r600_get_timestamp(struct pipe_screen
*screen
)
828 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
830 return 1000000 * rscreen
->b
.ws
->query_value(rscreen
->b
.ws
, RADEON_TIMESTAMP
) /
831 rscreen
->b
.info
.r600_clock_crystal_freq
;
834 static int r600_get_driver_query_info(struct pipe_screen
*screen
,
836 struct pipe_driver_query_info
*info
)
838 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
839 struct pipe_driver_query_info list
[] = {
840 {"draw-calls", R600_QUERY_DRAW_CALLS
, 0},
841 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM
, rscreen
->b
.info
.vram_size
, TRUE
},
842 {"requested-GTT", R600_QUERY_REQUESTED_GTT
, rscreen
->b
.info
.gart_size
, TRUE
},
843 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME
, 0, FALSE
}
847 return Elements(list
);
849 if (index
>= Elements(list
))
856 struct pipe_screen
*r600_screen_create(struct radeon_winsys
*ws
)
858 struct r600_screen
*rscreen
= CALLOC_STRUCT(r600_screen
);
860 if (rscreen
== NULL
) {
864 ws
->query_info(ws
, &rscreen
->b
.info
);
866 /* Set functions first. */
867 rscreen
->b
.b
.context_create
= r600_create_context
;
868 rscreen
->b
.b
.destroy
= r600_destroy_screen
;
869 rscreen
->b
.b
.get_name
= r600_get_name
;
870 rscreen
->b
.b
.get_vendor
= r600_get_vendor
;
871 rscreen
->b
.b
.get_param
= r600_get_param
;
872 rscreen
->b
.b
.get_shader_param
= r600_get_shader_param
;
873 rscreen
->b
.b
.get_paramf
= r600_get_paramf
;
874 rscreen
->b
.b
.get_compute_param
= r600_get_compute_param
;
875 rscreen
->b
.b
.get_timestamp
= r600_get_timestamp
;
876 if (rscreen
->b
.info
.chip_class
>= EVERGREEN
) {
877 rscreen
->b
.b
.is_format_supported
= evergreen_is_format_supported
;
879 rscreen
->b
.b
.is_format_supported
= r600_is_format_supported
;
881 rscreen
->b
.b
.get_driver_query_info
= r600_get_driver_query_info
;
882 if (rscreen
->b
.info
.has_uvd
) {
883 rscreen
->b
.b
.get_video_param
= ruvd_get_video_param
;
884 rscreen
->b
.b
.is_video_format_supported
= ruvd_is_format_supported
;
886 rscreen
->b
.b
.get_video_param
= r600_get_video_param
;
887 rscreen
->b
.b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
889 r600_init_screen_resource_functions(&rscreen
->b
.b
);
891 if (!r600_common_screen_init(&rscreen
->b
, ws
)) {
896 rscreen
->b
.debug_flags
|= debug_get_flags_option("R600_DEBUG", r600_debug_options
, 0);
897 if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE
))
898 rscreen
->b
.debug_flags
|= DBG_COMPUTE
;
899 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE
))
900 rscreen
->b
.debug_flags
|= DBG_FS
| DBG_VS
| DBG_GS
| DBG_PS
| DBG_CS
;
901 if (!debug_get_bool_option("R600_HYPERZ", TRUE
))
902 rscreen
->b
.debug_flags
|= DBG_NO_HYPERZ
;
903 if (!debug_get_bool_option("R600_LLVM", TRUE
))
904 rscreen
->b
.debug_flags
|= DBG_NO_LLVM
;
906 if (rscreen
->b
.family
== CHIP_UNKNOWN
) {
907 fprintf(stderr
, "r600: Unknown chipset 0x%04X\n", rscreen
->b
.info
.pci_id
);
912 /* Figure out streamout kernel support. */
913 switch (rscreen
->b
.chip_class
) {
915 if (rscreen
->b
.family
< CHIP_RS780
) {
916 rscreen
->has_streamout
= rscreen
->b
.info
.drm_minor
>= 14;
918 rscreen
->has_streamout
= rscreen
->b
.info
.drm_minor
>= 23;
922 rscreen
->has_streamout
= rscreen
->b
.info
.drm_minor
>= 17;
926 rscreen
->has_streamout
= rscreen
->b
.info
.drm_minor
>= 14;
929 rscreen
->has_streamout
= FALSE
;
934 switch (rscreen
->b
.chip_class
) {
937 rscreen
->has_msaa
= rscreen
->b
.info
.drm_minor
>= 22;
938 rscreen
->has_compressed_msaa_texturing
= false;
941 rscreen
->has_msaa
= rscreen
->b
.info
.drm_minor
>= 19;
942 rscreen
->has_compressed_msaa_texturing
= rscreen
->b
.info
.drm_minor
>= 24;
945 rscreen
->has_msaa
= rscreen
->b
.info
.drm_minor
>= 19;
946 rscreen
->has_compressed_msaa_texturing
= true;
949 rscreen
->has_msaa
= FALSE
;
950 rscreen
->has_compressed_msaa_texturing
= false;
953 rscreen
->has_cp_dma
= rscreen
->b
.info
.drm_minor
>= 27 &&
954 !(rscreen
->b
.debug_flags
& DBG_NO_CP_DMA
);
956 rscreen
->global_pool
= compute_memory_pool_new(rscreen
);
958 rscreen
->cs_count
= 0;
959 if (rscreen
->b
.info
.drm_minor
>= 28 && (rscreen
->b
.debug_flags
& DBG_TRACE_CS
)) {
960 rscreen
->trace_bo
= (struct r600_resource
*)pipe_buffer_create(&rscreen
->b
.b
,
964 if (rscreen
->trace_bo
) {
965 rscreen
->trace_ptr
= rscreen
->b
.ws
->buffer_map(rscreen
->trace_bo
->cs_buf
, NULL
,
966 PIPE_TRANSFER_UNSYNCHRONIZED
);
970 /* Create the auxiliary context. This must be done last. */
971 rscreen
->b
.aux_context
= rscreen
->b
.b
.context_create(&rscreen
->b
.b
, NULL
);
973 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
974 struct pipe_resource templ
= {};
977 templ
.height0
= 2048;
979 templ
.array_size
= 1;
980 templ
.target
= PIPE_TEXTURE_2D
;
981 templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
982 templ
.usage
= PIPE_USAGE_STATIC
;
984 struct r600_resource
*res
= r600_resource(rscreen
->screen
.resource_create(&rscreen
->screen
, &templ
));
985 unsigned char *map
= ws
->buffer_map(res
->cs_buf
, NULL
, PIPE_TRANSFER_WRITE
);
989 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 4, 4, 0xCC);
990 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 8, 4, 0xDD);
991 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 12, 4, 0xEE);
992 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 20, 4, 0xFF);
993 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 32, 20, 0x87);
995 ws
->buffer_wait(res
->buf
, RADEON_USAGE_WRITE
);
998 for (i
= 0; i
< 256; i
++) {
999 printf("%02X", map
[i
]);
1005 return &rscreen
->b
.b
;