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[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_pipe.h"
24 #include "r600_public.h"
25 #include "r600_isa.h"
26 #include "evergreen_compute.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include "pipe/p_shader_tokens.h"
31 #include "util/u_blitter.h"
32 #include "util/u_debug.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_memory.h"
35 #include "util/u_simple_shaders.h"
36 #include "util/u_upload_mgr.h"
37 #include "util/u_math.h"
38 #include "vl/vl_decoder.h"
39 #include "vl/vl_video_buffer.h"
40 #include "radeon/radeon_uvd.h"
41 #include "os/os_time.h"
42
43 static const struct debug_named_value debug_options[] = {
44 /* logging */
45 { "texdepth", DBG_TEX_DEPTH, "Print texture depth info" },
46 { "compute", DBG_COMPUTE, "Print compute info" },
47
48 /* shaders */
49 { "fs", DBG_FS, "Print fetch shaders" },
50 { "vs", DBG_VS, "Print vertex shaders" },
51 { "gs", DBG_GS, "Print geometry shaders" },
52 { "ps", DBG_PS, "Print pixel shaders" },
53 { "cs", DBG_CS, "Print compute shaders" },
54
55 /* features */
56 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
57 #if defined(R600_USE_LLVM)
58 { "nollvm", DBG_NO_LLVM, "Disable the LLVM shader compiler" },
59 #endif
60 { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
61 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
62 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
63 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
64
65 DEBUG_NAMED_VALUE_END /* must be last */
66 };
67
68 /*
69 * pipe_context
70 */
71 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
72 {
73 struct r600_screen *rscreen = rctx->screen;
74 struct r600_fence *fence = NULL;
75
76 pipe_mutex_lock(rscreen->fences.mutex);
77
78 if (!rscreen->fences.bo) {
79 /* Create the shared buffer object */
80 rscreen->fences.bo = (struct r600_resource*)
81 pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
82 PIPE_USAGE_STAGING, 4096);
83 if (!rscreen->fences.bo) {
84 R600_ERR("r600: failed to create bo for fence objects\n");
85 goto out;
86 }
87 rscreen->fences.data = r600_buffer_mmap_sync_with_rings(rctx, rscreen->fences.bo, PIPE_TRANSFER_READ_WRITE);
88 }
89
90 if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
91 struct r600_fence *entry;
92
93 /* Try to find a freed fence that has been signalled */
94 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
95 if (rscreen->fences.data[entry->index] != 0) {
96 LIST_DELINIT(&entry->head);
97 fence = entry;
98 break;
99 }
100 }
101 }
102
103 if (!fence) {
104 /* Allocate a new fence */
105 struct r600_fence_block *block;
106 unsigned index;
107
108 if ((rscreen->fences.next_index + 1) >= 1024) {
109 R600_ERR("r600: too many concurrent fences\n");
110 goto out;
111 }
112
113 index = rscreen->fences.next_index++;
114
115 if (!(index % FENCE_BLOCK_SIZE)) {
116 /* Allocate a new block */
117 block = CALLOC_STRUCT(r600_fence_block);
118 if (block == NULL)
119 goto out;
120
121 LIST_ADD(&block->head, &rscreen->fences.blocks);
122 } else {
123 block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
124 }
125
126 fence = &block->fences[index % FENCE_BLOCK_SIZE];
127 fence->index = index;
128 }
129
130 pipe_reference_init(&fence->reference, 1);
131
132 rscreen->fences.data[fence->index] = 0;
133 r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
134
135 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
136 fence->sleep_bo = (struct r600_resource*)
137 pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
138 PIPE_USAGE_STAGING, 1);
139 /* Add the fence as a dummy relocation. */
140 r600_context_bo_reloc(rctx, &rctx->rings.gfx, fence->sleep_bo, RADEON_USAGE_READWRITE);
141
142 out:
143 pipe_mutex_unlock(rscreen->fences.mutex);
144 return fence;
145 }
146
147 static void r600_flush(struct pipe_context *ctx, unsigned flags)
148 {
149 struct r600_context *rctx = (struct r600_context *)ctx;
150 struct pipe_query *render_cond = NULL;
151 unsigned render_cond_mode = 0;
152
153 rctx->rings.gfx.flushing = true;
154 /* Disable render condition. */
155 if (rctx->current_render_cond) {
156 render_cond = rctx->current_render_cond;
157 render_cond_mode = rctx->current_render_cond_mode;
158 ctx->render_condition(ctx, NULL, 0);
159 }
160
161 r600_context_flush(rctx, flags);
162 rctx->rings.gfx.flushing = false;
163 r600_begin_new_cs(rctx);
164
165 /* Re-enable render condition. */
166 if (render_cond) {
167 ctx->render_condition(ctx, render_cond, render_cond_mode);
168 }
169 }
170
171 static void r600_flush_from_st(struct pipe_context *ctx,
172 struct pipe_fence_handle **fence,
173 enum pipe_flush_flags flags)
174 {
175 struct r600_context *rctx = (struct r600_context *)ctx;
176 struct r600_fence **rfence = (struct r600_fence**)fence;
177 unsigned fflags;
178
179 fflags = flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0;
180 if (rfence) {
181 *rfence = r600_create_fence(rctx);
182 }
183 /* flush gfx & dma ring, order does not matter as only one can be live */
184 if (rctx->rings.dma.cs) {
185 rctx->rings.dma.flush(rctx, fflags);
186 }
187 rctx->rings.gfx.flush(rctx, fflags);
188 }
189
190 static void r600_flush_gfx_ring(void *ctx, unsigned flags)
191 {
192 r600_flush((struct pipe_context*)ctx, flags);
193 }
194
195 static void r600_flush_dma_ring(void *ctx, unsigned flags)
196 {
197 struct r600_context *rctx = (struct r600_context *)ctx;
198 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
199 unsigned padding_dw, i;
200
201 if (!cs->cdw) {
202 return;
203 }
204
205 /* Pad the DMA CS to a multiple of 8 dwords. */
206 padding_dw = 8 - cs->cdw % 8;
207 if (padding_dw < 8) {
208 for (i = 0; i < padding_dw; i++) {
209 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
210 }
211 }
212
213 rctx->rings.dma.flushing = true;
214 rctx->ws->cs_flush(cs, flags);
215 rctx->rings.dma.flushing = false;
216 }
217
218 boolean r600_rings_is_buffer_referenced(struct r600_context *ctx,
219 struct radeon_winsys_cs_handle *buf,
220 enum radeon_bo_usage usage)
221 {
222 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, buf, usage)) {
223 return TRUE;
224 }
225 if (ctx->rings.dma.cs) {
226 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, buf, usage)) {
227 return TRUE;
228 }
229 }
230 return FALSE;
231 }
232
233 void *r600_buffer_mmap_sync_with_rings(struct r600_context *ctx,
234 struct r600_resource *resource,
235 unsigned usage)
236 {
237 enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
238 unsigned flags = 0;
239 bool sync_flush = TRUE;
240
241 if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
242 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
243 }
244
245 if (!(usage & PIPE_TRANSFER_WRITE)) {
246 /* have to wait for pending read */
247 rusage = RADEON_USAGE_WRITE;
248 }
249 if (usage & PIPE_TRANSFER_DONTBLOCK) {
250 flags |= RADEON_FLUSH_ASYNC;
251 }
252
253 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, resource->cs_buf, rusage) && ctx->rings.gfx.cs->cdw) {
254 ctx->rings.gfx.flush(ctx, flags);
255 if (usage & PIPE_TRANSFER_DONTBLOCK) {
256 return NULL;
257 }
258 }
259 if (ctx->rings.dma.cs) {
260 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, resource->cs_buf, rusage) && ctx->rings.dma.cs->cdw) {
261 ctx->rings.dma.flush(ctx, flags);
262 if (usage & PIPE_TRANSFER_DONTBLOCK) {
263 return NULL;
264 }
265 }
266 }
267
268 if (usage & PIPE_TRANSFER_DONTBLOCK) {
269 if (ctx->ws->buffer_is_busy(resource->buf, rusage)) {
270 return NULL;
271 }
272 }
273 if (sync_flush) {
274 /* Try to avoid busy-waiting in radeon_bo_wait. */
275 ctx->ws->cs_sync_flush(ctx->rings.gfx.cs);
276 if (ctx->rings.dma.cs) {
277 ctx->ws->cs_sync_flush(ctx->rings.dma.cs);
278 }
279 }
280 ctx->ws->buffer_wait(resource->buf, rusage);
281
282 /* at this point everything is synchronized */
283 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage | PIPE_TRANSFER_UNSYNCHRONIZED);
284 }
285
286 static void r600_flush_from_winsys(void *ctx, unsigned flags)
287 {
288 struct r600_context *rctx = (struct r600_context *)ctx;
289
290 rctx->rings.gfx.flush(rctx, flags);
291 }
292
293 static void r600_flush_dma_from_winsys(void *ctx, unsigned flags)
294 {
295 struct r600_context *rctx = (struct r600_context *)ctx;
296
297 rctx->rings.dma.flush(rctx, flags);
298 }
299
300 static void r600_destroy_context(struct pipe_context *context)
301 {
302 struct r600_context *rctx = (struct r600_context *)context;
303
304 r600_isa_destroy(rctx->isa);
305
306 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
307 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
308
309 if (rctx->dummy_pixel_shader) {
310 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
311 }
312 if (rctx->custom_dsa_flush) {
313 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
314 }
315 if (rctx->custom_blend_resolve) {
316 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve);
317 }
318 if (rctx->custom_blend_decompress) {
319 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_decompress);
320 }
321 if (rctx->custom_blend_fmask_decompress) {
322 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_fmask_decompress);
323 }
324 util_unreference_framebuffer_state(&rctx->framebuffer.state);
325
326 if (rctx->blitter) {
327 util_blitter_destroy(rctx->blitter);
328 }
329 if (rctx->uploader) {
330 u_upload_destroy(rctx->uploader);
331 }
332 if (rctx->allocator_so_filled_size) {
333 u_suballocator_destroy(rctx->allocator_so_filled_size);
334 }
335 if (rctx->allocator_fetch_shader) {
336 u_suballocator_destroy(rctx->allocator_fetch_shader);
337 }
338 util_slab_destroy(&rctx->pool_transfers);
339
340 r600_release_command_buffer(&rctx->start_cs_cmd);
341
342 if (rctx->rings.gfx.cs) {
343 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
344 }
345 if (rctx->rings.dma.cs) {
346 rctx->ws->cs_destroy(rctx->rings.dma.cs);
347 }
348
349 FREE(rctx);
350 }
351
352 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
353 {
354 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
355 struct r600_screen* rscreen = (struct r600_screen *)screen;
356
357 if (rctx == NULL)
358 return NULL;
359
360 util_slab_create(&rctx->pool_transfers,
361 sizeof(struct r600_transfer), 64,
362 UTIL_SLAB_SINGLETHREADED);
363
364 rctx->context.screen = screen;
365 rctx->context.priv = priv;
366 rctx->context.destroy = r600_destroy_context;
367 rctx->context.flush = r600_flush_from_st;
368
369 /* Easy accessing of screen/winsys. */
370 rctx->screen = rscreen;
371 rctx->ws = rscreen->ws;
372 rctx->family = rscreen->family;
373 rctx->chip_class = rscreen->chip_class;
374 rctx->keep_tiling_flags = rscreen->info.drm_minor >= 12;
375
376 LIST_INITHEAD(&rctx->active_nontimer_queries);
377
378 r600_init_blit_functions(rctx);
379 r600_init_query_functions(rctx);
380 r600_init_context_resource_functions(rctx);
381 r600_init_surface_functions(rctx);
382
383 if (rscreen->info.has_uvd) {
384 rctx->context.create_video_decoder = r600_uvd_create_decoder;
385 rctx->context.create_video_buffer = r600_video_buffer_create;
386 } else {
387 rctx->context.create_video_decoder = vl_create_decoder;
388 rctx->context.create_video_buffer = vl_video_buffer_create;
389 }
390
391 r600_init_common_state_functions(rctx);
392
393 switch (rctx->chip_class) {
394 case R600:
395 case R700:
396 r600_init_state_functions(rctx);
397 r600_init_atom_start_cs(rctx);
398 rctx->max_db = 4;
399 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
400 rctx->custom_blend_resolve = rctx->chip_class == R700 ? r700_create_resolve_blend(rctx)
401 : r600_create_resolve_blend(rctx);
402 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
403 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
404 rctx->family == CHIP_RV620 ||
405 rctx->family == CHIP_RS780 ||
406 rctx->family == CHIP_RS880 ||
407 rctx->family == CHIP_RV710);
408 break;
409 case EVERGREEN:
410 case CAYMAN:
411 evergreen_init_state_functions(rctx);
412 evergreen_init_atom_start_cs(rctx);
413 evergreen_init_atom_start_compute_cs(rctx);
414 rctx->max_db = 8;
415 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
416 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
417 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
418 rctx->custom_blend_fmask_decompress = evergreen_create_fmask_decompress_blend(rctx);
419 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
420 rctx->family == CHIP_PALM ||
421 rctx->family == CHIP_SUMO ||
422 rctx->family == CHIP_SUMO2 ||
423 rctx->family == CHIP_CAICOS ||
424 rctx->family == CHIP_CAYMAN ||
425 rctx->family == CHIP_ARUBA);
426 break;
427 default:
428 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
429 goto fail;
430 }
431
432 rctx->rings.gfx.cs = rctx->ws->cs_create(rctx->ws, RING_GFX);
433 rctx->rings.gfx.flush = r600_flush_gfx_ring;
434 rctx->ws->cs_set_flush_callback(rctx->rings.gfx.cs, r600_flush_from_winsys, rctx);
435 rctx->rings.gfx.flushing = false;
436
437 rctx->rings.dma.cs = NULL;
438 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
439 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA);
440 rctx->rings.dma.flush = r600_flush_dma_ring;
441 rctx->ws->cs_set_flush_callback(rctx->rings.dma.cs, r600_flush_dma_from_winsys, rctx);
442 rctx->rings.dma.flushing = false;
443 }
444
445 rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
446 PIPE_BIND_INDEX_BUFFER |
447 PIPE_BIND_CONSTANT_BUFFER);
448 if (!rctx->uploader)
449 goto fail;
450
451 rctx->allocator_fetch_shader = u_suballocator_create(&rctx->context, 64 * 1024, 256,
452 0, PIPE_USAGE_STATIC, FALSE);
453 if (!rctx->allocator_fetch_shader)
454 goto fail;
455
456 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->context, 4096, 4,
457 0, PIPE_USAGE_STATIC, TRUE);
458 if (!rctx->allocator_so_filled_size)
459 goto fail;
460
461 rctx->isa = calloc(1, sizeof(struct r600_isa));
462 if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
463 goto fail;
464
465 rctx->blitter = util_blitter_create(&rctx->context);
466 if (rctx->blitter == NULL)
467 goto fail;
468 util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
469 rctx->blitter->draw_rectangle = r600_draw_rectangle;
470
471 r600_begin_new_cs(rctx);
472 r600_get_backend_mask(rctx); /* this emits commands and must be last */
473
474 rctx->dummy_pixel_shader =
475 util_make_fragment_cloneinput_shader(&rctx->context, 0,
476 TGSI_SEMANTIC_GENERIC,
477 TGSI_INTERPOLATE_CONSTANT);
478 rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
479
480 return &rctx->context;
481
482 fail:
483 r600_destroy_context(&rctx->context);
484 return NULL;
485 }
486
487 /*
488 * pipe_screen
489 */
490 static const char* r600_get_vendor(struct pipe_screen* pscreen)
491 {
492 return "X.Org";
493 }
494
495 static const char *r600_get_family_name(enum radeon_family family)
496 {
497 switch(family) {
498 case CHIP_R600: return "AMD R600";
499 case CHIP_RV610: return "AMD RV610";
500 case CHIP_RV630: return "AMD RV630";
501 case CHIP_RV670: return "AMD RV670";
502 case CHIP_RV620: return "AMD RV620";
503 case CHIP_RV635: return "AMD RV635";
504 case CHIP_RS780: return "AMD RS780";
505 case CHIP_RS880: return "AMD RS880";
506 case CHIP_RV770: return "AMD RV770";
507 case CHIP_RV730: return "AMD RV730";
508 case CHIP_RV710: return "AMD RV710";
509 case CHIP_RV740: return "AMD RV740";
510 case CHIP_CEDAR: return "AMD CEDAR";
511 case CHIP_REDWOOD: return "AMD REDWOOD";
512 case CHIP_JUNIPER: return "AMD JUNIPER";
513 case CHIP_CYPRESS: return "AMD CYPRESS";
514 case CHIP_HEMLOCK: return "AMD HEMLOCK";
515 case CHIP_PALM: return "AMD PALM";
516 case CHIP_SUMO: return "AMD SUMO";
517 case CHIP_SUMO2: return "AMD SUMO2";
518 case CHIP_BARTS: return "AMD BARTS";
519 case CHIP_TURKS: return "AMD TURKS";
520 case CHIP_CAICOS: return "AMD CAICOS";
521 case CHIP_CAYMAN: return "AMD CAYMAN";
522 case CHIP_ARUBA: return "AMD ARUBA";
523 default: return "AMD unknown";
524 }
525 }
526
527 static const char* r600_get_name(struct pipe_screen* pscreen)
528 {
529 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
530
531 return r600_get_family_name(rscreen->family);
532 }
533
534 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
535 {
536 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
537 enum radeon_family family = rscreen->family;
538
539 switch (param) {
540 /* Supported features (boolean caps). */
541 case PIPE_CAP_NPOT_TEXTURES:
542 case PIPE_CAP_TWO_SIDED_STENCIL:
543 case PIPE_CAP_ANISOTROPIC_FILTER:
544 case PIPE_CAP_POINT_SPRITE:
545 case PIPE_CAP_OCCLUSION_QUERY:
546 case PIPE_CAP_TEXTURE_SHADOW_MAP:
547 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
548 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
549 case PIPE_CAP_TEXTURE_SWIZZLE:
550 case PIPE_CAP_DEPTH_CLIP_DISABLE:
551 case PIPE_CAP_SHADER_STENCIL_EXPORT:
552 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
553 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
554 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
555 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
556 case PIPE_CAP_SM3:
557 case PIPE_CAP_SEAMLESS_CUBE_MAP:
558 case PIPE_CAP_PRIMITIVE_RESTART:
559 case PIPE_CAP_CONDITIONAL_RENDER:
560 case PIPE_CAP_TEXTURE_BARRIER:
561 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
562 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
563 case PIPE_CAP_TGSI_INSTANCEID:
564 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
565 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
566 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
567 case PIPE_CAP_USER_INDEX_BUFFERS:
568 case PIPE_CAP_USER_CONSTANT_BUFFERS:
569 case PIPE_CAP_COMPUTE:
570 case PIPE_CAP_START_INSTANCE:
571 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
572 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
573 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
574 return 1;
575 case PIPE_CAP_TGSI_TEXCOORD:
576 return 0;
577
578 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
579 return R600_MAP_BUFFER_ALIGNMENT;
580
581 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
582 return 256;
583
584 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
585 return 1;
586
587 case PIPE_CAP_GLSL_FEATURE_LEVEL:
588 return 140;
589
590 case PIPE_CAP_TEXTURE_MULTISAMPLE:
591 return rscreen->msaa_texture_support != MSAA_TEXTURE_SAMPLE_ZERO;
592
593 /* Supported except the original R600. */
594 case PIPE_CAP_INDEP_BLEND_ENABLE:
595 case PIPE_CAP_INDEP_BLEND_FUNC:
596 /* R600 doesn't support per-MRT blends */
597 return family == CHIP_R600 ? 0 : 1;
598
599 /* Supported on Evergreen. */
600 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
601 case PIPE_CAP_CUBE_MAP_ARRAY:
602 return family >= CHIP_CEDAR ? 1 : 0;
603
604 /* Unsupported features. */
605 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
606 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
607 case PIPE_CAP_SCALED_RESOLVE:
608 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
609 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
610 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
611 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
612 case PIPE_CAP_USER_VERTEX_BUFFERS:
613 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
614 return 0;
615
616 /* Stream output. */
617 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
618 return rscreen->has_streamout ? 4 : 0;
619 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
620 return rscreen->has_streamout ? 1 : 0;
621 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
622 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
623 return 32*4;
624
625 /* Texturing. */
626 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
627 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
628 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
629 if (family >= CHIP_CEDAR)
630 return 15;
631 else
632 return 14;
633 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
634 return rscreen->info.drm_minor >= 9 ?
635 (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
636 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
637 return 32;
638
639 /* Render targets. */
640 case PIPE_CAP_MAX_RENDER_TARGETS:
641 /* XXX some r6xx are buggy and can only do 4 */
642 return 8;
643
644 /* Timer queries, present when the clock frequency is non zero. */
645 case PIPE_CAP_QUERY_TIME_ELAPSED:
646 return rscreen->info.r600_clock_crystal_freq != 0;
647 case PIPE_CAP_QUERY_TIMESTAMP:
648 return rscreen->info.drm_minor >= 20 &&
649 rscreen->info.r600_clock_crystal_freq != 0;
650
651 case PIPE_CAP_MIN_TEXEL_OFFSET:
652 return -8;
653
654 case PIPE_CAP_MAX_TEXEL_OFFSET:
655 return 7;
656 }
657 return 0;
658 }
659
660 static float r600_get_paramf(struct pipe_screen* pscreen,
661 enum pipe_capf param)
662 {
663 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
664 enum radeon_family family = rscreen->family;
665
666 switch (param) {
667 case PIPE_CAPF_MAX_LINE_WIDTH:
668 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
669 case PIPE_CAPF_MAX_POINT_WIDTH:
670 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
671 if (family >= CHIP_CEDAR)
672 return 16384.0f;
673 else
674 return 8192.0f;
675 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
676 return 16.0f;
677 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
678 return 16.0f;
679 case PIPE_CAPF_GUARD_BAND_LEFT:
680 case PIPE_CAPF_GUARD_BAND_TOP:
681 case PIPE_CAPF_GUARD_BAND_RIGHT:
682 case PIPE_CAPF_GUARD_BAND_BOTTOM:
683 return 0.0f;
684 }
685 return 0.0f;
686 }
687
688 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
689 {
690 switch(shader)
691 {
692 case PIPE_SHADER_FRAGMENT:
693 case PIPE_SHADER_VERTEX:
694 case PIPE_SHADER_COMPUTE:
695 break;
696 case PIPE_SHADER_GEOMETRY:
697 /* XXX: support and enable geometry programs */
698 return 0;
699 default:
700 /* XXX: support tessellation on Evergreen */
701 return 0;
702 }
703
704 switch (param) {
705 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
706 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
707 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
708 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
709 return 16384;
710 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
711 return 32;
712 case PIPE_SHADER_CAP_MAX_INPUTS:
713 return 32;
714 case PIPE_SHADER_CAP_MAX_TEMPS:
715 return 256; /* Max native temporaries. */
716 case PIPE_SHADER_CAP_MAX_ADDRS:
717 /* XXX Isn't this equal to TEMPS? */
718 return 1; /* Max native address registers */
719 case PIPE_SHADER_CAP_MAX_CONSTS:
720 return R600_MAX_CONST_BUFFER_SIZE;
721 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
722 return R600_MAX_USER_CONST_BUFFERS;
723 case PIPE_SHADER_CAP_MAX_PREDS:
724 return 0; /* nothing uses this */
725 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
726 return 1;
727 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
728 return 0;
729 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
730 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
731 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
732 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
733 return 1;
734 case PIPE_SHADER_CAP_SUBROUTINES:
735 return 0;
736 case PIPE_SHADER_CAP_INTEGERS:
737 return 1;
738 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
739 return 16;
740 case PIPE_SHADER_CAP_PREFERRED_IR:
741 if (shader == PIPE_SHADER_COMPUTE) {
742 return PIPE_SHADER_IR_LLVM;
743 } else {
744 return PIPE_SHADER_IR_TGSI;
745 }
746 }
747 return 0;
748 }
749
750 static int r600_get_video_param(struct pipe_screen *screen,
751 enum pipe_video_profile profile,
752 enum pipe_video_cap param)
753 {
754 switch (param) {
755 case PIPE_VIDEO_CAP_SUPPORTED:
756 return vl_profile_supported(screen, profile);
757 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
758 return 1;
759 case PIPE_VIDEO_CAP_MAX_WIDTH:
760 case PIPE_VIDEO_CAP_MAX_HEIGHT:
761 return vl_video_buffer_max_size(screen);
762 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
763 return PIPE_FORMAT_NV12;
764 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
765 return false;
766 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
767 return false;
768 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
769 return true;
770 default:
771 return 0;
772 }
773 }
774
775 const char * r600_llvm_gpu_string(enum radeon_family family)
776 {
777 const char * gpu_family;
778
779 switch (family) {
780 case CHIP_R600:
781 case CHIP_RV610:
782 case CHIP_RV630:
783 case CHIP_RV620:
784 case CHIP_RV635:
785 case CHIP_RV670:
786 case CHIP_RS780:
787 case CHIP_RS880:
788 gpu_family = "r600";
789 break;
790 case CHIP_RV710:
791 gpu_family = "rv710";
792 break;
793 case CHIP_RV730:
794 gpu_family = "rv730";
795 break;
796 case CHIP_RV740:
797 case CHIP_RV770:
798 gpu_family = "rv770";
799 break;
800 case CHIP_PALM:
801 case CHIP_CEDAR:
802 gpu_family = "cedar";
803 break;
804 case CHIP_SUMO:
805 case CHIP_SUMO2:
806 case CHIP_REDWOOD:
807 gpu_family = "redwood";
808 break;
809 case CHIP_JUNIPER:
810 gpu_family = "juniper";
811 break;
812 case CHIP_HEMLOCK:
813 case CHIP_CYPRESS:
814 gpu_family = "cypress";
815 break;
816 case CHIP_BARTS:
817 gpu_family = "barts";
818 break;
819 case CHIP_TURKS:
820 gpu_family = "turks";
821 break;
822 case CHIP_CAICOS:
823 gpu_family = "caicos";
824 break;
825 case CHIP_CAYMAN:
826 case CHIP_ARUBA:
827 gpu_family = "cayman";
828 break;
829 default:
830 gpu_family = "";
831 fprintf(stderr, "Chip not supported by r600 llvm "
832 "backend, please file a bug at " PACKAGE_BUGREPORT "\n");
833 break;
834 }
835 return gpu_family;
836 }
837
838
839 static int r600_get_compute_param(struct pipe_screen *screen,
840 enum pipe_compute_cap param,
841 void *ret)
842 {
843 struct r600_screen *rscreen = (struct r600_screen *)screen;
844 //TODO: select these params by asic
845 switch (param) {
846 case PIPE_COMPUTE_CAP_IR_TARGET: {
847 const char *gpu = r600_llvm_gpu_string(rscreen->family);
848 if (ret) {
849 sprintf(ret, "%s-r600--", gpu);
850 }
851 return (8 + strlen(gpu)) * sizeof(char);
852 }
853 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
854 if (ret) {
855 uint64_t * grid_dimension = ret;
856 grid_dimension[0] = 3;
857 }
858 return 1 * sizeof(uint64_t);
859
860 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
861 if (ret) {
862 uint64_t * grid_size = ret;
863 grid_size[0] = 65535;
864 grid_size[1] = 65535;
865 grid_size[2] = 1;
866 }
867 return 3 * sizeof(uint64_t) ;
868
869 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
870 if (ret) {
871 uint64_t * block_size = ret;
872 block_size[0] = 256;
873 block_size[1] = 256;
874 block_size[2] = 256;
875 }
876 return 3 * sizeof(uint64_t);
877
878 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
879 if (ret) {
880 uint64_t * max_threads_per_block = ret;
881 *max_threads_per_block = 256;
882 }
883 return sizeof(uint64_t);
884
885 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
886 if (ret) {
887 uint64_t * max_global_size = ret;
888 /* XXX: This is what the proprietary driver reports, we
889 * may want to use a different value. */
890 *max_global_size = 201326592;
891 }
892 return sizeof(uint64_t);
893
894 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
895 if (ret) {
896 uint64_t * max_input_size = ret;
897 *max_input_size = 1024;
898 }
899 return sizeof(uint64_t);
900
901 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
902 if (ret) {
903 uint64_t * max_local_size = ret;
904 /* XXX: This is what the proprietary driver reports, we
905 * may want to use a different value. */
906 *max_local_size = 32768;
907 }
908 return sizeof(uint64_t);
909
910 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
911 if (ret) {
912 uint64_t max_global_size;
913 uint64_t * max_mem_alloc_size = ret;
914 r600_get_compute_param(screen,
915 PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
916 &max_global_size);
917 /* OpenCL requres this value be at least
918 * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
919 * I'm really not sure what value to report here, but
920 * MAX_GLOBAL_SIZE / 4 seems resonable.
921 */
922 *max_mem_alloc_size = max_global_size / 4;
923 }
924 return sizeof(uint64_t);
925
926 default:
927 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
928 return 0;
929 }
930 }
931
932 static void r600_destroy_screen(struct pipe_screen* pscreen)
933 {
934 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
935
936 if (rscreen == NULL)
937 return;
938
939 if (rscreen->global_pool) {
940 compute_memory_pool_delete(rscreen->global_pool);
941 }
942
943 if (rscreen->fences.bo) {
944 struct r600_fence_block *entry, *tmp;
945
946 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
947 LIST_DEL(&entry->head);
948 FREE(entry);
949 }
950
951 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
952 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
953 }
954 #if R600_TRACE_CS
955 if (rscreen->trace_bo) {
956 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
957 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
958 }
959 #endif
960 pipe_mutex_destroy(rscreen->fences.mutex);
961
962 rscreen->ws->destroy(rscreen->ws);
963 FREE(rscreen);
964 }
965
966 static void r600_fence_reference(struct pipe_screen *pscreen,
967 struct pipe_fence_handle **ptr,
968 struct pipe_fence_handle *fence)
969 {
970 struct r600_fence **oldf = (struct r600_fence**)ptr;
971 struct r600_fence *newf = (struct r600_fence*)fence;
972
973 if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
974 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
975 pipe_mutex_lock(rscreen->fences.mutex);
976 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
977 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
978 pipe_mutex_unlock(rscreen->fences.mutex);
979 }
980
981 *ptr = fence;
982 }
983
984 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
985 struct pipe_fence_handle *fence)
986 {
987 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
988 struct r600_fence *rfence = (struct r600_fence*)fence;
989
990 return rscreen->fences.data[rfence->index] != 0;
991 }
992
993 static boolean r600_fence_finish(struct pipe_screen *pscreen,
994 struct pipe_fence_handle *fence,
995 uint64_t timeout)
996 {
997 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
998 struct r600_fence *rfence = (struct r600_fence*)fence;
999 int64_t start_time = 0;
1000 unsigned spins = 0;
1001
1002 if (timeout != PIPE_TIMEOUT_INFINITE) {
1003 start_time = os_time_get();
1004
1005 /* Convert to microseconds. */
1006 timeout /= 1000;
1007 }
1008
1009 while (rscreen->fences.data[rfence->index] == 0) {
1010 /* Special-case infinite timeout - wait for the dummy BO to become idle */
1011 if (timeout == PIPE_TIMEOUT_INFINITE) {
1012 rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
1013 break;
1014 }
1015
1016 /* The dummy BO will be busy until the CS including the fence has completed, or
1017 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
1018 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
1019 break;
1020
1021 if (++spins % 256)
1022 continue;
1023 #ifdef PIPE_OS_UNIX
1024 sched_yield();
1025 #else
1026 os_time_sleep(10);
1027 #endif
1028 if (timeout != PIPE_TIMEOUT_INFINITE &&
1029 os_time_get() - start_time >= timeout) {
1030 break;
1031 }
1032 }
1033
1034 return rscreen->fences.data[rfence->index] != 0;
1035 }
1036
1037 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
1038 {
1039 switch ((tiling_config & 0xe) >> 1) {
1040 case 0:
1041 rscreen->tiling_info.num_channels = 1;
1042 break;
1043 case 1:
1044 rscreen->tiling_info.num_channels = 2;
1045 break;
1046 case 2:
1047 rscreen->tiling_info.num_channels = 4;
1048 break;
1049 case 3:
1050 rscreen->tiling_info.num_channels = 8;
1051 break;
1052 default:
1053 return -EINVAL;
1054 }
1055
1056 switch ((tiling_config & 0x30) >> 4) {
1057 case 0:
1058 rscreen->tiling_info.num_banks = 4;
1059 break;
1060 case 1:
1061 rscreen->tiling_info.num_banks = 8;
1062 break;
1063 default:
1064 return -EINVAL;
1065
1066 }
1067 switch ((tiling_config & 0xc0) >> 6) {
1068 case 0:
1069 rscreen->tiling_info.group_bytes = 256;
1070 break;
1071 case 1:
1072 rscreen->tiling_info.group_bytes = 512;
1073 break;
1074 default:
1075 return -EINVAL;
1076 }
1077 return 0;
1078 }
1079
1080 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
1081 {
1082 switch (tiling_config & 0xf) {
1083 case 0:
1084 rscreen->tiling_info.num_channels = 1;
1085 break;
1086 case 1:
1087 rscreen->tiling_info.num_channels = 2;
1088 break;
1089 case 2:
1090 rscreen->tiling_info.num_channels = 4;
1091 break;
1092 case 3:
1093 rscreen->tiling_info.num_channels = 8;
1094 break;
1095 default:
1096 return -EINVAL;
1097 }
1098
1099 switch ((tiling_config & 0xf0) >> 4) {
1100 case 0:
1101 rscreen->tiling_info.num_banks = 4;
1102 break;
1103 case 1:
1104 rscreen->tiling_info.num_banks = 8;
1105 break;
1106 case 2:
1107 rscreen->tiling_info.num_banks = 16;
1108 break;
1109 default:
1110 return -EINVAL;
1111 }
1112
1113 switch ((tiling_config & 0xf00) >> 8) {
1114 case 0:
1115 rscreen->tiling_info.group_bytes = 256;
1116 break;
1117 case 1:
1118 rscreen->tiling_info.group_bytes = 512;
1119 break;
1120 default:
1121 return -EINVAL;
1122 }
1123 return 0;
1124 }
1125
1126 static int r600_init_tiling(struct r600_screen *rscreen)
1127 {
1128 uint32_t tiling_config = rscreen->info.r600_tiling_config;
1129
1130 /* set default group bytes, overridden by tiling info ioctl */
1131 if (rscreen->chip_class <= R700) {
1132 rscreen->tiling_info.group_bytes = 256;
1133 } else {
1134 rscreen->tiling_info.group_bytes = 512;
1135 }
1136
1137 if (!tiling_config)
1138 return 0;
1139
1140 if (rscreen->chip_class <= R700) {
1141 return r600_interpret_tiling(rscreen, tiling_config);
1142 } else {
1143 return evergreen_interpret_tiling(rscreen, tiling_config);
1144 }
1145 }
1146
1147 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1148 {
1149 struct r600_screen *rscreen = (struct r600_screen*)screen;
1150
1151 return 1000000 * rscreen->ws->query_timestamp(rscreen->ws) /
1152 rscreen->info.r600_clock_crystal_freq;
1153 }
1154
1155 static int r600_get_driver_query_info(struct pipe_screen *screen,
1156 unsigned index,
1157 struct pipe_driver_query_info *info)
1158 {
1159 struct r600_screen *rscreen = (struct r600_screen*)screen;
1160 struct pipe_driver_query_info list[] = {
1161 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
1162 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
1163 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
1164 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE}
1165 };
1166
1167 if (!info)
1168 return Elements(list);
1169
1170 if (index >= Elements(list))
1171 return 0;
1172
1173 *info = list[index];
1174 return 1;
1175 }
1176
1177 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
1178 {
1179 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
1180
1181 if (rscreen == NULL) {
1182 return NULL;
1183 }
1184
1185 rscreen->ws = ws;
1186 ws->query_info(ws, &rscreen->info);
1187
1188 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", debug_options, 0);
1189 if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
1190 rscreen->debug_flags |= DBG_COMPUTE;
1191 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
1192 rscreen->debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
1193 if (!debug_get_bool_option("R600_HYPERZ", TRUE))
1194 rscreen->debug_flags |= DBG_NO_HYPERZ;
1195 if (!debug_get_bool_option("R600_LLVM", TRUE))
1196 rscreen->debug_flags |= DBG_NO_LLVM;
1197 if (debug_get_bool_option("R600_PRINT_TEXDEPTH", FALSE))
1198 rscreen->debug_flags |= DBG_TEX_DEPTH;
1199 rscreen->family = rscreen->info.family;
1200 rscreen->chip_class = rscreen->info.chip_class;
1201
1202 if (rscreen->family == CHIP_UNKNOWN) {
1203 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
1204 FREE(rscreen);
1205 return NULL;
1206 }
1207
1208 /* Figure out streamout kernel support. */
1209 switch (rscreen->chip_class) {
1210 case R600:
1211 if (rscreen->family < CHIP_RS780) {
1212 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
1213 } else {
1214 rscreen->has_streamout = rscreen->info.drm_minor >= 23;
1215 }
1216 break;
1217 case R700:
1218 rscreen->has_streamout = rscreen->info.drm_minor >= 17;
1219 break;
1220 case EVERGREEN:
1221 case CAYMAN:
1222 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
1223 break;
1224 default:
1225 rscreen->has_streamout = FALSE;
1226 break;
1227 }
1228
1229 /* MSAA support. */
1230 switch (rscreen->chip_class) {
1231 case R600:
1232 case R700:
1233 rscreen->has_msaa = rscreen->info.drm_minor >= 22;
1234 rscreen->msaa_texture_support = MSAA_TEXTURE_DECOMPRESSED;
1235 break;
1236 case EVERGREEN:
1237 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
1238 rscreen->msaa_texture_support =
1239 rscreen->info.drm_minor >= 24 ? MSAA_TEXTURE_COMPRESSED :
1240 MSAA_TEXTURE_DECOMPRESSED;
1241 break;
1242 case CAYMAN:
1243 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
1244 /* We should be able to read compressed MSAA textures, but it doesn't work. */
1245 rscreen->msaa_texture_support = MSAA_TEXTURE_SAMPLE_ZERO;
1246 break;
1247 default:
1248 rscreen->has_msaa = FALSE;
1249 rscreen->msaa_texture_support = 0;
1250 break;
1251 }
1252
1253 rscreen->has_cp_dma = rscreen->info.drm_minor >= 27 &&
1254 !(rscreen->debug_flags & DBG_NO_CP_DMA);
1255
1256 if (r600_init_tiling(rscreen)) {
1257 FREE(rscreen);
1258 return NULL;
1259 }
1260
1261 rscreen->screen.destroy = r600_destroy_screen;
1262 rscreen->screen.get_name = r600_get_name;
1263 rscreen->screen.get_vendor = r600_get_vendor;
1264 rscreen->screen.get_param = r600_get_param;
1265 rscreen->screen.get_shader_param = r600_get_shader_param;
1266 rscreen->screen.get_paramf = r600_get_paramf;
1267 rscreen->screen.get_compute_param = r600_get_compute_param;
1268 rscreen->screen.get_timestamp = r600_get_timestamp;
1269
1270 if (rscreen->chip_class >= EVERGREEN) {
1271 rscreen->screen.is_format_supported = evergreen_is_format_supported;
1272 rscreen->dma_blit = &evergreen_dma_blit;
1273 } else {
1274 rscreen->screen.is_format_supported = r600_is_format_supported;
1275 rscreen->dma_blit = &r600_dma_blit;
1276 }
1277 rscreen->screen.context_create = r600_create_context;
1278 rscreen->screen.fence_reference = r600_fence_reference;
1279 rscreen->screen.fence_signalled = r600_fence_signalled;
1280 rscreen->screen.fence_finish = r600_fence_finish;
1281 rscreen->screen.get_driver_query_info = r600_get_driver_query_info;
1282
1283 if (rscreen->info.has_uvd) {
1284 rscreen->screen.get_video_param = ruvd_get_video_param;
1285 rscreen->screen.is_video_format_supported = ruvd_is_format_supported;
1286 } else {
1287 rscreen->screen.get_video_param = r600_get_video_param;
1288 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
1289 }
1290
1291 r600_init_screen_resource_functions(&rscreen->screen);
1292
1293 util_format_s3tc_init();
1294
1295 rscreen->fences.bo = NULL;
1296 rscreen->fences.data = NULL;
1297 rscreen->fences.next_index = 0;
1298 LIST_INITHEAD(&rscreen->fences.pool);
1299 LIST_INITHEAD(&rscreen->fences.blocks);
1300 pipe_mutex_init(rscreen->fences.mutex);
1301
1302 rscreen->global_pool = compute_memory_pool_new(rscreen);
1303
1304 #if R600_TRACE_CS
1305 rscreen->cs_count = 0;
1306 if (rscreen->info.drm_minor >= 28) {
1307 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->screen,
1308 PIPE_BIND_CUSTOM,
1309 PIPE_USAGE_STAGING,
1310 4096);
1311 if (rscreen->trace_bo) {
1312 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
1313 PIPE_TRANSFER_UNSYNCHRONIZED);
1314 }
1315 }
1316 #endif
1317
1318 return &rscreen->screen;
1319 }