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[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_pipe.h"
24 #include "r600_public.h"
25 #include "r600_isa.h"
26 #include "evergreen_compute.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include "pipe/p_shader_tokens.h"
31 #include "util/u_blitter.h"
32 #include "util/u_debug.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_memory.h"
35 #include "util/u_simple_shaders.h"
36 #include "util/u_upload_mgr.h"
37 #include "util/u_math.h"
38 #include "vl/vl_decoder.h"
39 #include "vl/vl_video_buffer.h"
40 #include "os/os_time.h"
41
42 static const struct debug_named_value debug_options[] = {
43 /* logging */
44 { "texdepth", DBG_TEX_DEPTH, "Print texture depth info" },
45 { "compute", DBG_COMPUTE, "Print compute info" },
46
47 /* shaders */
48 { "fs", DBG_FS, "Print fetch shaders" },
49 { "vs", DBG_VS, "Print vertex shaders" },
50 { "gs", DBG_GS, "Print geometry shaders" },
51 { "ps", DBG_PS, "Print pixel shaders" },
52 { "cs", DBG_CS, "Print compute shaders" },
53
54 /* features */
55 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
56 #if defined(R600_USE_LLVM)
57 { "nollvm", DBG_NO_LLVM, "Disable the LLVM shader compiler" },
58 #endif
59 { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
60 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
61 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
62 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
63
64 DEBUG_NAMED_VALUE_END /* must be last */
65 };
66
67 /*
68 * pipe_context
69 */
70 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
71 {
72 struct r600_screen *rscreen = rctx->screen;
73 struct r600_fence *fence = NULL;
74
75 pipe_mutex_lock(rscreen->fences.mutex);
76
77 if (!rscreen->fences.bo) {
78 /* Create the shared buffer object */
79 rscreen->fences.bo = (struct r600_resource*)
80 pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
81 PIPE_USAGE_STAGING, 4096);
82 if (!rscreen->fences.bo) {
83 R600_ERR("r600: failed to create bo for fence objects\n");
84 goto out;
85 }
86 rscreen->fences.data = r600_buffer_mmap_sync_with_rings(rctx, rscreen->fences.bo, PIPE_TRANSFER_READ_WRITE);
87 }
88
89 if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
90 struct r600_fence *entry;
91
92 /* Try to find a freed fence that has been signalled */
93 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
94 if (rscreen->fences.data[entry->index] != 0) {
95 LIST_DELINIT(&entry->head);
96 fence = entry;
97 break;
98 }
99 }
100 }
101
102 if (!fence) {
103 /* Allocate a new fence */
104 struct r600_fence_block *block;
105 unsigned index;
106
107 if ((rscreen->fences.next_index + 1) >= 1024) {
108 R600_ERR("r600: too many concurrent fences\n");
109 goto out;
110 }
111
112 index = rscreen->fences.next_index++;
113
114 if (!(index % FENCE_BLOCK_SIZE)) {
115 /* Allocate a new block */
116 block = CALLOC_STRUCT(r600_fence_block);
117 if (block == NULL)
118 goto out;
119
120 LIST_ADD(&block->head, &rscreen->fences.blocks);
121 } else {
122 block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
123 }
124
125 fence = &block->fences[index % FENCE_BLOCK_SIZE];
126 fence->index = index;
127 }
128
129 pipe_reference_init(&fence->reference, 1);
130
131 rscreen->fences.data[fence->index] = 0;
132 r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
133
134 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
135 fence->sleep_bo = (struct r600_resource*)
136 pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
137 PIPE_USAGE_STAGING, 1);
138 /* Add the fence as a dummy relocation. */
139 r600_context_bo_reloc(rctx, &rctx->rings.gfx, fence->sleep_bo, RADEON_USAGE_READWRITE);
140
141 out:
142 pipe_mutex_unlock(rscreen->fences.mutex);
143 return fence;
144 }
145
146 static void r600_flush(struct pipe_context *ctx, unsigned flags)
147 {
148 struct r600_context *rctx = (struct r600_context *)ctx;
149 struct pipe_query *render_cond = NULL;
150 unsigned render_cond_mode = 0;
151
152 rctx->rings.gfx.flushing = true;
153 /* Disable render condition. */
154 if (rctx->current_render_cond) {
155 render_cond = rctx->current_render_cond;
156 render_cond_mode = rctx->current_render_cond_mode;
157 ctx->render_condition(ctx, NULL, 0);
158 }
159
160 r600_context_flush(rctx, flags);
161 rctx->rings.gfx.flushing = false;
162 r600_begin_new_cs(rctx);
163
164 /* Re-enable render condition. */
165 if (render_cond) {
166 ctx->render_condition(ctx, render_cond, render_cond_mode);
167 }
168 }
169
170 static void r600_flush_from_st(struct pipe_context *ctx,
171 struct pipe_fence_handle **fence,
172 enum pipe_flush_flags flags)
173 {
174 struct r600_context *rctx = (struct r600_context *)ctx;
175 struct r600_fence **rfence = (struct r600_fence**)fence;
176 unsigned fflags;
177
178 fflags = flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0;
179 if (rfence) {
180 *rfence = r600_create_fence(rctx);
181 }
182 /* flush gfx & dma ring, order does not matter as only one can be live */
183 if (rctx->rings.dma.cs) {
184 rctx->rings.dma.flush(rctx, fflags);
185 }
186 rctx->rings.gfx.flush(rctx, fflags);
187 }
188
189 static void r600_flush_gfx_ring(void *ctx, unsigned flags)
190 {
191 r600_flush((struct pipe_context*)ctx, flags);
192 }
193
194 static void r600_flush_dma_ring(void *ctx, unsigned flags)
195 {
196 struct r600_context *rctx = (struct r600_context *)ctx;
197 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
198 unsigned padding_dw, i;
199
200 if (!cs->cdw) {
201 return;
202 }
203
204 /* Pad the DMA CS to a multiple of 8 dwords. */
205 padding_dw = 8 - cs->cdw % 8;
206 if (padding_dw < 8) {
207 for (i = 0; i < padding_dw; i++) {
208 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
209 }
210 }
211
212 rctx->rings.dma.flushing = true;
213 rctx->ws->cs_flush(cs, flags);
214 rctx->rings.dma.flushing = false;
215 }
216
217 boolean r600_rings_is_buffer_referenced(struct r600_context *ctx,
218 struct radeon_winsys_cs_handle *buf,
219 enum radeon_bo_usage usage)
220 {
221 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, buf, usage)) {
222 return TRUE;
223 }
224 if (ctx->rings.dma.cs) {
225 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, buf, usage)) {
226 return TRUE;
227 }
228 }
229 return FALSE;
230 }
231
232 void *r600_buffer_mmap_sync_with_rings(struct r600_context *ctx,
233 struct r600_resource *resource,
234 unsigned usage)
235 {
236 enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
237 unsigned flags = 0;
238 bool sync_flush = TRUE;
239
240 if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
241 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
242 }
243
244 if (!(usage & PIPE_TRANSFER_WRITE)) {
245 /* have to wait for pending read */
246 rusage = RADEON_USAGE_WRITE;
247 }
248 if (usage & PIPE_TRANSFER_DONTBLOCK) {
249 flags |= RADEON_FLUSH_ASYNC;
250 }
251
252 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, resource->cs_buf, rusage) && ctx->rings.gfx.cs->cdw) {
253 ctx->rings.gfx.flush(ctx, flags);
254 if (usage & PIPE_TRANSFER_DONTBLOCK) {
255 return NULL;
256 }
257 }
258 if (ctx->rings.dma.cs) {
259 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, resource->cs_buf, rusage) && ctx->rings.dma.cs->cdw) {
260 ctx->rings.dma.flush(ctx, flags);
261 if (usage & PIPE_TRANSFER_DONTBLOCK) {
262 return NULL;
263 }
264 }
265 }
266
267 if (usage & PIPE_TRANSFER_DONTBLOCK) {
268 if (ctx->ws->buffer_is_busy(resource->buf, rusage)) {
269 return NULL;
270 }
271 }
272 if (sync_flush) {
273 /* Try to avoid busy-waiting in radeon_bo_wait. */
274 ctx->ws->cs_sync_flush(ctx->rings.gfx.cs);
275 if (ctx->rings.dma.cs) {
276 ctx->ws->cs_sync_flush(ctx->rings.dma.cs);
277 }
278 }
279 ctx->ws->buffer_wait(resource->buf, rusage);
280
281 /* at this point everything is synchronized */
282 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage | PIPE_TRANSFER_UNSYNCHRONIZED);
283 }
284
285 static void r600_flush_from_winsys(void *ctx, unsigned flags)
286 {
287 struct r600_context *rctx = (struct r600_context *)ctx;
288
289 rctx->rings.gfx.flush(rctx, flags);
290 }
291
292 static void r600_flush_dma_from_winsys(void *ctx, unsigned flags)
293 {
294 struct r600_context *rctx = (struct r600_context *)ctx;
295
296 rctx->rings.dma.flush(rctx, flags);
297 }
298
299 static void r600_destroy_context(struct pipe_context *context)
300 {
301 struct r600_context *rctx = (struct r600_context *)context;
302
303 r600_isa_destroy(rctx->isa);
304
305 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
306 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
307
308 if (rctx->dummy_pixel_shader) {
309 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
310 }
311 if (rctx->custom_dsa_flush) {
312 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
313 }
314 if (rctx->custom_blend_resolve) {
315 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve);
316 }
317 if (rctx->custom_blend_decompress) {
318 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_decompress);
319 }
320 if (rctx->custom_blend_fmask_decompress) {
321 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_fmask_decompress);
322 }
323 util_unreference_framebuffer_state(&rctx->framebuffer.state);
324
325 if (rctx->blitter) {
326 util_blitter_destroy(rctx->blitter);
327 }
328 if (rctx->uploader) {
329 u_upload_destroy(rctx->uploader);
330 }
331 if (rctx->allocator_so_filled_size) {
332 u_suballocator_destroy(rctx->allocator_so_filled_size);
333 }
334 if (rctx->allocator_fetch_shader) {
335 u_suballocator_destroy(rctx->allocator_fetch_shader);
336 }
337 util_slab_destroy(&rctx->pool_transfers);
338
339 r600_release_command_buffer(&rctx->start_cs_cmd);
340
341 if (rctx->rings.gfx.cs) {
342 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
343 }
344 if (rctx->rings.dma.cs) {
345 rctx->ws->cs_destroy(rctx->rings.dma.cs);
346 }
347
348 FREE(rctx);
349 }
350
351 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
352 {
353 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
354 struct r600_screen* rscreen = (struct r600_screen *)screen;
355
356 if (rctx == NULL)
357 return NULL;
358
359 util_slab_create(&rctx->pool_transfers,
360 sizeof(struct r600_transfer), 64,
361 UTIL_SLAB_SINGLETHREADED);
362
363 rctx->context.screen = screen;
364 rctx->context.priv = priv;
365 rctx->context.destroy = r600_destroy_context;
366 rctx->context.flush = r600_flush_from_st;
367
368 /* Easy accessing of screen/winsys. */
369 rctx->screen = rscreen;
370 rctx->ws = rscreen->ws;
371 rctx->family = rscreen->family;
372 rctx->chip_class = rscreen->chip_class;
373 rctx->keep_tiling_flags = rscreen->info.drm_minor >= 12;
374
375 LIST_INITHEAD(&rctx->active_nontimer_queries);
376
377 r600_init_blit_functions(rctx);
378 r600_init_query_functions(rctx);
379 r600_init_context_resource_functions(rctx);
380 r600_init_surface_functions(rctx);
381
382 rctx->context.create_video_decoder = vl_create_decoder;
383 rctx->context.create_video_buffer = vl_video_buffer_create;
384
385 r600_init_common_state_functions(rctx);
386
387 switch (rctx->chip_class) {
388 case R600:
389 case R700:
390 r600_init_state_functions(rctx);
391 r600_init_atom_start_cs(rctx);
392 rctx->max_db = 4;
393 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
394 rctx->custom_blend_resolve = rctx->chip_class == R700 ? r700_create_resolve_blend(rctx)
395 : r600_create_resolve_blend(rctx);
396 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
397 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
398 rctx->family == CHIP_RV620 ||
399 rctx->family == CHIP_RS780 ||
400 rctx->family == CHIP_RS880 ||
401 rctx->family == CHIP_RV710);
402 break;
403 case EVERGREEN:
404 case CAYMAN:
405 evergreen_init_state_functions(rctx);
406 evergreen_init_atom_start_cs(rctx);
407 evergreen_init_atom_start_compute_cs(rctx);
408 rctx->max_db = 8;
409 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
410 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
411 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
412 rctx->custom_blend_fmask_decompress = evergreen_create_fmask_decompress_blend(rctx);
413 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
414 rctx->family == CHIP_PALM ||
415 rctx->family == CHIP_SUMO ||
416 rctx->family == CHIP_SUMO2 ||
417 rctx->family == CHIP_CAICOS ||
418 rctx->family == CHIP_CAYMAN ||
419 rctx->family == CHIP_ARUBA);
420 break;
421 default:
422 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
423 goto fail;
424 }
425
426 rctx->rings.gfx.cs = rctx->ws->cs_create(rctx->ws, RING_GFX);
427 rctx->rings.gfx.flush = r600_flush_gfx_ring;
428 rctx->ws->cs_set_flush_callback(rctx->rings.gfx.cs, r600_flush_from_winsys, rctx);
429 rctx->rings.gfx.flushing = false;
430
431 rctx->rings.dma.cs = NULL;
432 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
433 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA);
434 rctx->rings.dma.flush = r600_flush_dma_ring;
435 rctx->ws->cs_set_flush_callback(rctx->rings.dma.cs, r600_flush_dma_from_winsys, rctx);
436 rctx->rings.dma.flushing = false;
437 }
438
439 rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
440 PIPE_BIND_INDEX_BUFFER |
441 PIPE_BIND_CONSTANT_BUFFER);
442 if (!rctx->uploader)
443 goto fail;
444
445 rctx->allocator_fetch_shader = u_suballocator_create(&rctx->context, 64 * 1024, 256,
446 0, PIPE_USAGE_STATIC, FALSE);
447 if (!rctx->allocator_fetch_shader)
448 goto fail;
449
450 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->context, 4096, 4,
451 0, PIPE_USAGE_STATIC, TRUE);
452 if (!rctx->allocator_so_filled_size)
453 goto fail;
454
455 rctx->isa = calloc(1, sizeof(struct r600_isa));
456 if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
457 goto fail;
458
459 rctx->blitter = util_blitter_create(&rctx->context);
460 if (rctx->blitter == NULL)
461 goto fail;
462 util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
463 rctx->blitter->draw_rectangle = r600_draw_rectangle;
464
465 r600_begin_new_cs(rctx);
466 r600_get_backend_mask(rctx); /* this emits commands and must be last */
467
468 rctx->dummy_pixel_shader =
469 util_make_fragment_cloneinput_shader(&rctx->context, 0,
470 TGSI_SEMANTIC_GENERIC,
471 TGSI_INTERPOLATE_CONSTANT);
472 rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
473
474 return &rctx->context;
475
476 fail:
477 r600_destroy_context(&rctx->context);
478 return NULL;
479 }
480
481 /*
482 * pipe_screen
483 */
484 static const char* r600_get_vendor(struct pipe_screen* pscreen)
485 {
486 return "X.Org";
487 }
488
489 static const char *r600_get_family_name(enum radeon_family family)
490 {
491 switch(family) {
492 case CHIP_R600: return "AMD R600";
493 case CHIP_RV610: return "AMD RV610";
494 case CHIP_RV630: return "AMD RV630";
495 case CHIP_RV670: return "AMD RV670";
496 case CHIP_RV620: return "AMD RV620";
497 case CHIP_RV635: return "AMD RV635";
498 case CHIP_RS780: return "AMD RS780";
499 case CHIP_RS880: return "AMD RS880";
500 case CHIP_RV770: return "AMD RV770";
501 case CHIP_RV730: return "AMD RV730";
502 case CHIP_RV710: return "AMD RV710";
503 case CHIP_RV740: return "AMD RV740";
504 case CHIP_CEDAR: return "AMD CEDAR";
505 case CHIP_REDWOOD: return "AMD REDWOOD";
506 case CHIP_JUNIPER: return "AMD JUNIPER";
507 case CHIP_CYPRESS: return "AMD CYPRESS";
508 case CHIP_HEMLOCK: return "AMD HEMLOCK";
509 case CHIP_PALM: return "AMD PALM";
510 case CHIP_SUMO: return "AMD SUMO";
511 case CHIP_SUMO2: return "AMD SUMO2";
512 case CHIP_BARTS: return "AMD BARTS";
513 case CHIP_TURKS: return "AMD TURKS";
514 case CHIP_CAICOS: return "AMD CAICOS";
515 case CHIP_CAYMAN: return "AMD CAYMAN";
516 case CHIP_ARUBA: return "AMD ARUBA";
517 default: return "AMD unknown";
518 }
519 }
520
521 static const char* r600_get_name(struct pipe_screen* pscreen)
522 {
523 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
524
525 return r600_get_family_name(rscreen->family);
526 }
527
528 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
529 {
530 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
531 enum radeon_family family = rscreen->family;
532
533 switch (param) {
534 /* Supported features (boolean caps). */
535 case PIPE_CAP_NPOT_TEXTURES:
536 case PIPE_CAP_TWO_SIDED_STENCIL:
537 case PIPE_CAP_ANISOTROPIC_FILTER:
538 case PIPE_CAP_POINT_SPRITE:
539 case PIPE_CAP_OCCLUSION_QUERY:
540 case PIPE_CAP_TEXTURE_SHADOW_MAP:
541 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
542 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
543 case PIPE_CAP_TEXTURE_SWIZZLE:
544 case PIPE_CAP_DEPTH_CLIP_DISABLE:
545 case PIPE_CAP_SHADER_STENCIL_EXPORT:
546 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
547 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
548 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
549 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
550 case PIPE_CAP_SM3:
551 case PIPE_CAP_SEAMLESS_CUBE_MAP:
552 case PIPE_CAP_PRIMITIVE_RESTART:
553 case PIPE_CAP_CONDITIONAL_RENDER:
554 case PIPE_CAP_TEXTURE_BARRIER:
555 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
556 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
557 case PIPE_CAP_TGSI_INSTANCEID:
558 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
559 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
560 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
561 case PIPE_CAP_USER_INDEX_BUFFERS:
562 case PIPE_CAP_USER_CONSTANT_BUFFERS:
563 case PIPE_CAP_COMPUTE:
564 case PIPE_CAP_START_INSTANCE:
565 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
566 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
567 return 1;
568
569 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
570 return R600_MAP_BUFFER_ALIGNMENT;
571
572 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
573 return 256;
574
575 case PIPE_CAP_GLSL_FEATURE_LEVEL:
576 return 140;
577
578 case PIPE_CAP_TEXTURE_MULTISAMPLE:
579 return rscreen->msaa_texture_support != MSAA_TEXTURE_SAMPLE_ZERO;
580
581 /* Supported except the original R600. */
582 case PIPE_CAP_INDEP_BLEND_ENABLE:
583 case PIPE_CAP_INDEP_BLEND_FUNC:
584 /* R600 doesn't support per-MRT blends */
585 return family == CHIP_R600 ? 0 : 1;
586
587 /* Supported on Evergreen. */
588 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
589 case PIPE_CAP_CUBE_MAP_ARRAY:
590 return family >= CHIP_CEDAR ? 1 : 0;
591
592 /* Unsupported features. */
593 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
594 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
595 case PIPE_CAP_SCALED_RESOLVE:
596 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
597 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
598 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
599 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
600 case PIPE_CAP_USER_VERTEX_BUFFERS:
601 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
602 return 0;
603
604 /* Stream output. */
605 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
606 return rscreen->has_streamout ? 4 : 0;
607 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
608 return rscreen->has_streamout ? 1 : 0;
609 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
610 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
611 return 32*4;
612
613 /* Texturing. */
614 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
615 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
616 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
617 if (family >= CHIP_CEDAR)
618 return 15;
619 else
620 return 14;
621 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
622 return rscreen->info.drm_minor >= 9 ?
623 (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
624 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
625 return 32;
626
627 /* Render targets. */
628 case PIPE_CAP_MAX_RENDER_TARGETS:
629 /* XXX some r6xx are buggy and can only do 4 */
630 return 8;
631
632 /* Timer queries, present when the clock frequency is non zero. */
633 case PIPE_CAP_QUERY_TIME_ELAPSED:
634 return rscreen->info.r600_clock_crystal_freq != 0;
635 case PIPE_CAP_QUERY_TIMESTAMP:
636 return rscreen->info.drm_minor >= 20 &&
637 rscreen->info.r600_clock_crystal_freq != 0;
638
639 case PIPE_CAP_MIN_TEXEL_OFFSET:
640 return -8;
641
642 case PIPE_CAP_MAX_TEXEL_OFFSET:
643 return 7;
644 }
645 return 0;
646 }
647
648 static float r600_get_paramf(struct pipe_screen* pscreen,
649 enum pipe_capf param)
650 {
651 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
652 enum radeon_family family = rscreen->family;
653
654 switch (param) {
655 case PIPE_CAPF_MAX_LINE_WIDTH:
656 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
657 case PIPE_CAPF_MAX_POINT_WIDTH:
658 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
659 if (family >= CHIP_CEDAR)
660 return 16384.0f;
661 else
662 return 8192.0f;
663 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
664 return 16.0f;
665 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
666 return 16.0f;
667 case PIPE_CAPF_GUARD_BAND_LEFT:
668 case PIPE_CAPF_GUARD_BAND_TOP:
669 case PIPE_CAPF_GUARD_BAND_RIGHT:
670 case PIPE_CAPF_GUARD_BAND_BOTTOM:
671 return 0.0f;
672 }
673 return 0.0f;
674 }
675
676 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
677 {
678 switch(shader)
679 {
680 case PIPE_SHADER_FRAGMENT:
681 case PIPE_SHADER_VERTEX:
682 case PIPE_SHADER_COMPUTE:
683 break;
684 case PIPE_SHADER_GEOMETRY:
685 /* XXX: support and enable geometry programs */
686 return 0;
687 default:
688 /* XXX: support tessellation on Evergreen */
689 return 0;
690 }
691
692 switch (param) {
693 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
694 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
695 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
696 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
697 return 16384;
698 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
699 return 32;
700 case PIPE_SHADER_CAP_MAX_INPUTS:
701 return 32;
702 case PIPE_SHADER_CAP_MAX_TEMPS:
703 return 256; /* Max native temporaries. */
704 case PIPE_SHADER_CAP_MAX_ADDRS:
705 /* XXX Isn't this equal to TEMPS? */
706 return 1; /* Max native address registers */
707 case PIPE_SHADER_CAP_MAX_CONSTS:
708 return R600_MAX_CONST_BUFFER_SIZE;
709 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
710 return R600_MAX_USER_CONST_BUFFERS;
711 case PIPE_SHADER_CAP_MAX_PREDS:
712 return 0; /* nothing uses this */
713 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
714 return 1;
715 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
716 return 0;
717 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
718 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
719 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
720 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
721 return 1;
722 case PIPE_SHADER_CAP_SUBROUTINES:
723 return 0;
724 case PIPE_SHADER_CAP_INTEGERS:
725 return 1;
726 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
727 return 16;
728 case PIPE_SHADER_CAP_PREFERRED_IR:
729 if (shader == PIPE_SHADER_COMPUTE) {
730 return PIPE_SHADER_IR_LLVM;
731 } else {
732 return PIPE_SHADER_IR_TGSI;
733 }
734 }
735 return 0;
736 }
737
738 static int r600_get_video_param(struct pipe_screen *screen,
739 enum pipe_video_profile profile,
740 enum pipe_video_cap param)
741 {
742 switch (param) {
743 case PIPE_VIDEO_CAP_SUPPORTED:
744 return vl_profile_supported(screen, profile);
745 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
746 return 1;
747 case PIPE_VIDEO_CAP_MAX_WIDTH:
748 case PIPE_VIDEO_CAP_MAX_HEIGHT:
749 return vl_video_buffer_max_size(screen);
750 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
751 return PIPE_FORMAT_NV12;
752 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
753 return false;
754 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
755 return false;
756 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
757 return true;
758 default:
759 return 0;
760 }
761 }
762
763 static int r600_get_compute_param(struct pipe_screen *screen,
764 enum pipe_compute_cap param,
765 void *ret)
766 {
767 //TODO: select these params by asic
768 switch (param) {
769 case PIPE_COMPUTE_CAP_IR_TARGET:
770 if (ret) {
771 strcpy(ret, "r600--");
772 }
773 return 7 * sizeof(char);
774
775 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
776 if (ret) {
777 uint64_t * grid_dimension = ret;
778 grid_dimension[0] = 3;
779 }
780 return 1 * sizeof(uint64_t);
781
782 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
783 if (ret) {
784 uint64_t * grid_size = ret;
785 grid_size[0] = 65535;
786 grid_size[1] = 65535;
787 grid_size[2] = 1;
788 }
789 return 3 * sizeof(uint64_t) ;
790
791 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
792 if (ret) {
793 uint64_t * block_size = ret;
794 block_size[0] = 256;
795 block_size[1] = 256;
796 block_size[2] = 256;
797 }
798 return 3 * sizeof(uint64_t);
799
800 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
801 if (ret) {
802 uint64_t * max_threads_per_block = ret;
803 *max_threads_per_block = 256;
804 }
805 return sizeof(uint64_t);
806
807 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
808 if (ret) {
809 uint64_t * max_global_size = ret;
810 /* XXX: This is what the proprietary driver reports, we
811 * may want to use a different value. */
812 *max_global_size = 201326592;
813 }
814 return sizeof(uint64_t);
815
816 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
817 if (ret) {
818 uint64_t * max_input_size = ret;
819 *max_input_size = 1024;
820 }
821 return sizeof(uint64_t);
822
823 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
824 if (ret) {
825 uint64_t * max_local_size = ret;
826 /* XXX: This is what the proprietary driver reports, we
827 * may want to use a different value. */
828 *max_local_size = 32768;
829 }
830 return sizeof(uint64_t);
831
832 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
833 if (ret) {
834 uint64_t max_global_size;
835 uint64_t * max_mem_alloc_size = ret;
836 r600_get_compute_param(screen,
837 PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
838 &max_global_size);
839 /* OpenCL requres this value be at least
840 * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
841 * I'm really not sure what value to report here, but
842 * MAX_GLOBAL_SIZE / 4 seems resonable.
843 */
844 *max_mem_alloc_size = max_global_size / 4;
845 }
846 return sizeof(uint64_t);
847
848 default:
849 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
850 return 0;
851 }
852 }
853
854 static void r600_destroy_screen(struct pipe_screen* pscreen)
855 {
856 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
857
858 if (rscreen == NULL)
859 return;
860
861 if (rscreen->global_pool) {
862 compute_memory_pool_delete(rscreen->global_pool);
863 }
864
865 if (rscreen->fences.bo) {
866 struct r600_fence_block *entry, *tmp;
867
868 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
869 LIST_DEL(&entry->head);
870 FREE(entry);
871 }
872
873 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
874 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
875 }
876 #if R600_TRACE_CS
877 if (rscreen->trace_bo) {
878 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
879 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
880 }
881 #endif
882 pipe_mutex_destroy(rscreen->fences.mutex);
883
884 rscreen->ws->destroy(rscreen->ws);
885 FREE(rscreen);
886 }
887
888 static void r600_fence_reference(struct pipe_screen *pscreen,
889 struct pipe_fence_handle **ptr,
890 struct pipe_fence_handle *fence)
891 {
892 struct r600_fence **oldf = (struct r600_fence**)ptr;
893 struct r600_fence *newf = (struct r600_fence*)fence;
894
895 if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
896 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
897 pipe_mutex_lock(rscreen->fences.mutex);
898 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
899 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
900 pipe_mutex_unlock(rscreen->fences.mutex);
901 }
902
903 *ptr = fence;
904 }
905
906 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
907 struct pipe_fence_handle *fence)
908 {
909 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
910 struct r600_fence *rfence = (struct r600_fence*)fence;
911
912 return rscreen->fences.data[rfence->index] != 0;
913 }
914
915 static boolean r600_fence_finish(struct pipe_screen *pscreen,
916 struct pipe_fence_handle *fence,
917 uint64_t timeout)
918 {
919 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
920 struct r600_fence *rfence = (struct r600_fence*)fence;
921 int64_t start_time = 0;
922 unsigned spins = 0;
923
924 if (timeout != PIPE_TIMEOUT_INFINITE) {
925 start_time = os_time_get();
926
927 /* Convert to microseconds. */
928 timeout /= 1000;
929 }
930
931 while (rscreen->fences.data[rfence->index] == 0) {
932 /* Special-case infinite timeout - wait for the dummy BO to become idle */
933 if (timeout == PIPE_TIMEOUT_INFINITE) {
934 rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
935 break;
936 }
937
938 /* The dummy BO will be busy until the CS including the fence has completed, or
939 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
940 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
941 break;
942
943 if (++spins % 256)
944 continue;
945 #ifdef PIPE_OS_UNIX
946 sched_yield();
947 #else
948 os_time_sleep(10);
949 #endif
950 if (timeout != PIPE_TIMEOUT_INFINITE &&
951 os_time_get() - start_time >= timeout) {
952 break;
953 }
954 }
955
956 return rscreen->fences.data[rfence->index] != 0;
957 }
958
959 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
960 {
961 switch ((tiling_config & 0xe) >> 1) {
962 case 0:
963 rscreen->tiling_info.num_channels = 1;
964 break;
965 case 1:
966 rscreen->tiling_info.num_channels = 2;
967 break;
968 case 2:
969 rscreen->tiling_info.num_channels = 4;
970 break;
971 case 3:
972 rscreen->tiling_info.num_channels = 8;
973 break;
974 default:
975 return -EINVAL;
976 }
977
978 switch ((tiling_config & 0x30) >> 4) {
979 case 0:
980 rscreen->tiling_info.num_banks = 4;
981 break;
982 case 1:
983 rscreen->tiling_info.num_banks = 8;
984 break;
985 default:
986 return -EINVAL;
987
988 }
989 switch ((tiling_config & 0xc0) >> 6) {
990 case 0:
991 rscreen->tiling_info.group_bytes = 256;
992 break;
993 case 1:
994 rscreen->tiling_info.group_bytes = 512;
995 break;
996 default:
997 return -EINVAL;
998 }
999 return 0;
1000 }
1001
1002 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
1003 {
1004 switch (tiling_config & 0xf) {
1005 case 0:
1006 rscreen->tiling_info.num_channels = 1;
1007 break;
1008 case 1:
1009 rscreen->tiling_info.num_channels = 2;
1010 break;
1011 case 2:
1012 rscreen->tiling_info.num_channels = 4;
1013 break;
1014 case 3:
1015 rscreen->tiling_info.num_channels = 8;
1016 break;
1017 default:
1018 return -EINVAL;
1019 }
1020
1021 switch ((tiling_config & 0xf0) >> 4) {
1022 case 0:
1023 rscreen->tiling_info.num_banks = 4;
1024 break;
1025 case 1:
1026 rscreen->tiling_info.num_banks = 8;
1027 break;
1028 case 2:
1029 rscreen->tiling_info.num_banks = 16;
1030 break;
1031 default:
1032 return -EINVAL;
1033 }
1034
1035 switch ((tiling_config & 0xf00) >> 8) {
1036 case 0:
1037 rscreen->tiling_info.group_bytes = 256;
1038 break;
1039 case 1:
1040 rscreen->tiling_info.group_bytes = 512;
1041 break;
1042 default:
1043 return -EINVAL;
1044 }
1045 return 0;
1046 }
1047
1048 static int r600_init_tiling(struct r600_screen *rscreen)
1049 {
1050 uint32_t tiling_config = rscreen->info.r600_tiling_config;
1051
1052 /* set default group bytes, overridden by tiling info ioctl */
1053 if (rscreen->chip_class <= R700) {
1054 rscreen->tiling_info.group_bytes = 256;
1055 } else {
1056 rscreen->tiling_info.group_bytes = 512;
1057 }
1058
1059 if (!tiling_config)
1060 return 0;
1061
1062 if (rscreen->chip_class <= R700) {
1063 return r600_interpret_tiling(rscreen, tiling_config);
1064 } else {
1065 return evergreen_interpret_tiling(rscreen, tiling_config);
1066 }
1067 }
1068
1069 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1070 {
1071 struct r600_screen *rscreen = (struct r600_screen*)screen;
1072
1073 return 1000000 * rscreen->ws->query_timestamp(rscreen->ws) /
1074 rscreen->info.r600_clock_crystal_freq;
1075 }
1076
1077 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
1078 {
1079 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
1080
1081 if (rscreen == NULL) {
1082 return NULL;
1083 }
1084
1085 rscreen->ws = ws;
1086 ws->query_info(ws, &rscreen->info);
1087
1088 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", debug_options, 0);
1089 rscreen->family = rscreen->info.family;
1090 rscreen->chip_class = rscreen->info.chip_class;
1091
1092 if (rscreen->family == CHIP_UNKNOWN) {
1093 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
1094 FREE(rscreen);
1095 return NULL;
1096 }
1097
1098 /* Figure out streamout kernel support. */
1099 switch (rscreen->chip_class) {
1100 case R600:
1101 if (rscreen->family < CHIP_RS780) {
1102 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
1103 } else {
1104 rscreen->has_streamout = rscreen->info.drm_minor >= 23;
1105 }
1106 break;
1107 case R700:
1108 rscreen->has_streamout = rscreen->info.drm_minor >= 17;
1109 break;
1110 case EVERGREEN:
1111 case CAYMAN:
1112 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
1113 break;
1114 default:
1115 rscreen->has_streamout = FALSE;
1116 break;
1117 }
1118
1119 /* MSAA support. */
1120 switch (rscreen->chip_class) {
1121 case R600:
1122 case R700:
1123 rscreen->has_msaa = rscreen->info.drm_minor >= 22;
1124 rscreen->msaa_texture_support = MSAA_TEXTURE_DECOMPRESSED;
1125 break;
1126 case EVERGREEN:
1127 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
1128 rscreen->msaa_texture_support =
1129 rscreen->info.drm_minor >= 24 ? MSAA_TEXTURE_COMPRESSED :
1130 MSAA_TEXTURE_DECOMPRESSED;
1131 break;
1132 case CAYMAN:
1133 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
1134 /* We should be able to read compressed MSAA textures, but it doesn't work. */
1135 rscreen->msaa_texture_support = MSAA_TEXTURE_SAMPLE_ZERO;
1136 break;
1137 default:
1138 rscreen->has_msaa = FALSE;
1139 rscreen->msaa_texture_support = 0;
1140 break;
1141 }
1142
1143 rscreen->has_cp_dma = rscreen->info.drm_minor >= 27 &&
1144 !(rscreen->debug_flags & DBG_NO_CP_DMA);
1145
1146 if (r600_init_tiling(rscreen)) {
1147 FREE(rscreen);
1148 return NULL;
1149 }
1150
1151 rscreen->screen.destroy = r600_destroy_screen;
1152 rscreen->screen.get_name = r600_get_name;
1153 rscreen->screen.get_vendor = r600_get_vendor;
1154 rscreen->screen.get_param = r600_get_param;
1155 rscreen->screen.get_shader_param = r600_get_shader_param;
1156 rscreen->screen.get_paramf = r600_get_paramf;
1157 rscreen->screen.get_video_param = r600_get_video_param;
1158 rscreen->screen.get_compute_param = r600_get_compute_param;
1159 rscreen->screen.get_timestamp = r600_get_timestamp;
1160
1161 if (rscreen->chip_class >= EVERGREEN) {
1162 rscreen->screen.is_format_supported = evergreen_is_format_supported;
1163 rscreen->dma_blit = &evergreen_dma_blit;
1164 } else {
1165 rscreen->screen.is_format_supported = r600_is_format_supported;
1166 rscreen->dma_blit = &r600_dma_blit;
1167 }
1168 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
1169 rscreen->screen.context_create = r600_create_context;
1170 rscreen->screen.fence_reference = r600_fence_reference;
1171 rscreen->screen.fence_signalled = r600_fence_signalled;
1172 rscreen->screen.fence_finish = r600_fence_finish;
1173 r600_init_screen_resource_functions(&rscreen->screen);
1174
1175 util_format_s3tc_init();
1176
1177 rscreen->fences.bo = NULL;
1178 rscreen->fences.data = NULL;
1179 rscreen->fences.next_index = 0;
1180 LIST_INITHEAD(&rscreen->fences.pool);
1181 LIST_INITHEAD(&rscreen->fences.blocks);
1182 pipe_mutex_init(rscreen->fences.mutex);
1183
1184 rscreen->global_pool = compute_memory_pool_new(rscreen);
1185
1186 #if R600_TRACE_CS
1187 rscreen->cs_count = 0;
1188 if (rscreen->info.drm_minor >= 28) {
1189 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->screen,
1190 PIPE_BIND_CUSTOM,
1191 PIPE_USAGE_STAGING,
1192 4096);
1193 if (rscreen->trace_bo) {
1194 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
1195 PIPE_TRANSFER_UNSYNCHRONIZED);
1196 }
1197 }
1198 #endif
1199
1200 return &rscreen->screen;
1201 }