src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25
  26 #include <errno.h>
  27 #include "pipe/p_shader_tokens.h"
  28 #include "util/u_blitter.h"
  29 #include "util/u_format_s3tc.h"
  30 #include "util/u_simple_shaders.h"
  31 #include "util/u_upload_mgr.h"
  32 #include "vl/vl_decoder.h"
  33 #include "vl/vl_video_buffer.h"
  34 #include "os/os_time.h"
  35
  36 /*
  37  * pipe_context
  38  */
  39 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  40 {
  41         struct r600_screen *rscreen = rctx->screen;
  42         struct r600_fence *fence = NULL;
  43
  44         pipe_mutex_lock(rscreen->fences.mutex);
  45
  46         if (!rscreen->fences.bo) {
  47                 /* Create the shared buffer object */
  48                 rscreen->fences.bo = (struct r600_resource*)
  49                         pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
  50                                            PIPE_USAGE_STAGING, 4096);
  51                 if (!rscreen->fences.bo) {
  52                         R600_ERR("r600: failed to create bo for fence objects\n");
  53                         goto out;
  54                 }
  55                 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf,
  56                                                            rctx->cs,
  57                                                            PIPE_TRANSFER_READ_WRITE);
  58         }
  59
  60         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  61                 struct r600_fence *entry;
  62
  63                 /* Try to find a freed fence that has been signalled */
  64                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  65                         if (rscreen->fences.data[entry->index] != 0) {
  66                                 LIST_DELINIT(&entry->head);
  67                                 fence = entry;
  68                                 break;
  69                         }
  70                 }
  71         }
  72
  73         if (!fence) {
  74                 /* Allocate a new fence */
  75                 struct r600_fence_block *block;
  76                 unsigned index;
  77
  78                 if ((rscreen->fences.next_index + 1) >= 1024) {
  79                         R600_ERR("r600: too many concurrent fences\n");
  80                         goto out;
  81                 }
  82
  83                 index = rscreen->fences.next_index++;
  84
  85                 if (!(index % FENCE_BLOCK_SIZE)) {
  86                         /* Allocate a new block */
  87                         block = CALLOC_STRUCT(r600_fence_block);
  88                         if (block == NULL)
  89                                 goto out;
  90
  91                         LIST_ADD(&block->head, &rscreen->fences.blocks);
  92                 } else {
  93                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
  94                 }
  95
  96                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
  97                 fence->index = index;
  98         }
  99
 100         pipe_reference_init(&fence->reference, 1);
 101
 102         rscreen->fences.data[fence->index] = 0;
 103         r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 104
 105         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 106         fence->sleep_bo = (struct r600_resource*)
 107                         pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
 108                                            PIPE_USAGE_STAGING, 1);
 109         /* Add the fence as a dummy relocation. */
 110         r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 111
 112 out:
 113         pipe_mutex_unlock(rscreen->fences.mutex);
 114         return fence;
 115 }
 116
 117
 118 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 119                 unsigned flags)
 120 {
 121         struct r600_context *rctx = (struct r600_context *)ctx;
 122         struct r600_fence **rfence = (struct r600_fence**)fence;
 123         struct pipe_query *render_cond = NULL;
 124         unsigned render_cond_mode = 0;
 125
 126         if (rfence)
 127                 *rfence = r600_create_fence(rctx);
 128
 129         /* Disable render condition. */
 130         if (rctx->current_render_cond) {
 131                 render_cond = rctx->current_render_cond;
 132                 render_cond_mode = rctx->current_render_cond_mode;
 133                 ctx->render_condition(ctx, NULL, 0);
 134         }
 135
 136         r600_context_flush(rctx, flags);
 137
 138         /* Re-enable render condition. */
 139         if (render_cond) {
 140                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 141         }
 142 }
 143
 144 static void r600_flush_from_st(struct pipe_context *ctx,
 145                                struct pipe_fence_handle **fence)
 146 {
 147         r600_flush(ctx, fence, 0);
 148 }
 149
 150 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 151 {
 152         r600_flush((struct pipe_context*)ctx, NULL, flags);
 153 }
 154
 155 static void r600_destroy_context(struct pipe_context *context)
 156 {
 157         struct r600_context *rctx = (struct r600_context *)context;
 158
 159         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
 160         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
 161
 162         if (rctx->no_blend) {
 163                 rctx->context.delete_blend_state(&rctx->context, rctx->no_blend);
 164         }
 165         if (rctx->dummy_pixel_shader) {
 166                 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 167         }
 168         if (rctx->custom_dsa_flush) {
 169                 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 170         }
 171         if (rctx->custom_blend_resolve) {
 172                 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve);
 173         }
 174         if (rctx->custom_blend_decompress) {
 175                 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_decompress);
 176         }
 177         util_unreference_framebuffer_state(&rctx->framebuffer);
 178
 179         r600_context_fini(rctx);
 180
 181         if (rctx->blitter) {
 182                 util_blitter_destroy(rctx->blitter);
 183         }
 184         for (int i = 0; i < R600_PIPE_NSTATES; i++) {
 185                 free(rctx->states[i]);
 186         }
 187
 188         if (rctx->uploader) {
 189                 u_upload_destroy(rctx->uploader);
 190         }
 191         util_slab_destroy(&rctx->pool_transfers);
 192
 193         r600_release_command_buffer(&rctx->start_cs_cmd);
 194
 195         if (rctx->cs) {
 196                 rctx->ws->cs_destroy(rctx->cs);
 197         }
 198
 199         FREE(rctx->range);
 200         FREE(rctx);
 201 }
 202
 203 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 204 {
 205         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 206         struct r600_screen* rscreen = (struct r600_screen *)screen;
 207         struct pipe_blend_state no_blend = {};
 208
 209         if (rctx == NULL)
 210                 return NULL;
 211
 212         util_slab_create(&rctx->pool_transfers,
 213                          sizeof(struct r600_transfer), 64,
 214                          UTIL_SLAB_SINGLETHREADED);
 215
 216         rctx->context.screen = screen;
 217         rctx->context.priv = priv;
 218         rctx->context.destroy = r600_destroy_context;
 219         rctx->context.flush = r600_flush_from_st;
 220
 221         /* Easy accessing of screen/winsys. */
 222         rctx->screen = rscreen;
 223         rctx->ws = rscreen->ws;
 224         rctx->family = rscreen->family;
 225         rctx->chip_class = rscreen->chip_class;
 226
 227         LIST_INITHEAD(&rctx->active_timer_queries);
 228         LIST_INITHEAD(&rctx->active_nontimer_queries);
 229         LIST_INITHEAD(&rctx->dirty);
 230         LIST_INITHEAD(&rctx->enable_list);
 231
 232         rctx->range = CALLOC(NUM_RANGES, sizeof(struct r600_range));
 233         if (!rctx->range)
 234                 goto fail;
 235
 236         r600_init_blit_functions(rctx);
 237         r600_init_query_functions(rctx);
 238         r600_init_context_resource_functions(rctx);
 239         r600_init_surface_functions(rctx);
 240
 241
 242         rctx->context.create_video_decoder = vl_create_decoder;
 243         rctx->context.create_video_buffer = vl_video_buffer_create;
 244
 245         r600_init_common_state_functions(rctx);
 246
 247         switch (rctx->chip_class) {
 248         case R600:
 249         case R700:
 250                 r600_init_state_functions(rctx);
 251                 r600_init_atom_start_cs(rctx);
 252                 if (r600_context_init(rctx))
 253                         goto fail;
 254                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 255                 rctx->custom_blend_resolve = rctx->chip_class == R700 ? r700_create_resolve_blend(rctx)
 256                                                                       : r600_create_resolve_blend(rctx);
 257                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 258                 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
 259                                            rctx->family == CHIP_RV620 ||
 260                                            rctx->family == CHIP_RS780 ||
 261                                            rctx->family == CHIP_RS880 ||
 262                                            rctx->family == CHIP_RV710);
 263                 break;
 264         case EVERGREEN:
 265         case CAYMAN:
 266                 evergreen_init_state_functions(rctx);
 267                 evergreen_init_atom_start_cs(rctx);
 268                 evergreen_init_atom_start_compute_cs(rctx);
 269                 if (evergreen_context_init(rctx))
 270                         goto fail;
 271                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 272                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 273                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 274                 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
 275                                            rctx->family == CHIP_PALM ||
 276                                            rctx->family == CHIP_SUMO ||
 277                                            rctx->family == CHIP_SUMO2 ||
 278                                            rctx->family == CHIP_CAICOS ||
 279                                            rctx->family == CHIP_CAYMAN ||
 280                                            rctx->family == CHIP_ARUBA);
 281                 break;
 282         default:
 283                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 284                 goto fail;
 285         }
 286
 287         rctx->cs = rctx->ws->cs_create(rctx->ws);
 288         rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
 289
 290         rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
 291                                          PIPE_BIND_INDEX_BUFFER |
 292                                          PIPE_BIND_CONSTANT_BUFFER);
 293         if (!rctx->uploader)
 294                 goto fail;
 295
 296         rctx->blitter = util_blitter_create(&rctx->context);
 297         if (rctx->blitter == NULL)
 298                 goto fail;
 299         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 300
 301         r600_begin_new_cs(rctx);
 302         r600_get_backend_mask(rctx); /* this emits commands and must be last */
 303
 304         if (rctx->chip_class == R600)
 305                 r600_set_max_scissor(rctx);
 306
 307         rctx->dummy_pixel_shader =
 308                 util_make_fragment_cloneinput_shader(&rctx->context, 0,
 309                                                      TGSI_SEMANTIC_GENERIC,
 310                                                      TGSI_INTERPOLATE_CONSTANT);
 311         rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 312
 313         no_blend.rt[0].colormask = 0xF;
 314         rctx->no_blend = rctx->context.create_blend_state(&rctx->context, &no_blend);
 315
 316         return &rctx->context;
 317
 318 fail:
 319         r600_destroy_context(&rctx->context);
 320         return NULL;
 321 }
 322
 323 /*
 324  * pipe_screen
 325  */
 326 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 327 {
 328         return "X.Org";
 329 }
 330
 331 static const char *r600_get_family_name(enum radeon_family family)
 332 {
 333         switch(family) {
 334         case CHIP_R600: return "AMD R600";
 335         case CHIP_RV610: return "AMD RV610";
 336         case CHIP_RV630: return "AMD RV630";
 337         case CHIP_RV670: return "AMD RV670";
 338         case CHIP_RV620: return "AMD RV620";
 339         case CHIP_RV635: return "AMD RV635";
 340         case CHIP_RS780: return "AMD RS780";
 341         case CHIP_RS880: return "AMD RS880";
 342         case CHIP_RV770: return "AMD RV770";
 343         case CHIP_RV730: return "AMD RV730";
 344         case CHIP_RV710: return "AMD RV710";
 345         case CHIP_RV740: return "AMD RV740";
 346         case CHIP_CEDAR: return "AMD CEDAR";
 347         case CHIP_REDWOOD: return "AMD REDWOOD";
 348         case CHIP_JUNIPER: return "AMD JUNIPER";
 349         case CHIP_CYPRESS: return "AMD CYPRESS";
 350         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 351         case CHIP_PALM: return "AMD PALM";
 352         case CHIP_SUMO: return "AMD SUMO";
 353         case CHIP_SUMO2: return "AMD SUMO2";
 354         case CHIP_BARTS: return "AMD BARTS";
 355         case CHIP_TURKS: return "AMD TURKS";
 356         case CHIP_CAICOS: return "AMD CAICOS";
 357         case CHIP_CAYMAN: return "AMD CAYMAN";
 358         case CHIP_ARUBA: return "AMD ARUBA";
 359         default: return "AMD unknown";
 360         }
 361 }
 362
 363 static const char* r600_get_name(struct pipe_screen* pscreen)
 364 {
 365         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 366
 367         return r600_get_family_name(rscreen->family);
 368 }
 369
 370 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 371 {
 372         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 373         enum radeon_family family = rscreen->family;
 374
 375         switch (param) {
 376         /* Supported features (boolean caps). */
 377         case PIPE_CAP_NPOT_TEXTURES:
 378         case PIPE_CAP_TWO_SIDED_STENCIL:
 379         case PIPE_CAP_ANISOTROPIC_FILTER:
 380         case PIPE_CAP_POINT_SPRITE:
 381         case PIPE_CAP_OCCLUSION_QUERY:
 382         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 383         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 384         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 385         case PIPE_CAP_TEXTURE_SWIZZLE:
 386         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 387         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 388         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 389         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 390         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 391         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 392         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 393         case PIPE_CAP_SM3:
 394         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 395         case PIPE_CAP_PRIMITIVE_RESTART:
 396         case PIPE_CAP_CONDITIONAL_RENDER:
 397         case PIPE_CAP_TEXTURE_BARRIER:
 398         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 399         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 400         case PIPE_CAP_TGSI_INSTANCEID:
 401         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 402         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 403         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 404         case PIPE_CAP_USER_INDEX_BUFFERS:
 405         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 406         case PIPE_CAP_COMPUTE:
 407         case PIPE_CAP_START_INSTANCE:
 408         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 409                 return 1;
 410
 411         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 412                 return 256;
 413
 414         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 415                 return 130;
 416
 417         /* Supported except the original R600. */
 418         case PIPE_CAP_INDEP_BLEND_ENABLE:
 419         case PIPE_CAP_INDEP_BLEND_FUNC:
 420                 /* R600 doesn't support per-MRT blends */
 421                 return family == CHIP_R600 ? 0 : 1;
 422
 423         /* Supported on Evergreen. */
 424         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 425                 return family >= CHIP_CEDAR ? 1 : 0;
 426
 427         /* Unsupported features. */
 428         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 429         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 430         case PIPE_CAP_SCALED_RESOLVE:
 431         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 432         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 433         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 434         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 435         case PIPE_CAP_USER_VERTEX_BUFFERS:
 436                 return 0;
 437
 438         /* Stream output. */
 439         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 440                 return rscreen->has_streamout ? 4 : 0;
 441         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 442                 return rscreen->has_streamout ? 1 : 0;
 443         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 444         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 445                 return 16*4;
 446
 447         /* Texturing. */
 448         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 449         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 450         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 451                 if (family >= CHIP_CEDAR)
 452                         return 15;
 453                 else
 454                         return 14;
 455         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 456                 return rscreen->info.drm_minor >= 9 ?
 457                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 458         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 459                 return 32;
 460
 461         /* Render targets. */
 462         case PIPE_CAP_MAX_RENDER_TARGETS:
 463                 /* XXX some r6xx are buggy and can only do 4 */
 464                 return 8;
 465
 466         /* Timer queries, present when the clock frequency is non zero. */
 467         case PIPE_CAP_TIMER_QUERY:
 468                 return rscreen->info.r600_clock_crystal_freq != 0;
 469         case PIPE_CAP_QUERY_TIMESTAMP:
 470                 return rscreen->info.drm_minor >= 20 &&
 471                        rscreen->info.r600_clock_crystal_freq != 0;
 472
 473         case PIPE_CAP_MIN_TEXEL_OFFSET:
 474                 return -8;
 475
 476         case PIPE_CAP_MAX_TEXEL_OFFSET:
 477                 return 7;
 478         }
 479         return 0;
 480 }
 481
 482 static float r600_get_paramf(struct pipe_screen* pscreen,
 483                              enum pipe_capf param)
 484 {
 485         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 486         enum radeon_family family = rscreen->family;
 487
 488         switch (param) {
 489         case PIPE_CAPF_MAX_LINE_WIDTH:
 490         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 491         case PIPE_CAPF_MAX_POINT_WIDTH:
 492         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 493                 if (family >= CHIP_CEDAR)
 494                         return 16384.0f;
 495                 else
 496                         return 8192.0f;
 497         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 498                 return 16.0f;
 499         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 500                 return 16.0f;
 501         case PIPE_CAPF_GUARD_BAND_LEFT:
 502         case PIPE_CAPF_GUARD_BAND_TOP:
 503         case PIPE_CAPF_GUARD_BAND_RIGHT:
 504         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 505                 return 0.0f;
 506         }
 507         return 0.0f;
 508 }
 509
 510 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 511 {
 512         switch(shader)
 513         {
 514         case PIPE_SHADER_FRAGMENT:
 515         case PIPE_SHADER_VERTEX:
 516         case PIPE_SHADER_COMPUTE:
 517                 break;
 518         case PIPE_SHADER_GEOMETRY:
 519                 /* XXX: support and enable geometry programs */
 520                 return 0;
 521         default:
 522                 /* XXX: support tessellation on Evergreen */
 523                 return 0;
 524         }
 525
 526         /* XXX: all these should be fixed, since r600 surely supports much more! */
 527         switch (param) {
 528         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 529         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 530         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 531         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 532                 return 16384;
 533         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 534                 return 8; /* XXX */
 535         case PIPE_SHADER_CAP_MAX_INPUTS:
 536                 if(shader == PIPE_SHADER_FRAGMENT)
 537                         return 34;
 538                 else
 539                         return 32;
 540         case PIPE_SHADER_CAP_MAX_TEMPS:
 541                 return 256; /* Max native temporaries. */
 542         case PIPE_SHADER_CAP_MAX_ADDRS:
 543                 /* XXX Isn't this equal to TEMPS? */
 544                 return 1; /* Max native address registers */
 545         case PIPE_SHADER_CAP_MAX_CONSTS:
 546                 return R600_MAX_CONST_BUFFER_SIZE;
 547         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 548                 return R600_MAX_CONST_BUFFERS-1;
 549         case PIPE_SHADER_CAP_MAX_PREDS:
 550                 return 0; /* nothing uses this */
 551         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 552                 return 1;
 553         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 554         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 555         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 556         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 557                 return 1;
 558         case PIPE_SHADER_CAP_SUBROUTINES:
 559                 return 0;
 560         case PIPE_SHADER_CAP_INTEGERS:
 561                 return 1;
 562         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 563                 return 16;
 564         case PIPE_SHADER_CAP_PREFERRED_IR:
 565                 if (shader == PIPE_SHADER_COMPUTE) {
 566                         return PIPE_SHADER_IR_LLVM;
 567                 } else {
 568                         return PIPE_SHADER_IR_TGSI;
 569                 }
 570         }
 571         return 0;
 572 }
 573
 574 static int r600_get_video_param(struct pipe_screen *screen,
 575                                 enum pipe_video_profile profile,
 576                                 enum pipe_video_cap param)
 577 {
 578         switch (param) {
 579         case PIPE_VIDEO_CAP_SUPPORTED:
 580                 return vl_profile_supported(screen, profile);
 581         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 582                 return 1;
 583         case PIPE_VIDEO_CAP_MAX_WIDTH:
 584         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 585                 return vl_video_buffer_max_size(screen);
 586         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 587                 return PIPE_FORMAT_NV12;
 588         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 589                 return false;
 590         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 591                 return false;
 592         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 593                 return true;
 594         default:
 595                 return 0;
 596         }
 597 }
 598
 599 static int r600_get_compute_param(struct pipe_screen *screen,
 600         enum pipe_compute_cap param,
 601         void *ret)
 602 {
 603         //TODO: select these params by asic
 604         switch (param) {
 605         case PIPE_COMPUTE_CAP_IR_TARGET:
 606                 if (ret) {
 607                         strcpy(ret, "r600--");
 608                 }
 609                 return 7 * sizeof(char);
 610
 611         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 612                 if (ret) {
 613                         uint64_t * grid_dimension = ret;
 614                         grid_dimension[0] = 3;
 615                 }
 616                 return 1 * sizeof(uint64_t);
 617
 618         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 619                 if (ret) {
 620                         uint64_t * grid_size = ret;
 621                         grid_size[0] = 65535;
 622                         grid_size[1] = 65535;
 623                         grid_size[2] = 1;
 624                 }
 625                 return 3 * sizeof(uint64_t) ;
 626
 627         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 628                 if (ret) {
 629                         uint64_t * block_size = ret;
 630                         block_size[0] = 256;
 631                         block_size[1] = 256;
 632                         block_size[2] = 256;
 633                 }
 634                 return 3 * sizeof(uint64_t);
 635
 636         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 637                 if (ret) {
 638                         uint64_t * max_threads_per_block = ret;
 639                         *max_threads_per_block = 256;
 640                 }
 641                 return sizeof(uint64_t);
 642
 643         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 644                 if (ret) {
 645                         uint64_t * max_global_size = ret;
 646                         /* XXX: This is 64kb for now until we get the
 647                          * compute memory pool working correctly.
 648                          */
 649                         *max_global_size = 1024 * 16 * 4;
 650                 }
 651                 return sizeof(uint64_t);
 652
 653         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 654                 if (ret) {
 655                         uint64_t * max_input_size = ret;
 656                         *max_input_size = 1024;
 657                 }
 658                 return sizeof(uint64_t);
 659
 660         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 661                 if (ret) {
 662                         uint64_t * max_local_size = ret;
 663                         /* XXX: This is what the proprietary driver reports, we
 664                          * may want to use a different value. */
 665                         *max_local_size = 32768;
 666                 }
 667                 return sizeof(uint64_t);
 668
 669         default:
 670                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 671                 return 0;
 672         }
 673 }
 674
 675 static void r600_destroy_screen(struct pipe_screen* pscreen)
 676 {
 677         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 678
 679         if (rscreen == NULL)
 680                 return;
 681
 682         if (rscreen->global_pool) {
 683                 compute_memory_pool_delete(rscreen->global_pool);
 684         }
 685
 686         if (rscreen->fences.bo) {
 687                 struct r600_fence_block *entry, *tmp;
 688
 689                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 690                         LIST_DEL(&entry->head);
 691                         FREE(entry);
 692                 }
 693
 694                 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
 695                 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
 696         }
 697         pipe_mutex_destroy(rscreen->fences.mutex);
 698
 699         rscreen->ws->destroy(rscreen->ws);
 700         FREE(rscreen);
 701 }
 702
 703 static void r600_fence_reference(struct pipe_screen *pscreen,
 704                                  struct pipe_fence_handle **ptr,
 705                                  struct pipe_fence_handle *fence)
 706 {
 707         struct r600_fence **oldf = (struct r600_fence**)ptr;
 708         struct r600_fence *newf = (struct r600_fence*)fence;
 709
 710         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 711                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 712                 pipe_mutex_lock(rscreen->fences.mutex);
 713                 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
 714                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 715                 pipe_mutex_unlock(rscreen->fences.mutex);
 716         }
 717
 718         *ptr = fence;
 719 }
 720
 721 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 722                                     struct pipe_fence_handle *fence)
 723 {
 724         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 725         struct r600_fence *rfence = (struct r600_fence*)fence;
 726
 727         return rscreen->fences.data[rfence->index];
 728 }
 729
 730 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 731                                  struct pipe_fence_handle *fence,
 732                                  uint64_t timeout)
 733 {
 734         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 735         struct r600_fence *rfence = (struct r600_fence*)fence;
 736         int64_t start_time = 0;
 737         unsigned spins = 0;
 738
 739         if (timeout != PIPE_TIMEOUT_INFINITE) {
 740                 start_time = os_time_get();
 741
 742                 /* Convert to microseconds. */
 743                 timeout /= 1000;
 744         }
 745
 746         while (rscreen->fences.data[rfence->index] == 0) {
 747                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
 748                 if (timeout == PIPE_TIMEOUT_INFINITE) {
 749                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
 750                         break;
 751                 }
 752
 753                 /* The dummy BO will be busy until the CS including the fence has completed, or
 754                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
 755                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
 756                         break;
 757
 758                 if (++spins % 256)
 759                         continue;
 760 #ifdef PIPE_OS_UNIX
 761                 sched_yield();
 762 #else
 763                 os_time_sleep(10);
 764 #endif
 765                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 766                     os_time_get() - start_time >= timeout) {
 767                         break;
 768                 }
 769         }
 770
 771         return rscreen->fences.data[rfence->index] != 0;
 772 }
 773
 774 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 775 {
 776         switch ((tiling_config & 0xe) >> 1) {
 777         case 0:
 778                 rscreen->tiling_info.num_channels = 1;
 779                 break;
 780         case 1:
 781                 rscreen->tiling_info.num_channels = 2;
 782                 break;
 783         case 2:
 784                 rscreen->tiling_info.num_channels = 4;
 785                 break;
 786         case 3:
 787                 rscreen->tiling_info.num_channels = 8;
 788                 break;
 789         default:
 790                 return -EINVAL;
 791         }
 792
 793         switch ((tiling_config & 0x30) >> 4) {
 794         case 0:
 795                 rscreen->tiling_info.num_banks = 4;
 796                 break;
 797         case 1:
 798                 rscreen->tiling_info.num_banks = 8;
 799                 break;
 800         default:
 801                 return -EINVAL;
 802
 803         }
 804         switch ((tiling_config & 0xc0) >> 6) {
 805         case 0:
 806                 rscreen->tiling_info.group_bytes = 256;
 807                 break;
 808         case 1:
 809                 rscreen->tiling_info.group_bytes = 512;
 810                 break;
 811         default:
 812                 return -EINVAL;
 813         }
 814         return 0;
 815 }
 816
 817 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 818 {
 819         switch (tiling_config & 0xf) {
 820         case 0:
 821                 rscreen->tiling_info.num_channels = 1;
 822                 break;
 823         case 1:
 824                 rscreen->tiling_info.num_channels = 2;
 825                 break;
 826         case 2:
 827                 rscreen->tiling_info.num_channels = 4;
 828                 break;
 829         case 3:
 830                 rscreen->tiling_info.num_channels = 8;
 831                 break;
 832         default:
 833                 return -EINVAL;
 834         }
 835
 836         switch ((tiling_config & 0xf0) >> 4) {
 837         case 0:
 838                 rscreen->tiling_info.num_banks = 4;
 839                 break;
 840         case 1:
 841                 rscreen->tiling_info.num_banks = 8;
 842                 break;
 843         case 2:
 844                 rscreen->tiling_info.num_banks = 16;
 845                 break;
 846         default:
 847                 return -EINVAL;
 848         }
 849
 850         switch ((tiling_config & 0xf00) >> 8) {
 851         case 0:
 852                 rscreen->tiling_info.group_bytes = 256;
 853                 break;
 854         case 1:
 855                 rscreen->tiling_info.group_bytes = 512;
 856                 break;
 857         default:
 858                 return -EINVAL;
 859         }
 860         return 0;
 861 }
 862
 863 static int r600_init_tiling(struct r600_screen *rscreen)
 864 {
 865         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 866
 867         /* set default group bytes, overridden by tiling info ioctl */
 868         if (rscreen->chip_class <= R700) {
 869                 rscreen->tiling_info.group_bytes = 256;
 870         } else {
 871                 rscreen->tiling_info.group_bytes = 512;
 872         }
 873
 874         if (!tiling_config)
 875                 return 0;
 876
 877         if (rscreen->chip_class <= R700) {
 878                 return r600_interpret_tiling(rscreen, tiling_config);
 879         } else {
 880                 return evergreen_interpret_tiling(rscreen, tiling_config);
 881         }
 882 }
 883
 884 static unsigned radeon_family_from_device(unsigned device)
 885 {
 886         switch (device) {
 887 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 888 #include "pci_ids/r600_pci_ids.h"
 889 #undef CHIPSET
 890         default:
 891                 return CHIP_UNKNOWN;
 892         }
 893 }
 894
 895 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 896 {
 897         struct r600_screen *rscreen = (struct r600_screen*)screen;
 898
 899         return 1000000 * rscreen->ws->query_timestamp(rscreen->ws) /
 900                         rscreen->info.r600_clock_crystal_freq;
 901 }
 902
 903 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 904 {
 905         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 906
 907         if (rscreen == NULL) {
 908                 return NULL;
 909         }
 910
 911         rscreen->ws = ws;
 912         ws->query_info(ws, &rscreen->info);
 913
 914         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 915         if (rscreen->family == CHIP_UNKNOWN) {
 916                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 917                 FREE(rscreen);
 918                 return NULL;
 919         }
 920
 921         /* setup class */
 922         if (rscreen->family >= CHIP_CAYMAN) {
 923                 rscreen->chip_class = CAYMAN;
 924         } else if (rscreen->family >= CHIP_CEDAR) {
 925                 rscreen->chip_class = EVERGREEN;
 926         } else if (rscreen->family >= CHIP_RV770) {
 927                 rscreen->chip_class = R700;
 928         } else {
 929                 rscreen->chip_class = R600;
 930         }
 931
 932         /* Figure out streamout kernel support. */
 933         switch (rscreen->chip_class) {
 934         case R600:
 935         case EVERGREEN:
 936         case CAYMAN:
 937                 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
 938                 break;
 939         case R700:
 940                 rscreen->has_streamout = rscreen->info.drm_minor >= 17;
 941                 break;
 942         }
 943
 944         if (r600_init_tiling(rscreen)) {
 945                 FREE(rscreen);
 946                 return NULL;
 947         }
 948
 949         rscreen->screen.destroy = r600_destroy_screen;
 950         rscreen->screen.get_name = r600_get_name;
 951         rscreen->screen.get_vendor = r600_get_vendor;
 952         rscreen->screen.get_param = r600_get_param;
 953         rscreen->screen.get_shader_param = r600_get_shader_param;
 954         rscreen->screen.get_paramf = r600_get_paramf;
 955         rscreen->screen.get_video_param = r600_get_video_param;
 956         rscreen->screen.get_compute_param = r600_get_compute_param;
 957         rscreen->screen.get_timestamp = r600_get_timestamp;
 958
 959         if (rscreen->chip_class >= EVERGREEN) {
 960                 rscreen->screen.is_format_supported = evergreen_is_format_supported;
 961         } else {
 962                 rscreen->screen.is_format_supported = r600_is_format_supported;
 963         }
 964         rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 965         rscreen->screen.context_create = r600_create_context;
 966         rscreen->screen.fence_reference = r600_fence_reference;
 967         rscreen->screen.fence_signalled = r600_fence_signalled;
 968         rscreen->screen.fence_finish = r600_fence_finish;
 969         r600_init_screen_resource_functions(&rscreen->screen);
 970
 971         util_format_s3tc_init();
 972
 973         rscreen->fences.bo = NULL;
 974         rscreen->fences.data = NULL;
 975         rscreen->fences.next_index = 0;
 976         LIST_INITHEAD(&rscreen->fences.pool);
 977         LIST_INITHEAD(&rscreen->fences.blocks);
 978         pipe_mutex_init(rscreen->fences.mutex);
 979
 980         rscreen->global_pool = compute_memory_pool_new(rscreen);
 981
 982         return &rscreen->screen;
 983 }