src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25
  26 #include <errno.h>
  27 #include "pipe/p_shader_tokens.h"
  28 #include "util/u_blitter.h"
  29 #include "util/u_format_s3tc.h"
  30 #include "util/u_simple_shaders.h"
  31 #include "util/u_upload_mgr.h"
  32 #include "vl/vl_decoder.h"
  33 #include "vl/vl_video_buffer.h"
  34 #include "os/os_time.h"
  35
  36 /*
  37  * pipe_context
  38  */
  39 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  40 {
  41         struct r600_screen *rscreen = rctx->screen;
  42         struct r600_fence *fence = NULL;
  43
  44         pipe_mutex_lock(rscreen->fences.mutex);
  45
  46         if (!rscreen->fences.bo) {
  47                 /* Create the shared buffer object */
  48                 rscreen->fences.bo = (struct r600_resource*)
  49                         pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
  50                                            PIPE_USAGE_STAGING, 4096);
  51                 if (!rscreen->fences.bo) {
  52                         R600_ERR("r600: failed to create bo for fence objects\n");
  53                         goto out;
  54                 }
  55                 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf,
  56                                                            rctx->cs,
  57                                                            PIPE_TRANSFER_READ_WRITE);
  58         }
  59
  60         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  61                 struct r600_fence *entry;
  62
  63                 /* Try to find a freed fence that has been signalled */
  64                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  65                         if (rscreen->fences.data[entry->index] != 0) {
  66                                 LIST_DELINIT(&entry->head);
  67                                 fence = entry;
  68                                 break;
  69                         }
  70                 }
  71         }
  72
  73         if (!fence) {
  74                 /* Allocate a new fence */
  75                 struct r600_fence_block *block;
  76                 unsigned index;
  77
  78                 if ((rscreen->fences.next_index + 1) >= 1024) {
  79                         R600_ERR("r600: too many concurrent fences\n");
  80                         goto out;
  81                 }
  82
  83                 index = rscreen->fences.next_index++;
  84
  85                 if (!(index % FENCE_BLOCK_SIZE)) {
  86                         /* Allocate a new block */
  87                         block = CALLOC_STRUCT(r600_fence_block);
  88                         if (block == NULL)
  89                                 goto out;
  90
  91                         LIST_ADD(&block->head, &rscreen->fences.blocks);
  92                 } else {
  93                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
  94                 }
  95
  96                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
  97                 fence->index = index;
  98         }
  99
 100         pipe_reference_init(&fence->reference, 1);
 101
 102         rscreen->fences.data[fence->index] = 0;
 103         r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 104
 105         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 106         fence->sleep_bo = (struct r600_resource*)
 107                         pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
 108                                            PIPE_USAGE_STAGING, 1);
 109         /* Add the fence as a dummy relocation. */
 110         r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 111
 112 out:
 113         pipe_mutex_unlock(rscreen->fences.mutex);
 114         return fence;
 115 }
 116
 117
 118 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 119                 unsigned flags)
 120 {
 121         struct r600_context *rctx = (struct r600_context *)ctx;
 122         struct r600_fence **rfence = (struct r600_fence**)fence;
 123         struct pipe_query *render_cond = NULL;
 124         unsigned render_cond_mode = 0;
 125
 126         if (rfence)
 127                 *rfence = r600_create_fence(rctx);
 128
 129         /* Disable render condition. */
 130         if (rctx->current_render_cond) {
 131                 render_cond = rctx->current_render_cond;
 132                 render_cond_mode = rctx->current_render_cond_mode;
 133                 ctx->render_condition(ctx, NULL, 0);
 134         }
 135
 136         r600_context_flush(rctx, flags);
 137
 138         /* Re-enable render condition. */
 139         if (render_cond) {
 140                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 141         }
 142 }
 143
 144 static void r600_flush_from_st(struct pipe_context *ctx,
 145                                struct pipe_fence_handle **fence)
 146 {
 147         r600_flush(ctx, fence, 0);
 148 }
 149
 150 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 151 {
 152         r600_flush((struct pipe_context*)ctx, NULL, flags);
 153 }
 154
 155 static void r600_destroy_context(struct pipe_context *context)
 156 {
 157         struct r600_context *rctx = (struct r600_context *)context;
 158
 159         if (rctx->dummy_pixel_shader) {
 160                 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 161         }
 162         if (rctx->custom_dsa_flush) {
 163                 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 164         }
 165         util_unreference_framebuffer_state(&rctx->framebuffer);
 166
 167         r600_context_fini(rctx);
 168
 169         if (rctx->blitter) {
 170                 util_blitter_destroy(rctx->blitter);
 171         }
 172         for (int i = 0; i < R600_PIPE_NSTATES; i++) {
 173                 free(rctx->states[i]);
 174         }
 175
 176         if (rctx->uploader) {
 177                 u_upload_destroy(rctx->uploader);
 178         }
 179         util_slab_destroy(&rctx->pool_transfers);
 180
 181         r600_release_command_buffer(&rctx->start_cs_cmd);
 182
 183         if (rctx->cs) {
 184                 rctx->ws->cs_destroy(rctx->cs);
 185         }
 186
 187         FREE(rctx->range);
 188         FREE(rctx);
 189 }
 190
 191 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 192 {
 193         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 194         struct r600_screen* rscreen = (struct r600_screen *)screen;
 195
 196         if (rctx == NULL)
 197                 return NULL;
 198
 199         util_slab_create(&rctx->pool_transfers,
 200                          sizeof(struct pipe_transfer), 64,
 201                          UTIL_SLAB_SINGLETHREADED);
 202
 203         rctx->context.screen = screen;
 204         rctx->context.priv = priv;
 205         rctx->context.destroy = r600_destroy_context;
 206         rctx->context.flush = r600_flush_from_st;
 207
 208         /* Easy accessing of screen/winsys. */
 209         rctx->screen = rscreen;
 210         rctx->ws = rscreen->ws;
 211         rctx->family = rscreen->family;
 212         rctx->chip_class = rscreen->chip_class;
 213
 214         LIST_INITHEAD(&rctx->dirty_states);
 215         LIST_INITHEAD(&rctx->active_timer_queries);
 216         LIST_INITHEAD(&rctx->active_nontimer_queries);
 217         LIST_INITHEAD(&rctx->dirty);
 218         LIST_INITHEAD(&rctx->resource_dirty);
 219         LIST_INITHEAD(&rctx->enable_list);
 220
 221         rctx->range = CALLOC(NUM_RANGES, sizeof(struct r600_range));
 222         if (!rctx->range)
 223                 goto fail;
 224
 225         r600_init_blit_functions(rctx);
 226         r600_init_query_functions(rctx);
 227         r600_init_context_resource_functions(rctx);
 228         r600_init_surface_functions(rctx);
 229         rctx->context.draw_vbo = r600_draw_vbo;
 230
 231         rctx->context.create_video_decoder = vl_create_decoder;
 232         rctx->context.create_video_buffer = vl_video_buffer_create;
 233
 234         r600_init_common_atoms(rctx);
 235
 236         switch (rctx->chip_class) {
 237         case R600:
 238         case R700:
 239                 r600_init_state_functions(rctx);
 240                 r600_init_atom_start_cs(rctx);
 241                 if (r600_context_init(rctx))
 242                         goto fail;
 243                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 244                 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
 245                                            rctx->family == CHIP_RV620 ||
 246                                            rctx->family == CHIP_RS780 ||
 247                                            rctx->family == CHIP_RS880 ||
 248                                            rctx->family == CHIP_RV710);
 249                 break;
 250         case EVERGREEN:
 251         case CAYMAN:
 252                 evergreen_init_state_functions(rctx);
 253                 evergreen_init_atom_start_cs(rctx);
 254                 evergreen_init_atom_start_compute_cs(rctx);
 255                 if (evergreen_context_init(rctx))
 256                         goto fail;
 257                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 258                 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
 259                                            rctx->family == CHIP_PALM ||
 260                                            rctx->family == CHIP_SUMO ||
 261                                            rctx->family == CHIP_SUMO2 ||
 262                                            rctx->family == CHIP_CAICOS ||
 263                                            rctx->family == CHIP_CAYMAN ||
 264                                            rctx->family == CHIP_ARUBA);
 265                 break;
 266         default:
 267                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 268                 goto fail;
 269         }
 270
 271         rctx->cs = rctx->ws->cs_create(rctx->ws);
 272         rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
 273         r600_emit_atom(rctx, &rctx->start_cs_cmd.atom);
 274
 275         rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
 276                                          PIPE_BIND_INDEX_BUFFER |
 277                                          PIPE_BIND_CONSTANT_BUFFER);
 278         if (!rctx->uploader)
 279                 goto fail;
 280
 281         rctx->blitter = util_blitter_create(&rctx->context);
 282         if (rctx->blitter == NULL)
 283                 goto fail;
 284
 285         r600_get_backend_mask(rctx); /* this emits commands and must be last */
 286
 287         if (rctx->chip_class == R600)
 288                 r600_set_max_scissor(rctx);
 289
 290         rctx->dummy_pixel_shader =
 291                 util_make_fragment_cloneinput_shader(&rctx->context, 0,
 292                                                      TGSI_SEMANTIC_GENERIC,
 293                                                      TGSI_INTERPOLATE_CONSTANT);
 294         rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 295
 296         return &rctx->context;
 297
 298 fail:
 299         r600_destroy_context(&rctx->context);
 300         return NULL;
 301 }
 302
 303 /*
 304  * pipe_screen
 305  */
 306 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 307 {
 308         return "X.Org";
 309 }
 310
 311 static const char *r600_get_family_name(enum radeon_family family)
 312 {
 313         switch(family) {
 314         case CHIP_R600: return "AMD R600";
 315         case CHIP_RV610: return "AMD RV610";
 316         case CHIP_RV630: return "AMD RV630";
 317         case CHIP_RV670: return "AMD RV670";
 318         case CHIP_RV620: return "AMD RV620";
 319         case CHIP_RV635: return "AMD RV635";
 320         case CHIP_RS780: return "AMD RS780";
 321         case CHIP_RS880: return "AMD RS880";
 322         case CHIP_RV770: return "AMD RV770";
 323         case CHIP_RV730: return "AMD RV730";
 324         case CHIP_RV710: return "AMD RV710";
 325         case CHIP_RV740: return "AMD RV740";
 326         case CHIP_CEDAR: return "AMD CEDAR";
 327         case CHIP_REDWOOD: return "AMD REDWOOD";
 328         case CHIP_JUNIPER: return "AMD JUNIPER";
 329         case CHIP_CYPRESS: return "AMD CYPRESS";
 330         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 331         case CHIP_PALM: return "AMD PALM";
 332         case CHIP_SUMO: return "AMD SUMO";
 333         case CHIP_SUMO2: return "AMD SUMO2";
 334         case CHIP_BARTS: return "AMD BARTS";
 335         case CHIP_TURKS: return "AMD TURKS";
 336         case CHIP_CAICOS: return "AMD CAICOS";
 337         case CHIP_CAYMAN: return "AMD CAYMAN";
 338         case CHIP_ARUBA: return "AMD ARUBA";
 339         default: return "AMD unknown";
 340         }
 341 }
 342
 343 static const char* r600_get_name(struct pipe_screen* pscreen)
 344 {
 345         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 346
 347         return r600_get_family_name(rscreen->family);
 348 }
 349
 350 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 351 {
 352         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 353         enum radeon_family family = rscreen->family;
 354
 355         switch (param) {
 356         /* Supported features (boolean caps). */
 357         case PIPE_CAP_NPOT_TEXTURES:
 358         case PIPE_CAP_TWO_SIDED_STENCIL:
 359         case PIPE_CAP_ANISOTROPIC_FILTER:
 360         case PIPE_CAP_POINT_SPRITE:
 361         case PIPE_CAP_OCCLUSION_QUERY:
 362         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 363         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 364         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 365         case PIPE_CAP_TEXTURE_SWIZZLE:
 366         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 367         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 368         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 369         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 370         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 371         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 372         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 373         case PIPE_CAP_SM3:
 374         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 375         case PIPE_CAP_PRIMITIVE_RESTART:
 376         case PIPE_CAP_CONDITIONAL_RENDER:
 377         case PIPE_CAP_TEXTURE_BARRIER:
 378         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 379         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 380         case PIPE_CAP_TGSI_INSTANCEID:
 381         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 382         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 383         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 384         case PIPE_CAP_USER_INDEX_BUFFERS:
 385         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 386         case PIPE_CAP_COMPUTE:
 387         case PIPE_CAP_START_INSTANCE:
 388                 return 1;
 389
 390         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 391                 return 256;
 392
 393         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 394                 return rscreen->glsl_feature_level;
 395
 396         /* Supported except the original R600. */
 397         case PIPE_CAP_INDEP_BLEND_ENABLE:
 398         case PIPE_CAP_INDEP_BLEND_FUNC:
 399                 /* R600 doesn't support per-MRT blends */
 400                 return family == CHIP_R600 ? 0 : 1;
 401
 402         /* Supported on Evergreen. */
 403         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 404                 return family >= CHIP_CEDAR ? 1 : 0;
 405
 406         /* Unsupported features. */
 407         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 408         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 409         case PIPE_CAP_SCALED_RESOLVE:
 410         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 411         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 412         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 413         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 414         case PIPE_CAP_USER_VERTEX_BUFFERS:
 415                 return 0;
 416
 417         /* Stream output. */
 418         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 419                 return rscreen->has_streamout ? 4 : 0;
 420         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 421                 return rscreen->has_streamout ? 1 : 0;
 422         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 423         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 424                 return 16*4;
 425
 426         /* Texturing. */
 427         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 428         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 429         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 430                 if (family >= CHIP_CEDAR)
 431                         return 15;
 432                 else
 433                         return 14;
 434         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 435                 return rscreen->info.drm_minor >= 9 ?
 436                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 437         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 438                 return 32;
 439
 440         /* Render targets. */
 441         case PIPE_CAP_MAX_RENDER_TARGETS:
 442                 /* XXX some r6xx are buggy and can only do 4 */
 443                 return 8;
 444
 445         /* Timer queries, present when the clock frequency is non zero. */
 446         case PIPE_CAP_TIMER_QUERY:
 447                 return rscreen->info.r600_clock_crystal_freq != 0;
 448
 449         case PIPE_CAP_MIN_TEXEL_OFFSET:
 450                 return -8;
 451
 452         case PIPE_CAP_MAX_TEXEL_OFFSET:
 453                 return 7;
 454
 455         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 456                 return family < CHIP_CEDAR ?  1 : 0;
 457         }
 458         return 0;
 459 }
 460
 461 static float r600_get_paramf(struct pipe_screen* pscreen,
 462                              enum pipe_capf param)
 463 {
 464         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 465         enum radeon_family family = rscreen->family;
 466
 467         switch (param) {
 468         case PIPE_CAPF_MAX_LINE_WIDTH:
 469         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 470         case PIPE_CAPF_MAX_POINT_WIDTH:
 471         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 472                 if (family >= CHIP_CEDAR)
 473                         return 16384.0f;
 474                 else
 475                         return 8192.0f;
 476         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 477                 return 16.0f;
 478         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 479                 return 16.0f;
 480         case PIPE_CAPF_GUARD_BAND_LEFT:
 481         case PIPE_CAPF_GUARD_BAND_TOP:
 482         case PIPE_CAPF_GUARD_BAND_RIGHT:
 483         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 484                 return 0.0f;
 485         }
 486         return 0.0f;
 487 }
 488
 489 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 490 {
 491         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 492         switch(shader)
 493         {
 494         case PIPE_SHADER_FRAGMENT:
 495         case PIPE_SHADER_VERTEX:
 496         case PIPE_SHADER_COMPUTE:
 497                 break;
 498         case PIPE_SHADER_GEOMETRY:
 499                 /* XXX: support and enable geometry programs */
 500                 return 0;
 501         default:
 502                 /* XXX: support tessellation on Evergreen */
 503                 return 0;
 504         }
 505
 506         /* XXX: all these should be fixed, since r600 surely supports much more! */
 507         switch (param) {
 508         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 509         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 510         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 511         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 512                 return 16384;
 513         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 514                 return 8; /* XXX */
 515         case PIPE_SHADER_CAP_MAX_INPUTS:
 516                 if(shader == PIPE_SHADER_FRAGMENT)
 517                         return 34;
 518                 else
 519                         return 32;
 520         case PIPE_SHADER_CAP_MAX_TEMPS:
 521                 return 256; /* Max native temporaries. */
 522         case PIPE_SHADER_CAP_MAX_ADDRS:
 523                 /* XXX Isn't this equal to TEMPS? */
 524                 return 1; /* Max native address registers */
 525         case PIPE_SHADER_CAP_MAX_CONSTS:
 526                 return R600_MAX_CONST_BUFFER_SIZE;
 527         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 528                 return R600_MAX_CONST_BUFFERS-1;
 529         case PIPE_SHADER_CAP_MAX_PREDS:
 530                 return 0; /* nothing uses this */
 531         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 532                 return 1;
 533         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 534         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 535         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 536         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 537                 return 1;
 538         case PIPE_SHADER_CAP_SUBROUTINES:
 539                 return 0;
 540         case PIPE_SHADER_CAP_INTEGERS:
 541                 return rscreen->glsl_feature_level >= 130;
 542         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 543                 return 16;
 544         case PIPE_SHADER_CAP_PREFERRED_IR:
 545                 if (shader == PIPE_SHADER_COMPUTE) {
 546                         return PIPE_SHADER_IR_LLVM;
 547                 } else {
 548                         return PIPE_SHADER_IR_TGSI;
 549                 }
 550         }
 551         return 0;
 552 }
 553
 554 static int r600_get_video_param(struct pipe_screen *screen,
 555                                 enum pipe_video_profile profile,
 556                                 enum pipe_video_cap param)
 557 {
 558         switch (param) {
 559         case PIPE_VIDEO_CAP_SUPPORTED:
 560                 return vl_profile_supported(screen, profile);
 561         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 562                 return 1;
 563         case PIPE_VIDEO_CAP_MAX_WIDTH:
 564         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 565                 return vl_video_buffer_max_size(screen);
 566         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 567                 return PIPE_FORMAT_NV12;
 568         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 569                 return false;
 570         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 571                 return false;
 572         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 573                 return true;
 574         default:
 575                 return 0;
 576         }
 577 }
 578
 579 static int r600_get_compute_param(struct pipe_screen *screen,
 580         enum pipe_compute_cap param,
 581         void *ret)
 582 {
 583         //TODO: select these params by asic
 584         switch (param) {
 585         case PIPE_COMPUTE_CAP_IR_TARGET:
 586                 if (ret) {
 587                         strcpy(ret, "r600--");
 588                 }
 589                 return 7 * sizeof(char);
 590
 591         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 592                 if (ret) {
 593                         uint64_t * grid_dimension = ret;
 594                         grid_dimension[0] = 3;
 595                 }
 596                 return 1 * sizeof(uint64_t);
 597
 598         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 599                 if (ret) {
 600                         uint64_t * grid_size = ret;
 601                         grid_size[0] = 65535;
 602                         grid_size[1] = 65535;
 603                         grid_size[2] = 1;
 604                 }
 605                 return 3 * sizeof(uint64_t) ;
 606
 607         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 608                 if (ret) {
 609                         uint64_t * block_size = ret;
 610                         block_size[0] = 256;
 611                         block_size[1] = 256;
 612                         block_size[2] = 256;
 613                 }
 614                 return 3 * sizeof(uint64_t);
 615
 616         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 617                 if (ret) {
 618                         uint64_t * max_threads_per_block = ret;
 619                         *max_threads_per_block = 256;
 620                 }
 621                 return sizeof(uint64_t);
 622
 623         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 624                 if (ret) {
 625                         uint64_t * max_global_size = ret;
 626                         /* XXX: This is what the proprietary driver reports, we
 627                          * may want to use a different value. */
 628                         *max_global_size = 201326592;
 629                 }
 630                 return sizeof(uint64_t);
 631
 632         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 633                 if (ret) {
 634                         uint64_t * max_input_size = ret;
 635                         *max_input_size = 1024;
 636                 }
 637                 return sizeof(uint64_t);
 638
 639         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 640                 if (ret) {
 641                         uint64_t * max_local_size = ret;
 642                         /* XXX: This is what the proprietary driver reports, we
 643                          * may want to use a different value. */
 644                         *max_local_size = 32768;
 645                 }
 646                 return sizeof(uint64_t);
 647
 648         default:
 649                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 650                 return 0;
 651         }
 652 }
 653
 654 static void r600_destroy_screen(struct pipe_screen* pscreen)
 655 {
 656         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 657
 658         if (rscreen == NULL)
 659                 return;
 660
 661         if (rscreen->global_pool) {
 662                 compute_memory_pool_delete(rscreen->global_pool);
 663         }
 664
 665         if (rscreen->fences.bo) {
 666                 struct r600_fence_block *entry, *tmp;
 667
 668                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 669                         LIST_DEL(&entry->head);
 670                         FREE(entry);
 671                 }
 672
 673                 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
 674                 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
 675         }
 676         pipe_mutex_destroy(rscreen->fences.mutex);
 677
 678         rscreen->ws->destroy(rscreen->ws);
 679         FREE(rscreen);
 680 }
 681
 682 static void r600_fence_reference(struct pipe_screen *pscreen,
 683                                  struct pipe_fence_handle **ptr,
 684                                  struct pipe_fence_handle *fence)
 685 {
 686         struct r600_fence **oldf = (struct r600_fence**)ptr;
 687         struct r600_fence *newf = (struct r600_fence*)fence;
 688
 689         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 690                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 691                 pipe_mutex_lock(rscreen->fences.mutex);
 692                 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
 693                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 694                 pipe_mutex_unlock(rscreen->fences.mutex);
 695         }
 696
 697         *ptr = fence;
 698 }
 699
 700 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 701                                     struct pipe_fence_handle *fence)
 702 {
 703         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 704         struct r600_fence *rfence = (struct r600_fence*)fence;
 705
 706         return rscreen->fences.data[rfence->index];
 707 }
 708
 709 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 710                                  struct pipe_fence_handle *fence,
 711                                  uint64_t timeout)
 712 {
 713         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 714         struct r600_fence *rfence = (struct r600_fence*)fence;
 715         int64_t start_time = 0;
 716         unsigned spins = 0;
 717
 718         if (timeout != PIPE_TIMEOUT_INFINITE) {
 719                 start_time = os_time_get();
 720
 721                 /* Convert to microseconds. */
 722                 timeout /= 1000;
 723         }
 724
 725         while (rscreen->fences.data[rfence->index] == 0) {
 726                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
 727                 if (timeout == PIPE_TIMEOUT_INFINITE) {
 728                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
 729                         break;
 730                 }
 731
 732                 /* The dummy BO will be busy until the CS including the fence has completed, or
 733                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
 734                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
 735                         break;
 736
 737                 if (++spins % 256)
 738                         continue;
 739 #ifdef PIPE_OS_UNIX
 740                 sched_yield();
 741 #else
 742                 os_time_sleep(10);
 743 #endif
 744                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 745                     os_time_get() - start_time >= timeout) {
 746                         break;
 747                 }
 748         }
 749
 750         return rscreen->fences.data[rfence->index] != 0;
 751 }
 752
 753 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 754 {
 755         switch ((tiling_config & 0xe) >> 1) {
 756         case 0:
 757                 rscreen->tiling_info.num_channels = 1;
 758                 break;
 759         case 1:
 760                 rscreen->tiling_info.num_channels = 2;
 761                 break;
 762         case 2:
 763                 rscreen->tiling_info.num_channels = 4;
 764                 break;
 765         case 3:
 766                 rscreen->tiling_info.num_channels = 8;
 767                 break;
 768         default:
 769                 return -EINVAL;
 770         }
 771
 772         switch ((tiling_config & 0x30) >> 4) {
 773         case 0:
 774                 rscreen->tiling_info.num_banks = 4;
 775                 break;
 776         case 1:
 777                 rscreen->tiling_info.num_banks = 8;
 778                 break;
 779         default:
 780                 return -EINVAL;
 781
 782         }
 783         switch ((tiling_config & 0xc0) >> 6) {
 784         case 0:
 785                 rscreen->tiling_info.group_bytes = 256;
 786                 break;
 787         case 1:
 788                 rscreen->tiling_info.group_bytes = 512;
 789                 break;
 790         default:
 791                 return -EINVAL;
 792         }
 793         return 0;
 794 }
 795
 796 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 797 {
 798         switch (tiling_config & 0xf) {
 799         case 0:
 800                 rscreen->tiling_info.num_channels = 1;
 801                 break;
 802         case 1:
 803                 rscreen->tiling_info.num_channels = 2;
 804                 break;
 805         case 2:
 806                 rscreen->tiling_info.num_channels = 4;
 807                 break;
 808         case 3:
 809                 rscreen->tiling_info.num_channels = 8;
 810                 break;
 811         default:
 812                 return -EINVAL;
 813         }
 814
 815         switch ((tiling_config & 0xf0) >> 4) {
 816         case 0:
 817                 rscreen->tiling_info.num_banks = 4;
 818                 break;
 819         case 1:
 820                 rscreen->tiling_info.num_banks = 8;
 821                 break;
 822         case 2:
 823                 rscreen->tiling_info.num_banks = 16;
 824                 break;
 825         default:
 826                 return -EINVAL;
 827         }
 828
 829         switch ((tiling_config & 0xf00) >> 8) {
 830         case 0:
 831                 rscreen->tiling_info.group_bytes = 256;
 832                 break;
 833         case 1:
 834                 rscreen->tiling_info.group_bytes = 512;
 835                 break;
 836         default:
 837                 return -EINVAL;
 838         }
 839         return 0;
 840 }
 841
 842 static int r600_init_tiling(struct r600_screen *rscreen)
 843 {
 844         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 845
 846         /* set default group bytes, overridden by tiling info ioctl */
 847         if (rscreen->chip_class <= R700) {
 848                 rscreen->tiling_info.group_bytes = 256;
 849         } else {
 850                 rscreen->tiling_info.group_bytes = 512;
 851         }
 852
 853         if (!tiling_config)
 854                 return 0;
 855
 856         if (rscreen->chip_class <= R700) {
 857                 return r600_interpret_tiling(rscreen, tiling_config);
 858         } else {
 859                 return evergreen_interpret_tiling(rscreen, tiling_config);
 860         }
 861 }
 862
 863 static unsigned radeon_family_from_device(unsigned device)
 864 {
 865         switch (device) {
 866 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 867 #include "pci_ids/r600_pci_ids.h"
 868 #undef CHIPSET
 869         default:
 870                 return CHIP_UNKNOWN;
 871         }
 872 }
 873
 874 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 875 {
 876         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 877
 878         if (rscreen == NULL) {
 879                 return NULL;
 880         }
 881
 882         rscreen->ws = ws;
 883         ws->query_info(ws, &rscreen->info);
 884
 885         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 886         if (rscreen->family == CHIP_UNKNOWN) {
 887                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 888                 FREE(rscreen);
 889                 return NULL;
 890         }
 891
 892         /* setup class */
 893         if (rscreen->family >= CHIP_CAYMAN) {
 894                 rscreen->chip_class = CAYMAN;
 895         } else if (rscreen->family >= CHIP_CEDAR) {
 896                 rscreen->chip_class = EVERGREEN;
 897         } else if (rscreen->family >= CHIP_RV770) {
 898                 rscreen->chip_class = R700;
 899         } else {
 900                 rscreen->chip_class = R600;
 901         }
 902
 903         /* Figure out streamout kernel support. */
 904         switch (rscreen->chip_class) {
 905         case R600:
 906         case EVERGREEN:
 907                 rscreen->has_streamout = rscreen->info.drm_minor >= 13;
 908                 break;
 909         case R700:
 910                 rscreen->has_streamout = rscreen->info.drm_minor >= 17;
 911                 break;
 912         /* TODO: Cayman */
 913         default:
 914                 rscreen->has_streamout = debug_get_bool_option("R600_STREAMOUT", FALSE);
 915         }
 916
 917         if (r600_init_tiling(rscreen)) {
 918                 FREE(rscreen);
 919                 return NULL;
 920         }
 921
 922         rscreen->screen.destroy = r600_destroy_screen;
 923         rscreen->screen.get_name = r600_get_name;
 924         rscreen->screen.get_vendor = r600_get_vendor;
 925         rscreen->screen.get_param = r600_get_param;
 926         rscreen->screen.get_shader_param = r600_get_shader_param;
 927         rscreen->screen.get_paramf = r600_get_paramf;
 928         rscreen->screen.get_video_param = r600_get_video_param;
 929         rscreen->screen.get_compute_param = r600_get_compute_param;
 930
 931         if (rscreen->chip_class >= EVERGREEN) {
 932                 rscreen->screen.is_format_supported = evergreen_is_format_supported;
 933         } else {
 934                 rscreen->screen.is_format_supported = r600_is_format_supported;
 935         }
 936         rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 937         rscreen->screen.context_create = r600_create_context;
 938         rscreen->screen.fence_reference = r600_fence_reference;
 939         rscreen->screen.fence_signalled = r600_fence_signalled;
 940         rscreen->screen.fence_finish = r600_fence_finish;
 941         r600_init_screen_resource_functions(&rscreen->screen);
 942
 943         util_format_s3tc_init();
 944
 945         rscreen->fences.bo = NULL;
 946         rscreen->fences.data = NULL;
 947         rscreen->fences.next_index = 0;
 948         LIST_INITHEAD(&rscreen->fences.pool);
 949         LIST_INITHEAD(&rscreen->fences.blocks);
 950         pipe_mutex_init(rscreen->fences.mutex);
 951
 952         rscreen->use_surface_alloc = debug_get_bool_option("R600_SURF", TRUE);
 953         rscreen->glsl_feature_level = debug_get_bool_option("R600_GLSL130", TRUE) ? 130 : 120;
 954
 955         rscreen->global_pool = compute_memory_pool_new(1024*16, rscreen);
 956
 957         return &rscreen->screen;
 958 }