src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_blitter.h"
  34 #include "util/u_debug.h"
  35 #include "util/u_memory.h"
  36 #include "util/u_simple_shaders.h"
  37 #include "util/u_upload_mgr.h"
  38 #include "util/u_math.h"
  39 #include "vl/vl_decoder.h"
  40 #include "vl/vl_video_buffer.h"
  41 #include "radeon/radeon_video.h"
  42 #include "radeon/radeon_uvd.h"
  43 #include "os/os_time.h"
  44
  45 static const struct debug_named_value r600_debug_options[] = {
  46         /* features */
  47 #if defined(R600_USE_LLVM)
  48         { "nollvm", DBG_NO_LLVM, "Disable the LLVM shader compiler" },
  49 #endif
  50         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  51
  52         /* shader backend */
  53         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  54         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  55         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  56         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  57         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  58         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  59         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  60         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  61
  62         DEBUG_NAMED_VALUE_END /* must be last */
  63 };
  64
  65 /*
  66  * pipe_context
  67  */
  68
  69 static void r600_flush(struct pipe_context *ctx, unsigned flags)
  70 {
  71         struct r600_context *rctx = (struct r600_context *)ctx;
  72         struct pipe_query *render_cond = NULL;
  73         unsigned render_cond_mode = 0;
  74         boolean render_cond_cond = FALSE;
  75
  76         if (rctx->b.rings.gfx.cs->cdw == rctx->b.initial_gfx_cs_size)
  77                 return;
  78
  79         rctx->b.rings.gfx.flushing = true;
  80         /* Disable render condition. */
  81         if (rctx->b.current_render_cond) {
  82                 render_cond = rctx->b.current_render_cond;
  83                 render_cond_cond = rctx->b.current_render_cond_cond;
  84                 render_cond_mode = rctx->b.current_render_cond_mode;
  85                 ctx->render_condition(ctx, NULL, FALSE, 0);
  86         }
  87
  88         r600_context_flush(rctx, flags);
  89         rctx->b.rings.gfx.flushing = false;
  90         r600_begin_new_cs(rctx);
  91
  92         /* Re-enable render condition. */
  93         if (render_cond) {
  94                 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
  95         }
  96
  97         rctx->b.initial_gfx_cs_size = rctx->b.rings.gfx.cs->cdw;
  98 }
  99
 100 static void r600_flush_from_st(struct pipe_context *ctx,
 101                                struct pipe_fence_handle **fence,
 102                                unsigned flags)
 103 {
 104         struct r600_context *rctx = (struct r600_context *)ctx;
 105         unsigned fflags;
 106
 107         fflags = flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0;
 108         if (fence) {
 109                 *fence = rctx->b.ws->cs_create_fence(rctx->b.rings.gfx.cs);
 110         }
 111         /* flush gfx & dma ring, order does not matter as only one can be live */
 112         if (rctx->b.rings.dma.cs) {
 113                 rctx->b.rings.dma.flush(rctx, fflags);
 114         }
 115         rctx->b.rings.gfx.flush(rctx, fflags);
 116 }
 117
 118 static void r600_flush_gfx_ring(void *ctx, unsigned flags)
 119 {
 120         r600_flush((struct pipe_context*)ctx, flags);
 121 }
 122
 123 static void r600_destroy_context(struct pipe_context *context)
 124 {
 125         struct r600_context *rctx = (struct r600_context *)context;
 126
 127         r600_isa_destroy(rctx->isa);
 128
 129         r600_sb_context_destroy(rctx->sb_context);
 130
 131         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
 132         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
 133
 134         if (rctx->dummy_pixel_shader) {
 135                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 136         }
 137         if (rctx->custom_dsa_flush) {
 138                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
 139         }
 140         if (rctx->custom_blend_resolve) {
 141                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
 142         }
 143         if (rctx->custom_blend_decompress) {
 144                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
 145         }
 146         if (rctx->custom_blend_fastclear) {
 147                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
 148         }
 149         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 150
 151         if (rctx->blitter) {
 152                 util_blitter_destroy(rctx->blitter);
 153         }
 154         if (rctx->allocator_fetch_shader) {
 155                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 156         }
 157
 158         r600_release_command_buffer(&rctx->start_cs_cmd);
 159
 160         FREE(rctx->start_compute_cs_cmd.buf);
 161
 162         r600_common_context_cleanup(&rctx->b);
 163         FREE(rctx);
 164 }
 165
 166 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 167 {
 168         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 169         struct r600_screen* rscreen = (struct r600_screen *)screen;
 170         struct radeon_winsys *ws = rscreen->b.ws;
 171
 172         if (rctx == NULL)
 173                 return NULL;
 174
 175         rctx->b.b.screen = screen;
 176         rctx->b.b.priv = priv;
 177         rctx->b.b.destroy = r600_destroy_context;
 178         rctx->b.b.flush = r600_flush_from_st;
 179
 180         if (!r600_common_context_init(&rctx->b, &rscreen->b))
 181                 goto fail;
 182
 183         rctx->screen = rscreen;
 184         rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
 185
 186         r600_init_blit_functions(rctx);
 187
 188         if (rscreen->b.info.has_uvd) {
 189                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 190                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 191         } else {
 192                 rctx->b.b.create_video_codec = vl_create_decoder;
 193                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 194         }
 195
 196         r600_init_common_state_functions(rctx);
 197
 198         switch (rctx->b.chip_class) {
 199         case R600:
 200         case R700:
 201                 r600_init_state_functions(rctx);
 202                 r600_init_atom_start_cs(rctx);
 203                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 204                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 205                                                                       : r600_create_resolve_blend(rctx);
 206                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 207                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 208                                            rctx->b.family == CHIP_RV620 ||
 209                                            rctx->b.family == CHIP_RS780 ||
 210                                            rctx->b.family == CHIP_RS880 ||
 211                                            rctx->b.family == CHIP_RV710);
 212                 break;
 213         case EVERGREEN:
 214         case CAYMAN:
 215                 evergreen_init_state_functions(rctx);
 216                 evergreen_init_atom_start_cs(rctx);
 217                 evergreen_init_atom_start_compute_cs(rctx);
 218                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 219                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 220                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 221                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 222                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 223                                            rctx->b.family == CHIP_PALM ||
 224                                            rctx->b.family == CHIP_SUMO ||
 225                                            rctx->b.family == CHIP_SUMO2 ||
 226                                            rctx->b.family == CHIP_CAICOS ||
 227                                            rctx->b.family == CHIP_CAYMAN ||
 228                                            rctx->b.family == CHIP_ARUBA);
 229                 break;
 230         default:
 231                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 232                 goto fail;
 233         }
 234
 235         rctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX,
 236                                              r600_flush_gfx_ring, rctx,
 237                                              rscreen->b.trace_bo ?
 238                                                      rscreen->b.trace_bo->cs_buf : NULL);
 239         rctx->b.rings.gfx.flush = r600_flush_gfx_ring;
 240         rctx->b.rings.gfx.flushing = false;
 241
 242         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
 243                                                              0, PIPE_USAGE_DEFAULT, FALSE);
 244         if (!rctx->allocator_fetch_shader)
 245                 goto fail;
 246
 247         rctx->isa = calloc(1, sizeof(struct r600_isa));
 248         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 249                 goto fail;
 250
 251         rctx->blitter = util_blitter_create(&rctx->b.b);
 252         if (rctx->blitter == NULL)
 253                 goto fail;
 254         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 255         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 256
 257         r600_begin_new_cs(rctx);
 258         r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
 259
 260         rctx->dummy_pixel_shader =
 261                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 262                                                      TGSI_SEMANTIC_GENERIC,
 263                                                      TGSI_INTERPOLATE_CONSTANT);
 264         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 265
 266         return &rctx->b.b;
 267
 268 fail:
 269         r600_destroy_context(&rctx->b.b);
 270         return NULL;
 271 }
 272
 273 /*
 274  * pipe_screen
 275  */
 276
 277 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 278 {
 279         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 280         enum radeon_family family = rscreen->b.family;
 281
 282         switch (param) {
 283         /* Supported features (boolean caps). */
 284         case PIPE_CAP_NPOT_TEXTURES:
 285         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 286         case PIPE_CAP_TWO_SIDED_STENCIL:
 287         case PIPE_CAP_ANISOTROPIC_FILTER:
 288         case PIPE_CAP_POINT_SPRITE:
 289         case PIPE_CAP_OCCLUSION_QUERY:
 290         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 291         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 292         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 293         case PIPE_CAP_TEXTURE_SWIZZLE:
 294         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 295         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 296         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 297         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 298         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 299         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 300         case PIPE_CAP_SM3:
 301         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 302         case PIPE_CAP_PRIMITIVE_RESTART:
 303         case PIPE_CAP_CONDITIONAL_RENDER:
 304         case PIPE_CAP_TEXTURE_BARRIER:
 305         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 306         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 307         case PIPE_CAP_TGSI_INSTANCEID:
 308         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 309         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 310         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 311         case PIPE_CAP_USER_INDEX_BUFFERS:
 312         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 313         case PIPE_CAP_START_INSTANCE:
 314         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 315         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 316         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 317         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 318         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 319         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 320                 return 1;
 321
 322         case PIPE_CAP_COMPUTE:
 323                 return rscreen->b.chip_class > R700;
 324
 325         case PIPE_CAP_TGSI_TEXCOORD:
 326                 return 0;
 327
 328         case PIPE_CAP_FAKE_SW_MSAA:
 329                 return 0;
 330
 331         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 332                 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
 333
 334         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 335                 return R600_MAP_BUFFER_ALIGNMENT;
 336
 337         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 338                 return 256;
 339
 340         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 341                 return 1;
 342
 343         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 344                 if (family >= CHIP_CEDAR)
 345                    return 330;
 346                 /* pre-evergreen geom shaders need newer kernel */
 347                 if (rscreen->b.info.drm_minor >= 37)
 348                    return 330;
 349                 return 140;
 350
 351         /* Supported except the original R600. */
 352         case PIPE_CAP_INDEP_BLEND_ENABLE:
 353         case PIPE_CAP_INDEP_BLEND_FUNC:
 354                 /* R600 doesn't support per-MRT blends */
 355                 return family == CHIP_R600 ? 0 : 1;
 356
 357         /* Supported on Evergreen. */
 358         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 359         case PIPE_CAP_CUBE_MAP_ARRAY:
 360         case PIPE_CAP_TGSI_VS_LAYER:
 361                 return family >= CHIP_CEDAR ? 1 : 0;
 362
 363         /* Unsupported features. */
 364         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 365         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 366         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 367         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 368         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 369         case PIPE_CAP_USER_VERTEX_BUFFERS:
 370         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 371         case PIPE_CAP_TEXTURE_GATHER_SM5:
 372         case PIPE_CAP_TEXTURE_QUERY_LOD:
 373                 return 0;
 374
 375         /* Stream output. */
 376         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 377                 return rscreen->b.has_streamout ? 4 : 0;
 378         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 379                 return rscreen->b.has_streamout ? 1 : 0;
 380         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 381         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 382                 return 32*4;
 383
 384         /* Geometry shader output. */
 385         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 386                 return 1024;
 387         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 388                 return 16384;
 389
 390         /* Texturing. */
 391         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 392         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 393                 if (family >= CHIP_CEDAR)
 394                         return 15;
 395                 else
 396                         return 14;
 397         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 398                 /* textures support 8192, but layered rendering supports 2048 */
 399                 return 12;
 400         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 401                 /* textures support 8192, but layered rendering supports 2048 */
 402                 return rscreen->b.info.drm_minor >= 9 ? 2048 : 0;
 403
 404         /* Render targets. */
 405         case PIPE_CAP_MAX_RENDER_TARGETS:
 406                 /* XXX some r6xx are buggy and can only do 4 */
 407                 return 8;
 408
 409         case PIPE_CAP_MAX_VIEWPORTS:
 410                 return 16;
 411
 412         /* Timer queries, present when the clock frequency is non zero. */
 413         case PIPE_CAP_QUERY_TIME_ELAPSED:
 414                 return rscreen->b.info.r600_clock_crystal_freq != 0;
 415         case PIPE_CAP_QUERY_TIMESTAMP:
 416                 return rscreen->b.info.drm_minor >= 20 &&
 417                        rscreen->b.info.r600_clock_crystal_freq != 0;
 418
 419         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 420         case PIPE_CAP_MIN_TEXEL_OFFSET:
 421                 return -8;
 422
 423         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 424         case PIPE_CAP_MAX_TEXEL_OFFSET:
 425                 return 7;
 426
 427         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 428                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 429         case PIPE_CAP_ENDIANNESS:
 430                 return PIPE_ENDIAN_LITTLE;
 431         }
 432         return 0;
 433 }
 434
 435 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 436 {
 437         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 438
 439         switch(shader)
 440         {
 441         case PIPE_SHADER_FRAGMENT:
 442         case PIPE_SHADER_VERTEX:
 443         case PIPE_SHADER_COMPUTE:
 444                 break;
 445         case PIPE_SHADER_GEOMETRY:
 446                 if (rscreen->b.family >= CHIP_CEDAR)
 447                         break;
 448                 /* pre-evergreen geom shaders need newer kernel */
 449                 if (rscreen->b.info.drm_minor >= 37)
 450                         break;
 451                 return 0;
 452         default:
 453                 /* XXX: support tessellation on Evergreen */
 454                 return 0;
 455         }
 456
 457         switch (param) {
 458         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 459         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 460         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 461         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 462                 return 16384;
 463         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 464                 return 32;
 465         case PIPE_SHADER_CAP_MAX_INPUTS:
 466                 return 32;
 467         case PIPE_SHADER_CAP_MAX_TEMPS:
 468                 return 256; /* Max native temporaries. */
 469         case PIPE_SHADER_CAP_MAX_ADDRS:
 470                 /* XXX Isn't this equal to TEMPS? */
 471                 return 1; /* Max native address registers */
 472         case PIPE_SHADER_CAP_MAX_CONSTS:
 473                 return R600_MAX_CONST_BUFFER_SIZE;
 474         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 475                 return R600_MAX_USER_CONST_BUFFERS;
 476         case PIPE_SHADER_CAP_MAX_PREDS:
 477                 return 0; /* nothing uses this */
 478         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 479                 return 1;
 480         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 481                 return 0;
 482         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 483         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 484         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 485         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 486                 return 1;
 487         case PIPE_SHADER_CAP_SUBROUTINES:
 488                 return 0;
 489         case PIPE_SHADER_CAP_INTEGERS:
 490                 return 1;
 491         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 492         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 493                 return 16;
 494         case PIPE_SHADER_CAP_PREFERRED_IR:
 495                 if (shader == PIPE_SHADER_COMPUTE) {
 496                         return PIPE_SHADER_IR_LLVM;
 497                 } else {
 498                         return PIPE_SHADER_IR_TGSI;
 499                 }
 500         }
 501         return 0;
 502 }
 503
 504 static void r600_destroy_screen(struct pipe_screen* pscreen)
 505 {
 506         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 507
 508         if (rscreen == NULL)
 509                 return;
 510
 511         if (!rscreen->b.ws->unref(rscreen->b.ws))
 512                 return;
 513
 514         if (rscreen->global_pool) {
 515                 compute_memory_pool_delete(rscreen->global_pool);
 516         }
 517
 518         r600_destroy_common_screen(&rscreen->b);
 519 }
 520
 521 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 522                                                   const struct pipe_resource *templ)
 523 {
 524         if (templ->target == PIPE_BUFFER &&
 525             (templ->bind & PIPE_BIND_GLOBAL))
 526                 return r600_compute_global_buffer_create(screen, templ);
 527
 528         return r600_resource_create_common(screen, templ);
 529 }
 530
 531 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 532 {
 533         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 534
 535         if (rscreen == NULL) {
 536                 return NULL;
 537         }
 538
 539         /* Set functions first. */
 540         rscreen->b.b.context_create = r600_create_context;
 541         rscreen->b.b.destroy = r600_destroy_screen;
 542         rscreen->b.b.get_param = r600_get_param;
 543         rscreen->b.b.get_shader_param = r600_get_shader_param;
 544         rscreen->b.b.resource_create = r600_resource_create;
 545
 546         if (!r600_common_screen_init(&rscreen->b, ws)) {
 547                 FREE(rscreen);
 548                 return NULL;
 549         }
 550
 551         if (rscreen->b.info.chip_class >= EVERGREEN) {
 552                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 553         } else {
 554                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 555         }
 556
 557         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 558         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 559                 rscreen->b.debug_flags |= DBG_COMPUTE;
 560         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 561                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 562         if (debug_get_bool_option("R600_HYPERZ", FALSE))
 563                 rscreen->b.debug_flags |= DBG_HYPERZ;
 564         if (!debug_get_bool_option("R600_LLVM", TRUE))
 565                 rscreen->b.debug_flags |= DBG_NO_LLVM;
 566
 567         if (rscreen->b.family == CHIP_UNKNOWN) {
 568                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 569                 FREE(rscreen);
 570                 return NULL;
 571         }
 572
 573         /* Figure out streamout kernel support. */
 574         switch (rscreen->b.chip_class) {
 575         case R600:
 576                 if (rscreen->b.family < CHIP_RS780) {
 577                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 578                 } else {
 579                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 580                 }
 581                 break;
 582         case R700:
 583                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 584                 break;
 585         case EVERGREEN:
 586         case CAYMAN:
 587                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 588                 break;
 589         default:
 590                 rscreen->b.has_streamout = FALSE;
 591                 break;
 592         }
 593
 594         /* MSAA support. */
 595         switch (rscreen->b.chip_class) {
 596         case R600:
 597         case R700:
 598                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 599                 rscreen->has_compressed_msaa_texturing = false;
 600                 break;
 601         case EVERGREEN:
 602                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 603                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 604                 break;
 605         case CAYMAN:
 606                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 607                 rscreen->has_compressed_msaa_texturing = true;
 608                 break;
 609         default:
 610                 rscreen->has_msaa = FALSE;
 611                 rscreen->has_compressed_msaa_texturing = false;
 612         }
 613
 614         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 615                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 616
 617         rscreen->global_pool = compute_memory_pool_new(rscreen);
 618
 619         /* Create the auxiliary context. This must be done last. */
 620         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
 621
 622 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 623         struct pipe_resource templ = {};
 624
 625         templ.width0 = 4;
 626         templ.height0 = 2048;
 627         templ.depth0 = 1;
 628         templ.array_size = 1;
 629         templ.target = PIPE_TEXTURE_2D;
 630         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 631         templ.usage = PIPE_USAGE_DEFAULT;
 632
 633         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 634         unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
 635
 636         memset(map, 0, 256);
 637
 638         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 639         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 640         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 641         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 642         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 643
 644         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 645
 646         int i;
 647         for (i = 0; i < 256; i++) {
 648                 printf("%02X", map[i]);
 649                 if (i % 16 == 15)
 650                         printf("\n");
 651         }
 652 #endif
 653
 654         return &rscreen->b.b;
 655 }