68b625cc3b4ec59997045dc508fadc736df5765b
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include <pipe/p_defines.h>
26 #include <pipe/p_state.h>
27 #include <pipe/p_context.h>
28 #include <tgsi/tgsi_scan.h>
29 #include <tgsi/tgsi_parse.h>
30 #include <tgsi/tgsi_util.h>
31 #include <util/u_blitter.h>
32 #include <util/u_double_list.h>
33 #include <util/u_transfer.h>
34 #include <util/u_surface.h>
35 #include <util/u_pack_color.h>
36 #include <util/u_memory.h>
37 #include <util/u_inlines.h>
38 #include <pipebuffer/pb_buffer.h>
39 #include "r600.h"
40 #include "r600d.h"
41 #include "r600_resource.h"
42 #include "r600_shader.h"
43 #include "r600_pipe.h"
44 #include "r600_state_inlines.h"
45 #include "r600_video_context.h"
46
47 /*
48 * pipe_context
49 */
50 static void r600_flush(struct pipe_context *ctx, unsigned flags,
51 struct pipe_fence_handle **fence)
52 {
53 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
54 #if 0
55 static int dc = 0;
56 char dname[256];
57 #endif
58
59 if (!rctx->ctx.pm4_cdwords)
60 return;
61
62 #if 0
63 sprintf(dname, "gallium-%08d.bof", dc);
64 if (dc < 20) {
65 r600_context_dump_bof(&rctx->ctx, dname);
66 R600_ERR("dumped %s\n", dname);
67 }
68 dc++;
69 #endif
70 r600_context_flush(&rctx->ctx);
71
72 r600_upload_flush(rctx->rupload_vb);
73 r600_upload_flush(rctx->rupload_const);
74 }
75
76 static void r600_destroy_context(struct pipe_context *context)
77 {
78 struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
79
80 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
81
82 r600_end_vertex_translate(rctx);
83
84 r600_context_fini(&rctx->ctx);
85
86 util_blitter_destroy(rctx->blitter);
87
88 for (int i = 0; i < R600_PIPE_NSTATES; i++) {
89 free(rctx->states[i]);
90 }
91
92 r600_upload_destroy(rctx->rupload_vb);
93 r600_upload_destroy(rctx->rupload_const);
94
95 if (rctx->tran.translate_cache)
96 translate_cache_destroy(rctx->tran.translate_cache);
97
98 FREE(rctx->ps_resource);
99 FREE(rctx->vs_resource);
100 FREE(rctx);
101 }
102
103 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
104 {
105 struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
106 struct r600_screen* rscreen = (struct r600_screen *)screen;
107 enum chip_class class;
108
109 if (rctx == NULL)
110 return NULL;
111 rctx->context.winsys = rscreen->screen.winsys;
112 rctx->context.screen = screen;
113 rctx->context.priv = priv;
114 rctx->context.destroy = r600_destroy_context;
115 rctx->context.flush = r600_flush;
116
117 /* Easy accessing of screen/winsys. */
118 rctx->screen = rscreen;
119 rctx->radeon = rscreen->radeon;
120 rctx->family = r600_get_family(rctx->radeon);
121
122 r600_init_blit_functions(rctx);
123 r600_init_query_functions(rctx);
124 r600_init_context_resource_functions(rctx);
125 r600_init_surface_functions(rctx);
126
127 switch (r600_get_family(rctx->radeon)) {
128 case CHIP_R600:
129 case CHIP_RV610:
130 case CHIP_RV630:
131 case CHIP_RV670:
132 case CHIP_RV620:
133 case CHIP_RV635:
134 case CHIP_RS780:
135 case CHIP_RS880:
136 case CHIP_RV770:
137 case CHIP_RV730:
138 case CHIP_RV710:
139 case CHIP_RV740:
140 rctx->context.draw_vbo = r600_draw_vbo;
141 r600_init_state_functions(rctx);
142 if (r600_context_init(&rctx->ctx, rctx->radeon)) {
143 r600_destroy_context(&rctx->context);
144 return NULL;
145 }
146 r600_init_config(rctx);
147 break;
148 case CHIP_CEDAR:
149 case CHIP_REDWOOD:
150 case CHIP_JUNIPER:
151 case CHIP_CYPRESS:
152 case CHIP_HEMLOCK:
153 case CHIP_PALM:
154 case CHIP_BARTS:
155 case CHIP_TURKS:
156 case CHIP_CAICOS:
157 rctx->context.draw_vbo = evergreen_draw;
158 evergreen_init_state_functions(rctx);
159 if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
160 r600_destroy_context(&rctx->context);
161 return NULL;
162 }
163 evergreen_init_config(rctx);
164 break;
165 default:
166 R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
167 r600_destroy_context(&rctx->context);
168 return NULL;
169 }
170
171 rctx->rupload_vb = r600_upload_create(rctx, 128 * 1024, 16);
172 if (rctx->rupload_vb == NULL) {
173 r600_destroy_context(&rctx->context);
174 return NULL;
175 }
176
177 rctx->rupload_const = r600_upload_create(rctx, 128 * 1024, 256);
178 if (rctx->rupload_const == NULL) {
179 r600_destroy_context(&rctx->context);
180 return NULL;
181 }
182
183 rctx->blitter = util_blitter_create(&rctx->context);
184 if (rctx->blitter == NULL) {
185 FREE(rctx);
186 return NULL;
187 }
188
189 rctx->tran.translate_cache = translate_cache_create();
190 if (rctx->tran.translate_cache == NULL) {
191 FREE(rctx);
192 return NULL;
193 }
194
195 rctx->vs_resource = CALLOC(R600_RESOURCE_ARRAY_SIZE, sizeof(struct r600_pipe_state));
196 if (!rctx->vs_resource) {
197 FREE(rctx);
198 return NULL;
199 }
200
201 rctx->ps_resource = CALLOC(R600_RESOURCE_ARRAY_SIZE, sizeof(struct r600_pipe_state));
202 if (!rctx->ps_resource) {
203 FREE(rctx);
204 return NULL;
205 }
206
207 class = r600_get_family_class(rctx->radeon);
208 if (class == R600 || class == R700)
209 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
210 else
211 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
212
213 return &rctx->context;
214 }
215
216 /*
217 * pipe_screen
218 */
219 static const char* r600_get_vendor(struct pipe_screen* pscreen)
220 {
221 return "X.Org";
222 }
223
224 static const char *r600_get_family_name(enum radeon_family family)
225 {
226 switch(family) {
227 case CHIP_R600: return "AMD R600";
228 case CHIP_RV610: return "AMD RV610";
229 case CHIP_RV630: return "AMD RV630";
230 case CHIP_RV670: return "AMD RV670";
231 case CHIP_RV620: return "AMD RV620";
232 case CHIP_RV635: return "AMD RV635";
233 case CHIP_RS780: return "AMD RS780";
234 case CHIP_RS880: return "AMD RS880";
235 case CHIP_RV770: return "AMD RV770";
236 case CHIP_RV730: return "AMD RV730";
237 case CHIP_RV710: return "AMD RV710";
238 case CHIP_RV740: return "AMD RV740";
239 case CHIP_CEDAR: return "AMD CEDAR";
240 case CHIP_REDWOOD: return "AMD REDWOOD";
241 case CHIP_JUNIPER: return "AMD JUNIPER";
242 case CHIP_CYPRESS: return "AMD CYPRESS";
243 case CHIP_HEMLOCK: return "AMD HEMLOCK";
244 case CHIP_PALM: return "AMD PALM";
245 case CHIP_BARTS: return "AMD BARTS";
246 case CHIP_TURKS: return "AMD TURKS";
247 case CHIP_CAICOS: return "AMD CAICOS";
248 default: return "AMD unknown";
249 }
250 }
251
252 static const char* r600_get_name(struct pipe_screen* pscreen)
253 {
254 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
255 enum radeon_family family = r600_get_family(rscreen->radeon);
256
257 return r600_get_family_name(family);
258 }
259
260 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
261 {
262 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
263 enum radeon_family family = r600_get_family(rscreen->radeon);
264
265 switch (param) {
266 /* Supported features (boolean caps). */
267 case PIPE_CAP_NPOT_TEXTURES:
268 case PIPE_CAP_TWO_SIDED_STENCIL:
269 case PIPE_CAP_GLSL:
270 case PIPE_CAP_DUAL_SOURCE_BLEND:
271 case PIPE_CAP_ANISOTROPIC_FILTER:
272 case PIPE_CAP_POINT_SPRITE:
273 case PIPE_CAP_OCCLUSION_QUERY:
274 case PIPE_CAP_TEXTURE_SHADOW_MAP:
275 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
276 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
277 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
278 case PIPE_CAP_SM3:
279 case PIPE_CAP_TEXTURE_SWIZZLE:
280 case PIPE_CAP_INDEP_BLEND_ENABLE:
281 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
282 case PIPE_CAP_DEPTH_CLAMP:
283 case PIPE_CAP_SHADER_STENCIL_EXPORT:
284 return 1;
285
286 /* Unsupported features (boolean caps). */
287 case PIPE_CAP_TIMER_QUERY:
288 case PIPE_CAP_STREAM_OUTPUT:
289 case PIPE_CAP_PRIMITIVE_RESTART:
290 case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */
291 case PIPE_CAP_INSTANCED_DRAWING:
292 return 0;
293
294 /* Texturing. */
295 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
296 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
297 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
298 if (family >= CHIP_CEDAR)
299 return 15;
300 else
301 return 14;
302 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
303 /* FIXME allow this once infrastructure is there */
304 return 16;
305 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
306 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
307 return 16;
308
309 /* Render targets. */
310 case PIPE_CAP_MAX_RENDER_TARGETS:
311 /* FIXME some r6xx are buggy and can only do 4 */
312 return 8;
313
314 /* Fragment coordinate conventions. */
315 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
316 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
317 return 1;
318 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
319 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
320 return 0;
321
322 default:
323 R600_ERR("r600: unknown param %d\n", param);
324 return 0;
325 }
326 }
327
328 static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
329 {
330 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
331 enum radeon_family family = r600_get_family(rscreen->radeon);
332
333 switch (param) {
334 case PIPE_CAP_MAX_LINE_WIDTH:
335 case PIPE_CAP_MAX_LINE_WIDTH_AA:
336 case PIPE_CAP_MAX_POINT_WIDTH:
337 case PIPE_CAP_MAX_POINT_WIDTH_AA:
338 if (family >= CHIP_CEDAR)
339 return 16384.0f;
340 else
341 return 8192.0f;
342 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
343 return 16.0f;
344 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
345 return 16.0f;
346 default:
347 R600_ERR("r600: unsupported paramf %d\n", param);
348 return 0.0f;
349 }
350 }
351
352 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
353 {
354 switch(shader)
355 {
356 case PIPE_SHADER_FRAGMENT:
357 case PIPE_SHADER_VERTEX:
358 break;
359 case PIPE_SHADER_GEOMETRY:
360 /* TODO: support and enable geometry programs */
361 return 0;
362 default:
363 /* TODO: support tessellation on Evergreen */
364 return 0;
365 }
366
367 /* TODO: all these should be fixed, since r600 surely supports much more! */
368 switch (param) {
369 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
370 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
371 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
372 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
373 return 16384;
374 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
375 return 8; /* FIXME */
376 case PIPE_SHADER_CAP_MAX_INPUTS:
377 if(shader == PIPE_SHADER_FRAGMENT)
378 return 10;
379 else
380 return 16;
381 case PIPE_SHADER_CAP_MAX_TEMPS:
382 return 256; //max native temporaries
383 case PIPE_SHADER_CAP_MAX_ADDRS:
384 return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */
385 case PIPE_SHADER_CAP_MAX_CONSTS:
386 return 256; //max native parameters
387 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
388 return 1;
389 case PIPE_SHADER_CAP_MAX_PREDS:
390 return 0; /* FIXME */
391 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
392 return 1;
393 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
394 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
395 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
396 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
397 return 1;
398 case PIPE_SHADER_CAP_SUBROUTINES:
399 return 0;
400 default:
401 return 0;
402 }
403 }
404
405 static boolean r600_is_format_supported(struct pipe_screen* screen,
406 enum pipe_format format,
407 enum pipe_texture_target target,
408 unsigned sample_count,
409 unsigned usage,
410 unsigned geom_flags)
411 {
412 unsigned retval = 0;
413 if (target >= PIPE_MAX_TEXTURE_TYPES) {
414 R600_ERR("r600: unsupported texture type %d\n", target);
415 return FALSE;
416 }
417
418 /* Multisample */
419 if (sample_count > 1)
420 return FALSE;
421
422 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
423 r600_is_sampler_format_supported(format)) {
424 retval |= PIPE_BIND_SAMPLER_VIEW;
425 }
426
427 if ((usage & (PIPE_BIND_RENDER_TARGET |
428 PIPE_BIND_DISPLAY_TARGET |
429 PIPE_BIND_SCANOUT |
430 PIPE_BIND_SHARED)) &&
431 r600_is_colorbuffer_format_supported(format)) {
432 retval |= usage &
433 (PIPE_BIND_RENDER_TARGET |
434 PIPE_BIND_DISPLAY_TARGET |
435 PIPE_BIND_SCANOUT |
436 PIPE_BIND_SHARED);
437 }
438
439 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
440 r600_is_zs_format_supported(format)) {
441 retval |= PIPE_BIND_DEPTH_STENCIL;
442 }
443
444 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
445 r600_is_vertex_format_supported(format))
446 retval |= PIPE_BIND_VERTEX_BUFFER;
447
448 if (usage & PIPE_BIND_TRANSFER_READ)
449 retval |= PIPE_BIND_TRANSFER_READ;
450 if (usage & PIPE_BIND_TRANSFER_WRITE)
451 retval |= PIPE_BIND_TRANSFER_WRITE;
452
453 return retval == usage;
454 }
455
456 static void r600_destroy_screen(struct pipe_screen* pscreen)
457 {
458 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
459
460 if (rscreen == NULL)
461 return;
462
463 radeon_decref(rscreen->radeon);
464
465 FREE(rscreen);
466 }
467
468
469 struct pipe_screen *r600_screen_create(struct radeon *radeon)
470 {
471 struct r600_screen *rscreen;
472
473 rscreen = CALLOC_STRUCT(r600_screen);
474 if (rscreen == NULL) {
475 return NULL;
476 }
477
478 rscreen->radeon = radeon;
479 rscreen->screen.winsys = (struct pipe_winsys*)radeon;
480 rscreen->screen.destroy = r600_destroy_screen;
481 rscreen->screen.get_name = r600_get_name;
482 rscreen->screen.get_vendor = r600_get_vendor;
483 rscreen->screen.get_param = r600_get_param;
484 rscreen->screen.get_shader_param = r600_get_shader_param;
485 rscreen->screen.get_paramf = r600_get_paramf;
486 rscreen->screen.is_format_supported = r600_is_format_supported;
487 rscreen->screen.context_create = r600_create_context;
488 rscreen->screen.video_context_create = r600_video_create;
489 r600_init_screen_resource_functions(&rscreen->screen);
490
491 rscreen->tiling_info = r600_get_tiling_info(radeon);
492
493 return &rscreen->screen;
494 }