src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_blitter.h"
  34 #include "util/u_debug.h"
  35 #include "util/u_memory.h"
  36 #include "util/u_simple_shaders.h"
  37 #include "util/u_upload_mgr.h"
  38 #include "util/u_math.h"
  39 #include "vl/vl_decoder.h"
  40 #include "vl/vl_video_buffer.h"
  41 #include "radeon/radeon_video.h"
  42 #include "radeon/radeon_uvd.h"
  43 #include "os/os_time.h"
  44
  45 static const struct debug_named_value r600_debug_options[] = {
  46         /* features */
  47 #if defined(R600_USE_LLVM)
  48         { "nollvm", DBG_NO_LLVM, "Disable the LLVM shader compiler" },
  49 #endif
  50         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  51
  52         /* shader backend */
  53         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  54         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  55         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  56         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  57         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  58         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  59         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  60         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  61
  62         DEBUG_NAMED_VALUE_END /* must be last */
  63 };
  64
  65 /*
  66  * pipe_context
  67  */
  68
  69 static void r600_flush(struct pipe_context *ctx, unsigned flags)
  70 {
  71         struct r600_context *rctx = (struct r600_context *)ctx;
  72         struct pipe_query *render_cond = NULL;
  73         unsigned render_cond_mode = 0;
  74         boolean render_cond_cond = FALSE;
  75
  76         if (rctx->b.rings.gfx.cs->cdw == rctx->b.initial_gfx_cs_size)
  77                 return;
  78
  79         rctx->b.rings.gfx.flushing = true;
  80         /* Disable render condition. */
  81         if (rctx->b.current_render_cond) {
  82                 render_cond = rctx->b.current_render_cond;
  83                 render_cond_cond = rctx->b.current_render_cond_cond;
  84                 render_cond_mode = rctx->b.current_render_cond_mode;
  85                 ctx->render_condition(ctx, NULL, FALSE, 0);
  86         }
  87
  88         r600_context_flush(rctx, flags);
  89         rctx->b.rings.gfx.flushing = false;
  90         r600_begin_new_cs(rctx);
  91
  92         /* Re-enable render condition. */
  93         if (render_cond) {
  94                 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
  95         }
  96
  97         rctx->b.initial_gfx_cs_size = rctx->b.rings.gfx.cs->cdw;
  98 }
  99
 100 static void r600_flush_from_st(struct pipe_context *ctx,
 101                                struct pipe_fence_handle **fence,
 102                                unsigned flags)
 103 {
 104         struct r600_context *rctx = (struct r600_context *)ctx;
 105         unsigned fflags;
 106
 107         fflags = flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0;
 108         if (fence) {
 109                 *fence = rctx->b.ws->cs_create_fence(rctx->b.rings.gfx.cs);
 110         }
 111         /* flush gfx & dma ring, order does not matter as only one can be live */
 112         if (rctx->b.rings.dma.cs) {
 113                 rctx->b.rings.dma.flush(rctx, fflags);
 114         }
 115         rctx->b.rings.gfx.flush(rctx, fflags);
 116 }
 117
 118 static void r600_flush_gfx_ring(void *ctx, unsigned flags)
 119 {
 120         r600_flush((struct pipe_context*)ctx, flags);
 121 }
 122
 123 static void r600_destroy_context(struct pipe_context *context)
 124 {
 125         struct r600_context *rctx = (struct r600_context *)context;
 126
 127         r600_isa_destroy(rctx->isa);
 128
 129         r600_sb_context_destroy(rctx->sb_context);
 130
 131         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
 132         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
 133
 134         if (rctx->dummy_pixel_shader) {
 135                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 136         }
 137         if (rctx->custom_dsa_flush) {
 138                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
 139         }
 140         if (rctx->custom_blend_resolve) {
 141                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
 142         }
 143         if (rctx->custom_blend_decompress) {
 144                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
 145         }
 146         if (rctx->custom_blend_fastclear) {
 147                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
 148         }
 149         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 150
 151         if (rctx->blitter) {
 152                 util_blitter_destroy(rctx->blitter);
 153         }
 154         if (rctx->allocator_fetch_shader) {
 155                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 156         }
 157
 158         r600_release_command_buffer(&rctx->start_cs_cmd);
 159
 160         FREE(rctx->start_compute_cs_cmd.buf);
 161
 162         r600_common_context_cleanup(&rctx->b);
 163         FREE(rctx);
 164 }
 165
 166 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 167 {
 168         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 169         struct r600_screen* rscreen = (struct r600_screen *)screen;
 170
 171         if (rctx == NULL)
 172                 return NULL;
 173
 174         rctx->b.b.screen = screen;
 175         rctx->b.b.priv = priv;
 176         rctx->b.b.destroy = r600_destroy_context;
 177         rctx->b.b.flush = r600_flush_from_st;
 178
 179         if (!r600_common_context_init(&rctx->b, &rscreen->b))
 180                 goto fail;
 181
 182         rctx->screen = rscreen;
 183         rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
 184
 185         r600_init_blit_functions(rctx);
 186
 187         if (rscreen->b.info.has_uvd) {
 188                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 189                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 190         } else {
 191                 rctx->b.b.create_video_codec = vl_create_decoder;
 192                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 193         }
 194
 195         r600_init_common_state_functions(rctx);
 196
 197         switch (rctx->b.chip_class) {
 198         case R600:
 199         case R700:
 200                 r600_init_state_functions(rctx);
 201                 r600_init_atom_start_cs(rctx);
 202                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 203                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 204                                                                       : r600_create_resolve_blend(rctx);
 205                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 206                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 207                                            rctx->b.family == CHIP_RV620 ||
 208                                            rctx->b.family == CHIP_RS780 ||
 209                                            rctx->b.family == CHIP_RS880 ||
 210                                            rctx->b.family == CHIP_RV710);
 211                 break;
 212         case EVERGREEN:
 213         case CAYMAN:
 214                 evergreen_init_state_functions(rctx);
 215                 evergreen_init_atom_start_cs(rctx);
 216                 evergreen_init_atom_start_compute_cs(rctx);
 217                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 218                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 219                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 220                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 221                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 222                                            rctx->b.family == CHIP_PALM ||
 223                                            rctx->b.family == CHIP_SUMO ||
 224                                            rctx->b.family == CHIP_SUMO2 ||
 225                                            rctx->b.family == CHIP_CAICOS ||
 226                                            rctx->b.family == CHIP_CAYMAN ||
 227                                            rctx->b.family == CHIP_ARUBA);
 228                 break;
 229         default:
 230                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 231                 goto fail;
 232         }
 233
 234         if (rscreen->b.trace_bo) {
 235                 rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, rscreen->b.trace_bo->cs_buf);
 236         } else {
 237                 rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, NULL);
 238         }
 239         rctx->b.rings.gfx.flush = r600_flush_gfx_ring;
 240         rctx->b.ws->cs_set_flush_callback(rctx->b.rings.gfx.cs, r600_flush_gfx_ring, rctx);
 241         rctx->b.rings.gfx.flushing = false;
 242
 243         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
 244                                                              0, PIPE_USAGE_DEFAULT, FALSE);
 245         if (!rctx->allocator_fetch_shader)
 246                 goto fail;
 247
 248         rctx->isa = calloc(1, sizeof(struct r600_isa));
 249         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 250                 goto fail;
 251
 252         rctx->blitter = util_blitter_create(&rctx->b.b);
 253         if (rctx->blitter == NULL)
 254                 goto fail;
 255         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 256         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 257
 258         r600_begin_new_cs(rctx);
 259         r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
 260
 261         rctx->dummy_pixel_shader =
 262                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 263                                                      TGSI_SEMANTIC_GENERIC,
 264                                                      TGSI_INTERPOLATE_CONSTANT);
 265         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 266
 267         return &rctx->b.b;
 268
 269 fail:
 270         r600_destroy_context(&rctx->b.b);
 271         return NULL;
 272 }
 273
 274 /*
 275  * pipe_screen
 276  */
 277
 278 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 279 {
 280         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 281         enum radeon_family family = rscreen->b.family;
 282
 283         switch (param) {
 284         /* Supported features (boolean caps). */
 285         case PIPE_CAP_NPOT_TEXTURES:
 286         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 287         case PIPE_CAP_TWO_SIDED_STENCIL:
 288         case PIPE_CAP_ANISOTROPIC_FILTER:
 289         case PIPE_CAP_POINT_SPRITE:
 290         case PIPE_CAP_OCCLUSION_QUERY:
 291         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 292         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 293         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 294         case PIPE_CAP_TEXTURE_SWIZZLE:
 295         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 296         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 297         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 298         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 299         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 300         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 301         case PIPE_CAP_SM3:
 302         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 303         case PIPE_CAP_PRIMITIVE_RESTART:
 304         case PIPE_CAP_CONDITIONAL_RENDER:
 305         case PIPE_CAP_TEXTURE_BARRIER:
 306         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 307         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 308         case PIPE_CAP_TGSI_INSTANCEID:
 309         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 310         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 311         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 312         case PIPE_CAP_USER_INDEX_BUFFERS:
 313         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 314         case PIPE_CAP_START_INSTANCE:
 315         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 316         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 317         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 318         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 319         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 320         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 321                 return 1;
 322
 323         case PIPE_CAP_COMPUTE:
 324                 return rscreen->b.chip_class > R700;
 325
 326         case PIPE_CAP_TGSI_TEXCOORD:
 327                 return 0;
 328
 329         case PIPE_CAP_FAKE_SW_MSAA:
 330                 return 0;
 331
 332         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 333                 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
 334
 335         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 336                 return R600_MAP_BUFFER_ALIGNMENT;
 337
 338         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 339                 return 256;
 340
 341         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 342                 return 1;
 343
 344         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 345                 if (family >= CHIP_CEDAR)
 346                    return 330;
 347                 /* pre-evergreen geom shaders need newer kernel */
 348                 if (rscreen->b.info.drm_minor >= 37)
 349                    return 330;
 350                 return 140;
 351
 352         /* Supported except the original R600. */
 353         case PIPE_CAP_INDEP_BLEND_ENABLE:
 354         case PIPE_CAP_INDEP_BLEND_FUNC:
 355                 /* R600 doesn't support per-MRT blends */
 356                 return family == CHIP_R600 ? 0 : 1;
 357
 358         /* Supported on Evergreen. */
 359         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 360         case PIPE_CAP_CUBE_MAP_ARRAY:
 361         case PIPE_CAP_TGSI_VS_LAYER:
 362                 return family >= CHIP_CEDAR ? 1 : 0;
 363
 364         /* Unsupported features. */
 365         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 366         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 367         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 368         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 369         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 370         case PIPE_CAP_USER_VERTEX_BUFFERS:
 371         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 372         case PIPE_CAP_TEXTURE_GATHER_SM5:
 373         case PIPE_CAP_TEXTURE_QUERY_LOD:
 374                 return 0;
 375
 376         /* Stream output. */
 377         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 378                 return rscreen->b.has_streamout ? 4 : 0;
 379         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 380                 return rscreen->b.has_streamout ? 1 : 0;
 381         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 382         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 383                 return 32*4;
 384
 385         /* Geometry shader output. */
 386         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 387                 return 1024;
 388         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 389                 return 16384;
 390
 391         /* Texturing. */
 392         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 393         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 394                 if (family >= CHIP_CEDAR)
 395                         return 15;
 396                 else
 397                         return 14;
 398         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 399                 /* textures support 8192, but layered rendering supports 2048 */
 400                 return 12;
 401         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 402                 /* textures support 8192, but layered rendering supports 2048 */
 403                 return rscreen->b.info.drm_minor >= 9 ? 2048 : 0;
 404
 405         /* Render targets. */
 406         case PIPE_CAP_MAX_RENDER_TARGETS:
 407                 /* XXX some r6xx are buggy and can only do 4 */
 408                 return 8;
 409
 410         case PIPE_CAP_MAX_VIEWPORTS:
 411                 return 16;
 412
 413         /* Timer queries, present when the clock frequency is non zero. */
 414         case PIPE_CAP_QUERY_TIME_ELAPSED:
 415                 return rscreen->b.info.r600_clock_crystal_freq != 0;
 416         case PIPE_CAP_QUERY_TIMESTAMP:
 417                 return rscreen->b.info.drm_minor >= 20 &&
 418                        rscreen->b.info.r600_clock_crystal_freq != 0;
 419
 420         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 421         case PIPE_CAP_MIN_TEXEL_OFFSET:
 422                 return -8;
 423
 424         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 425         case PIPE_CAP_MAX_TEXEL_OFFSET:
 426                 return 7;
 427
 428         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 429                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 430         case PIPE_CAP_ENDIANNESS:
 431                 return PIPE_ENDIAN_LITTLE;
 432         }
 433         return 0;
 434 }
 435
 436 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 437 {
 438         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 439
 440         switch(shader)
 441         {
 442         case PIPE_SHADER_FRAGMENT:
 443         case PIPE_SHADER_VERTEX:
 444         case PIPE_SHADER_COMPUTE:
 445                 break;
 446         case PIPE_SHADER_GEOMETRY:
 447                 if (rscreen->b.family >= CHIP_CEDAR)
 448                         break;
 449                 /* pre-evergreen geom shaders need newer kernel */
 450                 if (rscreen->b.info.drm_minor >= 37)
 451                         break;
 452                 return 0;
 453         default:
 454                 /* XXX: support tessellation on Evergreen */
 455                 return 0;
 456         }
 457
 458         switch (param) {
 459         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 460         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 461         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 462         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 463                 return 16384;
 464         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 465                 return 32;
 466         case PIPE_SHADER_CAP_MAX_INPUTS:
 467                 return 32;
 468         case PIPE_SHADER_CAP_MAX_TEMPS:
 469                 return 256; /* Max native temporaries. */
 470         case PIPE_SHADER_CAP_MAX_ADDRS:
 471                 /* XXX Isn't this equal to TEMPS? */
 472                 return 1; /* Max native address registers */
 473         case PIPE_SHADER_CAP_MAX_CONSTS:
 474                 return R600_MAX_CONST_BUFFER_SIZE;
 475         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 476                 return R600_MAX_USER_CONST_BUFFERS;
 477         case PIPE_SHADER_CAP_MAX_PREDS:
 478                 return 0; /* nothing uses this */
 479         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 480                 return 1;
 481         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 482                 return 0;
 483         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 484         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 485         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 486         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 487                 return 1;
 488         case PIPE_SHADER_CAP_SUBROUTINES:
 489                 return 0;
 490         case PIPE_SHADER_CAP_INTEGERS:
 491                 return 1;
 492         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 493         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 494                 return 16;
 495         case PIPE_SHADER_CAP_PREFERRED_IR:
 496                 if (shader == PIPE_SHADER_COMPUTE) {
 497                         return PIPE_SHADER_IR_LLVM;
 498                 } else {
 499                         return PIPE_SHADER_IR_TGSI;
 500                 }
 501         }
 502         return 0;
 503 }
 504
 505 static void r600_destroy_screen(struct pipe_screen* pscreen)
 506 {
 507         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 508
 509         if (rscreen == NULL)
 510                 return;
 511
 512         if (!rscreen->b.ws->unref(rscreen->b.ws))
 513                 return;
 514
 515         if (rscreen->global_pool) {
 516                 compute_memory_pool_delete(rscreen->global_pool);
 517         }
 518
 519         r600_destroy_common_screen(&rscreen->b);
 520 }
 521
 522 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 523                                                   const struct pipe_resource *templ)
 524 {
 525         if (templ->target == PIPE_BUFFER &&
 526             (templ->bind & PIPE_BIND_GLOBAL))
 527                 return r600_compute_global_buffer_create(screen, templ);
 528
 529         return r600_resource_create_common(screen, templ);
 530 }
 531
 532 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 533 {
 534         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 535
 536         if (rscreen == NULL) {
 537                 return NULL;
 538         }
 539
 540         /* Set functions first. */
 541         rscreen->b.b.context_create = r600_create_context;
 542         rscreen->b.b.destroy = r600_destroy_screen;
 543         rscreen->b.b.get_param = r600_get_param;
 544         rscreen->b.b.get_shader_param = r600_get_shader_param;
 545         rscreen->b.b.resource_create = r600_resource_create;
 546
 547         if (!r600_common_screen_init(&rscreen->b, ws)) {
 548                 FREE(rscreen);
 549                 return NULL;
 550         }
 551
 552         if (rscreen->b.info.chip_class >= EVERGREEN) {
 553                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 554         } else {
 555                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 556         }
 557
 558         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 559         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 560                 rscreen->b.debug_flags |= DBG_COMPUTE;
 561         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 562                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 563         if (debug_get_bool_option("R600_HYPERZ", FALSE))
 564                 rscreen->b.debug_flags |= DBG_HYPERZ;
 565         if (!debug_get_bool_option("R600_LLVM", TRUE))
 566                 rscreen->b.debug_flags |= DBG_NO_LLVM;
 567
 568         if (rscreen->b.family == CHIP_UNKNOWN) {
 569                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 570                 FREE(rscreen);
 571                 return NULL;
 572         }
 573
 574         /* Figure out streamout kernel support. */
 575         switch (rscreen->b.chip_class) {
 576         case R600:
 577                 if (rscreen->b.family < CHIP_RS780) {
 578                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 579                 } else {
 580                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 581                 }
 582                 break;
 583         case R700:
 584                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 585                 break;
 586         case EVERGREEN:
 587         case CAYMAN:
 588                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 589                 break;
 590         default:
 591                 rscreen->b.has_streamout = FALSE;
 592                 break;
 593         }
 594
 595         /* MSAA support. */
 596         switch (rscreen->b.chip_class) {
 597         case R600:
 598         case R700:
 599                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 600                 rscreen->has_compressed_msaa_texturing = false;
 601                 break;
 602         case EVERGREEN:
 603                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 604                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 605                 break;
 606         case CAYMAN:
 607                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 608                 rscreen->has_compressed_msaa_texturing = true;
 609                 break;
 610         default:
 611                 rscreen->has_msaa = FALSE;
 612                 rscreen->has_compressed_msaa_texturing = false;
 613         }
 614
 615         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 616                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 617
 618         rscreen->global_pool = compute_memory_pool_new(rscreen);
 619
 620         /* Create the auxiliary context. This must be done last. */
 621         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
 622
 623 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 624         struct pipe_resource templ = {};
 625
 626         templ.width0 = 4;
 627         templ.height0 = 2048;
 628         templ.depth0 = 1;
 629         templ.array_size = 1;
 630         templ.target = PIPE_TEXTURE_2D;
 631         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 632         templ.usage = PIPE_USAGE_DEFAULT;
 633
 634         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 635         unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
 636
 637         memset(map, 0, 256);
 638
 639         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 640         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 641         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 642         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 643         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 644
 645         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 646
 647         int i;
 648         for (i = 0; i < 256; i++) {
 649                 printf("%02X", map[i]);
 650                 if (i % 16 == 15)
 651                         printf("\n");
 652         }
 653 #endif
 654
 655         return &rscreen->b.b;
 656 }