src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_debug.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_simple_shaders.h"
  36 #include "util/u_upload_mgr.h"
  37 #include "util/u_math.h"
  38 #include "vl/vl_decoder.h"
  39 #include "vl/vl_video_buffer.h"
  40 #include "radeon_video.h"
  41 #include "radeon_uvd.h"
  42 #include "util/os_time.h"
  43
  44 static const struct debug_named_value r600_debug_options[] = {
  45         /* features */
  46         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  47
  48         /* shader backend */
  49         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  50         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  51         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  52         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  53         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  54         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  55         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  56         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  57
  58         DEBUG_NAMED_VALUE_END /* must be last */
  59 };
  60
  61 /*
  62  * pipe_context
  63  */
  64
  65 static void r600_destroy_context(struct pipe_context *context)
  66 {
  67         struct r600_context *rctx = (struct r600_context *)context;
  68         unsigned sh;
  69
  70         r600_isa_destroy(rctx->isa);
  71
  72         r600_sb_context_destroy(rctx->sb_context);
  73
  74         r600_resource_reference(&rctx->dummy_cmask, NULL);
  75         r600_resource_reference(&rctx->dummy_fmask, NULL);
  76
  77         if (rctx->append_fence)
  78                 pipe_resource_reference((struct pipe_resource**)&rctx->append_fence, NULL);
  79         for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
  80                 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, NULL);
  81                 free(rctx->driver_consts[sh].constants);
  82         }
  83
  84         if (rctx->fixed_func_tcs_shader)
  85                 rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
  86
  87         if (rctx->dummy_pixel_shader) {
  88                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
  89         }
  90         if (rctx->custom_dsa_flush) {
  91                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
  92         }
  93         if (rctx->custom_blend_resolve) {
  94                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
  95         }
  96         if (rctx->custom_blend_decompress) {
  97                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
  98         }
  99         if (rctx->custom_blend_fastclear) {
 100                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
 101         }
 102         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 103
 104         if (rctx->blitter) {
 105                 util_blitter_destroy(rctx->blitter);
 106         }
 107         if (rctx->allocator_fetch_shader) {
 108                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 109         }
 110
 111         r600_release_command_buffer(&rctx->start_cs_cmd);
 112
 113         FREE(rctx->start_compute_cs_cmd.buf);
 114
 115         r600_common_context_cleanup(&rctx->b);
 116
 117         r600_resource_reference(&rctx->trace_buf, NULL);
 118         r600_resource_reference(&rctx->last_trace_buf, NULL);
 119         radeon_clear_saved_cs(&rctx->last_gfx);
 120
 121         FREE(rctx);
 122 }
 123
 124 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
 125                                                 void *priv, unsigned flags)
 126 {
 127         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 128         struct r600_screen* rscreen = (struct r600_screen *)screen;
 129         struct radeon_winsys *ws = rscreen->b.ws;
 130
 131         if (!rctx)
 132                 return NULL;
 133
 134         rctx->b.b.screen = screen;
 135         assert(!priv);
 136         rctx->b.b.priv = NULL; /* for threaded_context_unwrap_sync */
 137         rctx->b.b.destroy = r600_destroy_context;
 138         rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
 139
 140         if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
 141                 goto fail;
 142
 143         rctx->screen = rscreen;
 144         LIST_INITHEAD(&rctx->texture_buffers);
 145
 146         r600_init_blit_functions(rctx);
 147
 148         if (rscreen->b.info.has_hw_decode) {
 149                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 150                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 151         } else {
 152                 rctx->b.b.create_video_codec = vl_create_decoder;
 153                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 154         }
 155
 156         if (getenv("R600_TRACE"))
 157                 rctx->is_debug = true;
 158         r600_init_common_state_functions(rctx);
 159
 160         switch (rctx->b.chip_class) {
 161         case R600:
 162         case R700:
 163                 r600_init_state_functions(rctx);
 164                 r600_init_atom_start_cs(rctx);
 165                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 166                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 167                                                                       : r600_create_resolve_blend(rctx);
 168                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 169                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 170                                            rctx->b.family == CHIP_RV620 ||
 171                                            rctx->b.family == CHIP_RS780 ||
 172                                            rctx->b.family == CHIP_RS880 ||
 173                                            rctx->b.family == CHIP_RV710);
 174                 break;
 175         case EVERGREEN:
 176         case CAYMAN:
 177                 evergreen_init_state_functions(rctx);
 178                 evergreen_init_atom_start_cs(rctx);
 179                 evergreen_init_atom_start_compute_cs(rctx);
 180                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 181                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 182                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 183                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 184                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 185                                            rctx->b.family == CHIP_PALM ||
 186                                            rctx->b.family == CHIP_SUMO ||
 187                                            rctx->b.family == CHIP_SUMO2 ||
 188                                            rctx->b.family == CHIP_CAICOS ||
 189                                            rctx->b.family == CHIP_CAYMAN ||
 190                                            rctx->b.family == CHIP_ARUBA);
 191
 192                 rctx->append_fence = pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
 193                                                          PIPE_USAGE_DEFAULT, 32);
 194                 break;
 195         default:
 196                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 197                 goto fail;
 198         }
 199
 200         rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
 201                                        r600_context_gfx_flush, rctx);
 202         rctx->b.gfx.flush = r600_context_gfx_flush;
 203
 204         rctx->allocator_fetch_shader =
 205                 u_suballocator_create(&rctx->b.b, 64 * 1024,
 206                                       0, PIPE_USAGE_DEFAULT, 0, FALSE);
 207         if (!rctx->allocator_fetch_shader)
 208                 goto fail;
 209
 210         rctx->isa = calloc(1, sizeof(struct r600_isa));
 211         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 212                 goto fail;
 213
 214         if (rscreen->b.debug_flags & DBG_FORCE_DMA)
 215                 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
 216
 217         rctx->blitter = util_blitter_create(&rctx->b.b);
 218         if (rctx->blitter == NULL)
 219                 goto fail;
 220         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 221         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 222
 223         r600_begin_new_cs(rctx);
 224
 225         rctx->dummy_pixel_shader =
 226                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 227                                                      TGSI_SEMANTIC_GENERIC,
 228                                                      TGSI_INTERPOLATE_CONSTANT);
 229         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 230
 231         return &rctx->b.b;
 232
 233 fail:
 234         r600_destroy_context(&rctx->b.b);
 235         return NULL;
 236 }
 237
 238 /*
 239  * pipe_screen
 240  */
 241
 242 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 243 {
 244         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 245         enum radeon_family family = rscreen->b.family;
 246
 247         switch (param) {
 248         /* Supported features (boolean caps). */
 249         case PIPE_CAP_NPOT_TEXTURES:
 250         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 251         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 252         case PIPE_CAP_ANISOTROPIC_FILTER:
 253         case PIPE_CAP_POINT_SPRITE:
 254         case PIPE_CAP_OCCLUSION_QUERY:
 255         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 256         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 257         case PIPE_CAP_TEXTURE_SWIZZLE:
 258         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 259         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 260         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 261         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 262         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 263         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 264         case PIPE_CAP_SM3:
 265         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 266         case PIPE_CAP_PRIMITIVE_RESTART:
 267         case PIPE_CAP_CONDITIONAL_RENDER:
 268         case PIPE_CAP_TEXTURE_BARRIER:
 269         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 270         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 271         case PIPE_CAP_TGSI_INSTANCEID:
 272         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 273         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 274         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 275         case PIPE_CAP_START_INSTANCE:
 276         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 277         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 278         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 279         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 280         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 281         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 282         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 283         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 284         case PIPE_CAP_SAMPLE_SHADING:
 285         case PIPE_CAP_CLIP_HALFZ:
 286         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 287         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 288         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 289         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 290         case PIPE_CAP_TGSI_TXQS:
 291         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 292         case PIPE_CAP_INVALIDATE_BUFFER:
 293         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 294         case PIPE_CAP_QUERY_MEMORY_INFO:
 295         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 296         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 297         case PIPE_CAP_CLEAR_TEXTURE:
 298         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 299         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 300         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 301         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 302                 return 1;
 303
 304         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 305                 return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
 306
 307         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 308                 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
 309
 310         case PIPE_CAP_COMPUTE:
 311                 return rscreen->b.chip_class > R700;
 312
 313         case PIPE_CAP_TGSI_TEXCOORD:
 314                 return 0;
 315
 316         case PIPE_CAP_FAKE_SW_MSAA:
 317                 return 0;
 318
 319         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 320                 return MIN2(rscreen->b.info.max_alloc_size, INT_MAX);
 321
 322         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 323                 return R600_MAP_BUFFER_ALIGNMENT;
 324
 325         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 326                 return 256;
 327
 328         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 329                 return 1;
 330
 331         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 332                 if (family >= CHIP_CEDAR)
 333                    return 430;
 334                 /* pre-evergreen geom shaders need newer kernel */
 335                 if (rscreen->b.info.drm_minor >= 37)
 336                    return 330;
 337                 return 140;
 338
 339         /* Supported except the original R600. */
 340         case PIPE_CAP_INDEP_BLEND_ENABLE:
 341         case PIPE_CAP_INDEP_BLEND_FUNC:
 342                 /* R600 doesn't support per-MRT blends */
 343                 return family == CHIP_R600 ? 0 : 1;
 344
 345         /* Supported on Evergreen. */
 346         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 347         case PIPE_CAP_CUBE_MAP_ARRAY:
 348         case PIPE_CAP_TEXTURE_GATHER_SM5:
 349         case PIPE_CAP_TEXTURE_QUERY_LOD:
 350         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 351         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 352         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 353         case PIPE_CAP_TGSI_CLOCK:
 354         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 355         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 356                 return family >= CHIP_CEDAR ? 1 : 0;
 357         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 358                 return family >= CHIP_CEDAR ? 4 : 0;
 359         case PIPE_CAP_DRAW_INDIRECT:
 360                 /* kernel command checker support is also required */
 361                 return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
 362
 363         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 364                 return family >= CHIP_CEDAR ? 0 : 1;
 365
 366         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 367                 return 8;
 368
 369         /* Unsupported features. */
 370         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 371         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 372         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 373         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 374         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 375         case PIPE_CAP_USER_VERTEX_BUFFERS:
 376         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 377         case PIPE_CAP_VERTEXID_NOBASE:
 378         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 379         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 380         case PIPE_CAP_SHAREABLE_SHADERS:
 381         case PIPE_CAP_DRAW_PARAMETERS:
 382         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 383         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 384         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 385         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 386         case PIPE_CAP_GENERATE_MIPMAP:
 387         case PIPE_CAP_STRING_MARKER:
 388         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 389         case PIPE_CAP_TGSI_VOTE:
 390         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 391         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 392         case PIPE_CAP_NATIVE_FENCE_FD:
 393         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 394         case PIPE_CAP_TGSI_FS_FBFETCH:
 395         case PIPE_CAP_INT64:
 396         case PIPE_CAP_INT64_DIVMOD:
 397         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 398         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 399         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 400         case PIPE_CAP_TGSI_BALLOT:
 401         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 402         case PIPE_CAP_POST_DEPTH_COVERAGE:
 403         case PIPE_CAP_BINDLESS_TEXTURE:
 404         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 405         case PIPE_CAP_QUERY_SO_OVERFLOW:
 406         case PIPE_CAP_MEMOBJ:
 407         case PIPE_CAP_LOAD_CONSTBUF:
 408         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 409         case PIPE_CAP_TILE_RASTER_ORDER:
 410         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 411         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 412         case PIPE_CAP_FENCE_SIGNAL:
 413                 return 0;
 414
 415         case PIPE_CAP_DOUBLES:
 416                 if (rscreen->b.family == CHIP_ARUBA ||
 417                     rscreen->b.family == CHIP_CAYMAN ||
 418                     rscreen->b.family == CHIP_CYPRESS ||
 419                     rscreen->b.family == CHIP_HEMLOCK)
 420                         return 1;
 421                 return 0;
 422         case PIPE_CAP_CULL_DISTANCE:
 423                 return 1;
 424
 425         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 426                 if (family >= CHIP_CEDAR)
 427                         return 256;
 428                 return 0;
 429
 430         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 431                 if (family >= CHIP_CEDAR)
 432                         return 30;
 433                 else
 434                         return 0;
 435         /* Stream output. */
 436         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 437                 return rscreen->b.has_streamout ? 4 : 0;
 438         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 439         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 440                 return rscreen->b.has_streamout ? 1 : 0;
 441         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 442         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 443                 return 32*4;
 444
 445         /* Geometry shader output. */
 446         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 447                 return 1024;
 448         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 449                 return 16384;
 450         case PIPE_CAP_MAX_VERTEX_STREAMS:
 451                 return family >= CHIP_CEDAR ? 4 : 1;
 452
 453         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 454                 return 2047;
 455
 456         /* Texturing. */
 457         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 458         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 459                 if (family >= CHIP_CEDAR)
 460                         return 15;
 461                 else
 462                         return 14;
 463         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 464                 /* textures support 8192, but layered rendering supports 2048 */
 465                 return 12;
 466         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 467                 /* textures support 8192, but layered rendering supports 2048 */
 468                 return 2048;
 469
 470         /* Render targets. */
 471         case PIPE_CAP_MAX_RENDER_TARGETS:
 472                 /* XXX some r6xx are buggy and can only do 4 */
 473                 return 8;
 474
 475         case PIPE_CAP_MAX_VIEWPORTS:
 476                 return R600_MAX_VIEWPORTS;
 477         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 478                 return 8;
 479
 480         /* Timer queries, present when the clock frequency is non zero. */
 481         case PIPE_CAP_QUERY_TIME_ELAPSED:
 482                 return rscreen->b.info.clock_crystal_freq != 0;
 483         case PIPE_CAP_QUERY_TIMESTAMP:
 484                 return rscreen->b.info.drm_minor >= 20 &&
 485                        rscreen->b.info.clock_crystal_freq != 0;
 486
 487         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 488         case PIPE_CAP_MIN_TEXEL_OFFSET:
 489                 return -8;
 490
 491         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 492         case PIPE_CAP_MAX_TEXEL_OFFSET:
 493                 return 7;
 494
 495         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 496                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 497         case PIPE_CAP_ENDIANNESS:
 498                 return PIPE_ENDIAN_LITTLE;
 499
 500         case PIPE_CAP_VENDOR_ID:
 501                 return ATI_VENDOR_ID;
 502         case PIPE_CAP_DEVICE_ID:
 503                 return rscreen->b.info.pci_id;
 504         case PIPE_CAP_ACCELERATED:
 505                 return 1;
 506         case PIPE_CAP_VIDEO_MEMORY:
 507                 return rscreen->b.info.vram_size >> 20;
 508         case PIPE_CAP_UMA:
 509                 return 0;
 510         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 511                 return rscreen->b.chip_class >= R700;
 512         case PIPE_CAP_PCI_GROUP:
 513                 return rscreen->b.info.pci_domain;
 514         case PIPE_CAP_PCI_BUS:
 515                 return rscreen->b.info.pci_bus;
 516         case PIPE_CAP_PCI_DEVICE:
 517                 return rscreen->b.info.pci_dev;
 518         case PIPE_CAP_PCI_FUNCTION:
 519                 return rscreen->b.info.pci_func;
 520         }
 521         return 0;
 522 }
 523
 524 static int r600_get_shader_param(struct pipe_screen* pscreen,
 525                                  enum pipe_shader_type shader,
 526                                  enum pipe_shader_cap param)
 527 {
 528         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 529
 530         switch(shader)
 531         {
 532         case PIPE_SHADER_FRAGMENT:
 533         case PIPE_SHADER_VERTEX:
 534         case PIPE_SHADER_COMPUTE:
 535                 break;
 536         case PIPE_SHADER_GEOMETRY:
 537                 if (rscreen->b.family >= CHIP_CEDAR)
 538                         break;
 539                 /* pre-evergreen geom shaders need newer kernel */
 540                 if (rscreen->b.info.drm_minor >= 37)
 541                         break;
 542                 return 0;
 543         case PIPE_SHADER_TESS_CTRL:
 544         case PIPE_SHADER_TESS_EVAL:
 545                 if (rscreen->b.family >= CHIP_CEDAR)
 546                         break;
 547         default:
 548                 return 0;
 549         }
 550
 551         switch (param) {
 552         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 553         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 554         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 555         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 556                 return 16384;
 557         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 558                 return 32;
 559         case PIPE_SHADER_CAP_MAX_INPUTS:
 560                 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
 561         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 562                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 563         case PIPE_SHADER_CAP_MAX_TEMPS:
 564                 return 256; /* Max native temporaries. */
 565         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 566                 if (shader == PIPE_SHADER_COMPUTE) {
 567                         uint64_t max_const_buffer_size;
 568                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 569                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 570                                 &max_const_buffer_size);
 571                         return MIN2(max_const_buffer_size, INT_MAX);
 572
 573                 } else {
 574                         return R600_MAX_CONST_BUFFER_SIZE;
 575                 }
 576         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 577                 return R600_MAX_USER_CONST_BUFFERS;
 578         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 579                 return 1;
 580         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 581                 return 1;
 582         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 583         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 584         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 585         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 586                 return 1;
 587         case PIPE_SHADER_CAP_SUBROUTINES:
 588         case PIPE_SHADER_CAP_INT64_ATOMICS:
 589         case PIPE_SHADER_CAP_FP16:
 590                 return 0;
 591         case PIPE_SHADER_CAP_INTEGERS:
 592         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 593                 return 1;
 594         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 595         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 596                 return 16;
 597         case PIPE_SHADER_CAP_PREFERRED_IR:
 598                 if (shader == PIPE_SHADER_COMPUTE) {
 599                         return PIPE_SHADER_IR_NATIVE;
 600                 } else {
 601                         return PIPE_SHADER_IR_TGSI;
 602                 }
 603         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 604                 if (rscreen->b.family >= CHIP_CEDAR)
 605                         return (1 << PIPE_SHADER_IR_TGSI);
 606                 return 0;
 607         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 608                 if (rscreen->b.family == CHIP_ARUBA ||
 609                     rscreen->b.family == CHIP_CAYMAN ||
 610                     rscreen->b.family == CHIP_CYPRESS ||
 611                     rscreen->b.family == CHIP_HEMLOCK)
 612                         return 1;
 613                 return 0;
 614         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 615         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 616         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 617         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 618         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 619                 return 0;
 620         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 621         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 622                 if (rscreen->b.family >= CHIP_CEDAR &&
 623                     (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE))
 624                     return 8;
 625                 return 0;
 626         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 627                 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
 628                         return 8;
 629                 return 0;
 630         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 631                 /* having to allocate the atomics out amongst shaders stages is messy,
 632                    so give compute 8 buffers and all the others one */
 633                 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) {
 634                         return EG_MAX_ATOMIC_BUFFERS;
 635                 }
 636                 return 0;
 637         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 638                 /* due to a bug in the shader compiler, some loops hang
 639                  * if they are not unrolled, see:
 640                  *    https://bugs.freedesktop.org/show_bug.cgi?id=86720
 641                  */
 642                 return 255;
 643         }
 644         return 0;
 645 }
 646
 647 static void r600_destroy_screen(struct pipe_screen* pscreen)
 648 {
 649         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 650
 651         if (!rscreen)
 652                 return;
 653
 654         if (!rscreen->b.ws->unref(rscreen->b.ws))
 655                 return;
 656
 657         if (rscreen->global_pool) {
 658                 compute_memory_pool_delete(rscreen->global_pool);
 659         }
 660
 661         r600_destroy_common_screen(&rscreen->b);
 662 }
 663
 664 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 665                                                   const struct pipe_resource *templ)
 666 {
 667         if (templ->target == PIPE_BUFFER &&
 668             (templ->bind & PIPE_BIND_GLOBAL))
 669                 return r600_compute_global_buffer_create(screen, templ);
 670
 671         return r600_resource_create_common(screen, templ);
 672 }
 673
 674 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws,
 675                                        const struct pipe_screen_config *config)
 676 {
 677         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 678
 679         if (!rscreen) {
 680                 return NULL;
 681         }
 682
 683         /* Set functions first. */
 684         rscreen->b.b.context_create = r600_create_context;
 685         rscreen->b.b.destroy = r600_destroy_screen;
 686         rscreen->b.b.get_param = r600_get_param;
 687         rscreen->b.b.get_shader_param = r600_get_shader_param;
 688         rscreen->b.b.resource_create = r600_resource_create;
 689
 690         if (!r600_common_screen_init(&rscreen->b, ws)) {
 691                 FREE(rscreen);
 692                 return NULL;
 693         }
 694
 695         if (rscreen->b.info.chip_class >= EVERGREEN) {
 696                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 697         } else {
 698                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 699         }
 700
 701         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 702         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 703                 rscreen->b.debug_flags |= DBG_COMPUTE;
 704         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 705                 rscreen->b.debug_flags |= DBG_ALL_SHADERS | DBG_FS;
 706         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
 707                 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
 708
 709         if (rscreen->b.family == CHIP_UNKNOWN) {
 710                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 711                 FREE(rscreen);
 712                 return NULL;
 713         }
 714
 715         /* Figure out streamout kernel support. */
 716         switch (rscreen->b.chip_class) {
 717         case R600:
 718                 if (rscreen->b.family < CHIP_RS780) {
 719                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 720                 } else {
 721                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 722                 }
 723                 break;
 724         case R700:
 725                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 726                 break;
 727         case EVERGREEN:
 728         case CAYMAN:
 729                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 730                 break;
 731         default:
 732                 rscreen->b.has_streamout = FALSE;
 733                 break;
 734         }
 735
 736         /* MSAA support. */
 737         switch (rscreen->b.chip_class) {
 738         case R600:
 739         case R700:
 740                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 741                 rscreen->has_compressed_msaa_texturing = false;
 742                 break;
 743         case EVERGREEN:
 744                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 745                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 746                 break;
 747         case CAYMAN:
 748                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 749                 rscreen->has_compressed_msaa_texturing = true;
 750                 break;
 751         default:
 752                 rscreen->has_msaa = FALSE;
 753                 rscreen->has_compressed_msaa_texturing = false;
 754         }
 755
 756         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 757                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 758
 759         rscreen->b.barrier_flags.cp_to_L2 =
 760                 R600_CONTEXT_INV_VERTEX_CACHE |
 761                 R600_CONTEXT_INV_TEX_CACHE |
 762                 R600_CONTEXT_INV_CONST_CACHE;
 763         rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_CS_PARTIAL_FLUSH | R600_CONTEXT_FLUSH_AND_INV;
 764
 765         rscreen->global_pool = compute_memory_pool_new(rscreen);
 766
 767         /* Create the auxiliary context. This must be done last. */
 768         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
 769
 770         rscreen->has_atomics = rscreen->b.info.drm_minor >= 44;
 771 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 772         struct pipe_resource templ = {};
 773
 774         templ.width0 = 4;
 775         templ.height0 = 2048;
 776         templ.depth0 = 1;
 777         templ.array_size = 1;
 778         templ.target = PIPE_TEXTURE_2D;
 779         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 780         templ.usage = PIPE_USAGE_DEFAULT;
 781
 782         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 783         unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_TRANSFER_WRITE);
 784
 785         memset(map, 0, 256);
 786
 787         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 788         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 789         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 790         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 791         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 792
 793         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 794
 795         int i;
 796         for (i = 0; i < 256; i++) {
 797                 printf("%02X", map[i]);
 798                 if (i % 16 == 15)
 799                         printf("\n");
 800         }
 801 #endif
 802
 803         if (rscreen->b.debug_flags & DBG_TEST_DMA)
 804                 r600_test_dma(&rscreen->b);
 805
 806         r600_query_fix_enabled_rb_mask(&rscreen->b);
 807         return &rscreen->b.b;
 808 }