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[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_pipe.h"
24 #include "r600_public.h"
25
26 #include <errno.h>
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_blitter.h"
29 #include "util/u_format_s3tc.h"
30 #include "util/u_simple_shaders.h"
31 #include "util/u_upload_mgr.h"
32 #include "vl/vl_decoder.h"
33 #include "vl/vl_video_buffer.h"
34 #include "os/os_time.h"
35
36 /*
37 * pipe_context
38 */
39 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
40 {
41 struct r600_screen *rscreen = rctx->screen;
42 struct r600_fence *fence = NULL;
43
44 pipe_mutex_lock(rscreen->fences.mutex);
45
46 if (!rscreen->fences.bo) {
47 /* Create the shared buffer object */
48 rscreen->fences.bo = (struct r600_resource*)
49 pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
50 PIPE_USAGE_STAGING, 4096);
51 if (!rscreen->fences.bo) {
52 R600_ERR("r600: failed to create bo for fence objects\n");
53 goto out;
54 }
55 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf,
56 rctx->cs,
57 PIPE_TRANSFER_READ_WRITE);
58 }
59
60 if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
61 struct r600_fence *entry;
62
63 /* Try to find a freed fence that has been signalled */
64 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
65 if (rscreen->fences.data[entry->index] != 0) {
66 LIST_DELINIT(&entry->head);
67 fence = entry;
68 break;
69 }
70 }
71 }
72
73 if (!fence) {
74 /* Allocate a new fence */
75 struct r600_fence_block *block;
76 unsigned index;
77
78 if ((rscreen->fences.next_index + 1) >= 1024) {
79 R600_ERR("r600: too many concurrent fences\n");
80 goto out;
81 }
82
83 index = rscreen->fences.next_index++;
84
85 if (!(index % FENCE_BLOCK_SIZE)) {
86 /* Allocate a new block */
87 block = CALLOC_STRUCT(r600_fence_block);
88 if (block == NULL)
89 goto out;
90
91 LIST_ADD(&block->head, &rscreen->fences.blocks);
92 } else {
93 block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
94 }
95
96 fence = &block->fences[index % FENCE_BLOCK_SIZE];
97 fence->index = index;
98 }
99
100 pipe_reference_init(&fence->reference, 1);
101
102 rscreen->fences.data[fence->index] = 0;
103 r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
104
105 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
106 fence->sleep_bo = (struct r600_resource*)
107 pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
108 PIPE_USAGE_STAGING, 1);
109 /* Add the fence as a dummy relocation. */
110 r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
111
112 out:
113 pipe_mutex_unlock(rscreen->fences.mutex);
114 return fence;
115 }
116
117
118 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
119 unsigned flags)
120 {
121 struct r600_context *rctx = (struct r600_context *)ctx;
122 struct r600_fence **rfence = (struct r600_fence**)fence;
123 struct pipe_query *render_cond = NULL;
124 unsigned render_cond_mode = 0;
125
126 if (rfence)
127 *rfence = r600_create_fence(rctx);
128
129 /* Disable render condition. */
130 if (rctx->current_render_cond) {
131 render_cond = rctx->current_render_cond;
132 render_cond_mode = rctx->current_render_cond_mode;
133 ctx->render_condition(ctx, NULL, 0);
134 }
135
136 r600_context_flush(rctx, flags);
137
138 /* Re-enable render condition. */
139 if (render_cond) {
140 ctx->render_condition(ctx, render_cond, render_cond_mode);
141 }
142 }
143
144 static void r600_flush_from_st(struct pipe_context *ctx,
145 struct pipe_fence_handle **fence)
146 {
147 r600_flush(ctx, fence, 0);
148 }
149
150 static void r600_flush_from_winsys(void *ctx, unsigned flags)
151 {
152 r600_flush((struct pipe_context*)ctx, NULL, flags);
153 }
154
155 static void r600_destroy_context(struct pipe_context *context)
156 {
157 struct r600_context *rctx = (struct r600_context *)context;
158
159 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
160 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
161
162 if (rctx->no_blend) {
163 rctx->context.delete_blend_state(&rctx->context, rctx->no_blend);
164 }
165 if (rctx->dummy_pixel_shader) {
166 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
167 }
168 if (rctx->custom_dsa_flush) {
169 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
170 }
171 if (rctx->custom_blend_resolve) {
172 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve);
173 }
174 if (rctx->custom_blend_decompress) {
175 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_decompress);
176 }
177 util_unreference_framebuffer_state(&rctx->framebuffer);
178
179 r600_context_fini(rctx);
180
181 if (rctx->blitter) {
182 util_blitter_destroy(rctx->blitter);
183 }
184 for (int i = 0; i < R600_PIPE_NSTATES; i++) {
185 free(rctx->states[i]);
186 }
187
188 if (rctx->uploader) {
189 u_upload_destroy(rctx->uploader);
190 }
191 util_slab_destroy(&rctx->pool_transfers);
192
193 r600_release_command_buffer(&rctx->start_cs_cmd);
194
195 if (rctx->cs) {
196 rctx->ws->cs_destroy(rctx->cs);
197 }
198
199 FREE(rctx->range);
200 FREE(rctx);
201 }
202
203 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
204 {
205 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
206 struct r600_screen* rscreen = (struct r600_screen *)screen;
207 struct pipe_blend_state no_blend = {};
208
209 if (rctx == NULL)
210 return NULL;
211
212 util_slab_create(&rctx->pool_transfers,
213 sizeof(struct r600_transfer), 64,
214 UTIL_SLAB_SINGLETHREADED);
215
216 rctx->context.screen = screen;
217 rctx->context.priv = priv;
218 rctx->context.destroy = r600_destroy_context;
219 rctx->context.flush = r600_flush_from_st;
220
221 /* Easy accessing of screen/winsys. */
222 rctx->screen = rscreen;
223 rctx->ws = rscreen->ws;
224 rctx->family = rscreen->family;
225 rctx->chip_class = rscreen->chip_class;
226
227 LIST_INITHEAD(&rctx->dirty_states);
228 LIST_INITHEAD(&rctx->active_timer_queries);
229 LIST_INITHEAD(&rctx->active_nontimer_queries);
230 LIST_INITHEAD(&rctx->dirty);
231 LIST_INITHEAD(&rctx->enable_list);
232
233 rctx->range = CALLOC(NUM_RANGES, sizeof(struct r600_range));
234 if (!rctx->range)
235 goto fail;
236
237 r600_init_blit_functions(rctx);
238 r600_init_query_functions(rctx);
239 r600_init_context_resource_functions(rctx);
240 r600_init_surface_functions(rctx);
241 rctx->context.draw_vbo = r600_draw_vbo;
242
243 rctx->context.create_video_decoder = vl_create_decoder;
244 rctx->context.create_video_buffer = vl_video_buffer_create;
245
246 r600_init_common_atoms(rctx);
247
248 switch (rctx->chip_class) {
249 case R600:
250 case R700:
251 r600_init_state_functions(rctx);
252 r600_init_atom_start_cs(rctx);
253 if (r600_context_init(rctx))
254 goto fail;
255 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
256 rctx->custom_blend_resolve = rctx->chip_class == R700 ? r700_create_resolve_blend(rctx)
257 : r600_create_resolve_blend(rctx);
258 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
259 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
260 rctx->family == CHIP_RV620 ||
261 rctx->family == CHIP_RS780 ||
262 rctx->family == CHIP_RS880 ||
263 rctx->family == CHIP_RV710);
264 break;
265 case EVERGREEN:
266 case CAYMAN:
267 evergreen_init_state_functions(rctx);
268 evergreen_init_atom_start_cs(rctx);
269 evergreen_init_atom_start_compute_cs(rctx);
270 if (evergreen_context_init(rctx))
271 goto fail;
272 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
273 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
274 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
275 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
276 rctx->family == CHIP_PALM ||
277 rctx->family == CHIP_SUMO ||
278 rctx->family == CHIP_SUMO2 ||
279 rctx->family == CHIP_CAICOS ||
280 rctx->family == CHIP_CAYMAN ||
281 rctx->family == CHIP_ARUBA);
282 break;
283 default:
284 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
285 goto fail;
286 }
287
288 rctx->cs = rctx->ws->cs_create(rctx->ws);
289 rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
290 r600_emit_atom(rctx, &rctx->start_cs_cmd.atom);
291
292 rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
293 PIPE_BIND_INDEX_BUFFER |
294 PIPE_BIND_CONSTANT_BUFFER);
295 if (!rctx->uploader)
296 goto fail;
297
298 rctx->blitter = util_blitter_create(&rctx->context);
299 if (rctx->blitter == NULL)
300 goto fail;
301 rctx->blitter->draw_rectangle = r600_draw_rectangle;
302
303 r600_get_backend_mask(rctx); /* this emits commands and must be last */
304
305 if (rctx->chip_class == R600)
306 r600_set_max_scissor(rctx);
307
308 rctx->dummy_pixel_shader =
309 util_make_fragment_cloneinput_shader(&rctx->context, 0,
310 TGSI_SEMANTIC_GENERIC,
311 TGSI_INTERPOLATE_CONSTANT);
312 rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
313
314 no_blend.rt[0].colormask = 0xF;
315 rctx->no_blend = rctx->context.create_blend_state(&rctx->context, &no_blend);
316
317 return &rctx->context;
318
319 fail:
320 r600_destroy_context(&rctx->context);
321 return NULL;
322 }
323
324 /*
325 * pipe_screen
326 */
327 static const char* r600_get_vendor(struct pipe_screen* pscreen)
328 {
329 return "X.Org";
330 }
331
332 static const char *r600_get_family_name(enum radeon_family family)
333 {
334 switch(family) {
335 case CHIP_R600: return "AMD R600";
336 case CHIP_RV610: return "AMD RV610";
337 case CHIP_RV630: return "AMD RV630";
338 case CHIP_RV670: return "AMD RV670";
339 case CHIP_RV620: return "AMD RV620";
340 case CHIP_RV635: return "AMD RV635";
341 case CHIP_RS780: return "AMD RS780";
342 case CHIP_RS880: return "AMD RS880";
343 case CHIP_RV770: return "AMD RV770";
344 case CHIP_RV730: return "AMD RV730";
345 case CHIP_RV710: return "AMD RV710";
346 case CHIP_RV740: return "AMD RV740";
347 case CHIP_CEDAR: return "AMD CEDAR";
348 case CHIP_REDWOOD: return "AMD REDWOOD";
349 case CHIP_JUNIPER: return "AMD JUNIPER";
350 case CHIP_CYPRESS: return "AMD CYPRESS";
351 case CHIP_HEMLOCK: return "AMD HEMLOCK";
352 case CHIP_PALM: return "AMD PALM";
353 case CHIP_SUMO: return "AMD SUMO";
354 case CHIP_SUMO2: return "AMD SUMO2";
355 case CHIP_BARTS: return "AMD BARTS";
356 case CHIP_TURKS: return "AMD TURKS";
357 case CHIP_CAICOS: return "AMD CAICOS";
358 case CHIP_CAYMAN: return "AMD CAYMAN";
359 case CHIP_ARUBA: return "AMD ARUBA";
360 default: return "AMD unknown";
361 }
362 }
363
364 static const char* r600_get_name(struct pipe_screen* pscreen)
365 {
366 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
367
368 return r600_get_family_name(rscreen->family);
369 }
370
371 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
372 {
373 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
374 enum radeon_family family = rscreen->family;
375
376 switch (param) {
377 /* Supported features (boolean caps). */
378 case PIPE_CAP_NPOT_TEXTURES:
379 case PIPE_CAP_TWO_SIDED_STENCIL:
380 case PIPE_CAP_ANISOTROPIC_FILTER:
381 case PIPE_CAP_POINT_SPRITE:
382 case PIPE_CAP_OCCLUSION_QUERY:
383 case PIPE_CAP_TEXTURE_SHADOW_MAP:
384 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
385 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
386 case PIPE_CAP_TEXTURE_SWIZZLE:
387 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
388 case PIPE_CAP_DEPTH_CLIP_DISABLE:
389 case PIPE_CAP_SHADER_STENCIL_EXPORT:
390 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
391 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
392 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
393 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
394 case PIPE_CAP_SM3:
395 case PIPE_CAP_SEAMLESS_CUBE_MAP:
396 case PIPE_CAP_PRIMITIVE_RESTART:
397 case PIPE_CAP_CONDITIONAL_RENDER:
398 case PIPE_CAP_TEXTURE_BARRIER:
399 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
400 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
401 case PIPE_CAP_TGSI_INSTANCEID:
402 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
403 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
404 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
405 case PIPE_CAP_USER_INDEX_BUFFERS:
406 case PIPE_CAP_USER_CONSTANT_BUFFERS:
407 case PIPE_CAP_COMPUTE:
408 case PIPE_CAP_START_INSTANCE:
409 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
410 return 1;
411
412 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
413 return 256;
414
415 case PIPE_CAP_GLSL_FEATURE_LEVEL:
416 return 130;
417
418 /* Supported except the original R600. */
419 case PIPE_CAP_INDEP_BLEND_ENABLE:
420 case PIPE_CAP_INDEP_BLEND_FUNC:
421 /* R600 doesn't support per-MRT blends */
422 return family == CHIP_R600 ? 0 : 1;
423
424 /* Supported on Evergreen. */
425 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
426 return family >= CHIP_CEDAR ? 1 : 0;
427
428 /* Unsupported features. */
429 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
430 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
431 case PIPE_CAP_SCALED_RESOLVE:
432 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
433 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
434 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
435 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
436 case PIPE_CAP_USER_VERTEX_BUFFERS:
437 return 0;
438
439 /* Stream output. */
440 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
441 return rscreen->has_streamout ? 4 : 0;
442 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
443 return rscreen->has_streamout ? 1 : 0;
444 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
445 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
446 return 16*4;
447
448 /* Texturing. */
449 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
450 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
451 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
452 if (family >= CHIP_CEDAR)
453 return 15;
454 else
455 return 14;
456 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
457 return rscreen->info.drm_minor >= 9 ?
458 (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
459 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
460 return 32;
461
462 /* Render targets. */
463 case PIPE_CAP_MAX_RENDER_TARGETS:
464 /* XXX some r6xx are buggy and can only do 4 */
465 return 8;
466
467 /* Timer queries, present when the clock frequency is non zero. */
468 case PIPE_CAP_TIMER_QUERY:
469 return rscreen->info.r600_clock_crystal_freq != 0;
470 case PIPE_CAP_QUERY_TIMESTAMP:
471 return rscreen->info.drm_minor >= 20 &&
472 rscreen->info.r600_clock_crystal_freq != 0;
473
474 case PIPE_CAP_MIN_TEXEL_OFFSET:
475 return -8;
476
477 case PIPE_CAP_MAX_TEXEL_OFFSET:
478 return 7;
479 }
480 return 0;
481 }
482
483 static float r600_get_paramf(struct pipe_screen* pscreen,
484 enum pipe_capf param)
485 {
486 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
487 enum radeon_family family = rscreen->family;
488
489 switch (param) {
490 case PIPE_CAPF_MAX_LINE_WIDTH:
491 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
492 case PIPE_CAPF_MAX_POINT_WIDTH:
493 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
494 if (family >= CHIP_CEDAR)
495 return 16384.0f;
496 else
497 return 8192.0f;
498 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
499 return 16.0f;
500 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
501 return 16.0f;
502 case PIPE_CAPF_GUARD_BAND_LEFT:
503 case PIPE_CAPF_GUARD_BAND_TOP:
504 case PIPE_CAPF_GUARD_BAND_RIGHT:
505 case PIPE_CAPF_GUARD_BAND_BOTTOM:
506 return 0.0f;
507 }
508 return 0.0f;
509 }
510
511 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
512 {
513 switch(shader)
514 {
515 case PIPE_SHADER_FRAGMENT:
516 case PIPE_SHADER_VERTEX:
517 case PIPE_SHADER_COMPUTE:
518 break;
519 case PIPE_SHADER_GEOMETRY:
520 /* XXX: support and enable geometry programs */
521 return 0;
522 default:
523 /* XXX: support tessellation on Evergreen */
524 return 0;
525 }
526
527 /* XXX: all these should be fixed, since r600 surely supports much more! */
528 switch (param) {
529 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
530 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
531 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
532 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
533 return 16384;
534 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
535 return 8; /* XXX */
536 case PIPE_SHADER_CAP_MAX_INPUTS:
537 if(shader == PIPE_SHADER_FRAGMENT)
538 return 34;
539 else
540 return 32;
541 case PIPE_SHADER_CAP_MAX_TEMPS:
542 return 256; /* Max native temporaries. */
543 case PIPE_SHADER_CAP_MAX_ADDRS:
544 /* XXX Isn't this equal to TEMPS? */
545 return 1; /* Max native address registers */
546 case PIPE_SHADER_CAP_MAX_CONSTS:
547 return R600_MAX_CONST_BUFFER_SIZE;
548 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
549 return R600_MAX_CONST_BUFFERS-1;
550 case PIPE_SHADER_CAP_MAX_PREDS:
551 return 0; /* nothing uses this */
552 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
553 return 1;
554 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
555 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
556 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
557 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
558 return 1;
559 case PIPE_SHADER_CAP_SUBROUTINES:
560 return 0;
561 case PIPE_SHADER_CAP_INTEGERS:
562 return 1;
563 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
564 return 16;
565 case PIPE_SHADER_CAP_PREFERRED_IR:
566 if (shader == PIPE_SHADER_COMPUTE) {
567 return PIPE_SHADER_IR_LLVM;
568 } else {
569 return PIPE_SHADER_IR_TGSI;
570 }
571 }
572 return 0;
573 }
574
575 static int r600_get_video_param(struct pipe_screen *screen,
576 enum pipe_video_profile profile,
577 enum pipe_video_cap param)
578 {
579 switch (param) {
580 case PIPE_VIDEO_CAP_SUPPORTED:
581 return vl_profile_supported(screen, profile);
582 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
583 return 1;
584 case PIPE_VIDEO_CAP_MAX_WIDTH:
585 case PIPE_VIDEO_CAP_MAX_HEIGHT:
586 return vl_video_buffer_max_size(screen);
587 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
588 return PIPE_FORMAT_NV12;
589 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
590 return false;
591 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
592 return false;
593 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
594 return true;
595 default:
596 return 0;
597 }
598 }
599
600 static int r600_get_compute_param(struct pipe_screen *screen,
601 enum pipe_compute_cap param,
602 void *ret)
603 {
604 //TODO: select these params by asic
605 switch (param) {
606 case PIPE_COMPUTE_CAP_IR_TARGET:
607 if (ret) {
608 strcpy(ret, "r600--");
609 }
610 return 7 * sizeof(char);
611
612 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
613 if (ret) {
614 uint64_t * grid_dimension = ret;
615 grid_dimension[0] = 3;
616 }
617 return 1 * sizeof(uint64_t);
618
619 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
620 if (ret) {
621 uint64_t * grid_size = ret;
622 grid_size[0] = 65535;
623 grid_size[1] = 65535;
624 grid_size[2] = 1;
625 }
626 return 3 * sizeof(uint64_t) ;
627
628 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
629 if (ret) {
630 uint64_t * block_size = ret;
631 block_size[0] = 256;
632 block_size[1] = 256;
633 block_size[2] = 256;
634 }
635 return 3 * sizeof(uint64_t);
636
637 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
638 if (ret) {
639 uint64_t * max_threads_per_block = ret;
640 *max_threads_per_block = 256;
641 }
642 return sizeof(uint64_t);
643
644 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
645 if (ret) {
646 uint64_t * max_global_size = ret;
647 /* XXX: This is 64kb for now until we get the
648 * compute memory pool working correctly.
649 */
650 *max_global_size = 1024 * 16 * 4;
651 }
652 return sizeof(uint64_t);
653
654 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
655 if (ret) {
656 uint64_t * max_input_size = ret;
657 *max_input_size = 1024;
658 }
659 return sizeof(uint64_t);
660
661 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
662 if (ret) {
663 uint64_t * max_local_size = ret;
664 /* XXX: This is what the proprietary driver reports, we
665 * may want to use a different value. */
666 *max_local_size = 32768;
667 }
668 return sizeof(uint64_t);
669
670 default:
671 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
672 return 0;
673 }
674 }
675
676 static void r600_destroy_screen(struct pipe_screen* pscreen)
677 {
678 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
679
680 if (rscreen == NULL)
681 return;
682
683 if (rscreen->global_pool) {
684 compute_memory_pool_delete(rscreen->global_pool);
685 }
686
687 if (rscreen->fences.bo) {
688 struct r600_fence_block *entry, *tmp;
689
690 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
691 LIST_DEL(&entry->head);
692 FREE(entry);
693 }
694
695 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
696 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
697 }
698 pipe_mutex_destroy(rscreen->fences.mutex);
699
700 rscreen->ws->destroy(rscreen->ws);
701 FREE(rscreen);
702 }
703
704 static void r600_fence_reference(struct pipe_screen *pscreen,
705 struct pipe_fence_handle **ptr,
706 struct pipe_fence_handle *fence)
707 {
708 struct r600_fence **oldf = (struct r600_fence**)ptr;
709 struct r600_fence *newf = (struct r600_fence*)fence;
710
711 if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
712 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
713 pipe_mutex_lock(rscreen->fences.mutex);
714 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
715 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
716 pipe_mutex_unlock(rscreen->fences.mutex);
717 }
718
719 *ptr = fence;
720 }
721
722 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
723 struct pipe_fence_handle *fence)
724 {
725 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
726 struct r600_fence *rfence = (struct r600_fence*)fence;
727
728 return rscreen->fences.data[rfence->index];
729 }
730
731 static boolean r600_fence_finish(struct pipe_screen *pscreen,
732 struct pipe_fence_handle *fence,
733 uint64_t timeout)
734 {
735 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
736 struct r600_fence *rfence = (struct r600_fence*)fence;
737 int64_t start_time = 0;
738 unsigned spins = 0;
739
740 if (timeout != PIPE_TIMEOUT_INFINITE) {
741 start_time = os_time_get();
742
743 /* Convert to microseconds. */
744 timeout /= 1000;
745 }
746
747 while (rscreen->fences.data[rfence->index] == 0) {
748 /* Special-case infinite timeout - wait for the dummy BO to become idle */
749 if (timeout == PIPE_TIMEOUT_INFINITE) {
750 rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
751 break;
752 }
753
754 /* The dummy BO will be busy until the CS including the fence has completed, or
755 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
756 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
757 break;
758
759 if (++spins % 256)
760 continue;
761 #ifdef PIPE_OS_UNIX
762 sched_yield();
763 #else
764 os_time_sleep(10);
765 #endif
766 if (timeout != PIPE_TIMEOUT_INFINITE &&
767 os_time_get() - start_time >= timeout) {
768 break;
769 }
770 }
771
772 return rscreen->fences.data[rfence->index] != 0;
773 }
774
775 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
776 {
777 switch ((tiling_config & 0xe) >> 1) {
778 case 0:
779 rscreen->tiling_info.num_channels = 1;
780 break;
781 case 1:
782 rscreen->tiling_info.num_channels = 2;
783 break;
784 case 2:
785 rscreen->tiling_info.num_channels = 4;
786 break;
787 case 3:
788 rscreen->tiling_info.num_channels = 8;
789 break;
790 default:
791 return -EINVAL;
792 }
793
794 switch ((tiling_config & 0x30) >> 4) {
795 case 0:
796 rscreen->tiling_info.num_banks = 4;
797 break;
798 case 1:
799 rscreen->tiling_info.num_banks = 8;
800 break;
801 default:
802 return -EINVAL;
803
804 }
805 switch ((tiling_config & 0xc0) >> 6) {
806 case 0:
807 rscreen->tiling_info.group_bytes = 256;
808 break;
809 case 1:
810 rscreen->tiling_info.group_bytes = 512;
811 break;
812 default:
813 return -EINVAL;
814 }
815 return 0;
816 }
817
818 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
819 {
820 switch (tiling_config & 0xf) {
821 case 0:
822 rscreen->tiling_info.num_channels = 1;
823 break;
824 case 1:
825 rscreen->tiling_info.num_channels = 2;
826 break;
827 case 2:
828 rscreen->tiling_info.num_channels = 4;
829 break;
830 case 3:
831 rscreen->tiling_info.num_channels = 8;
832 break;
833 default:
834 return -EINVAL;
835 }
836
837 switch ((tiling_config & 0xf0) >> 4) {
838 case 0:
839 rscreen->tiling_info.num_banks = 4;
840 break;
841 case 1:
842 rscreen->tiling_info.num_banks = 8;
843 break;
844 case 2:
845 rscreen->tiling_info.num_banks = 16;
846 break;
847 default:
848 return -EINVAL;
849 }
850
851 switch ((tiling_config & 0xf00) >> 8) {
852 case 0:
853 rscreen->tiling_info.group_bytes = 256;
854 break;
855 case 1:
856 rscreen->tiling_info.group_bytes = 512;
857 break;
858 default:
859 return -EINVAL;
860 }
861 return 0;
862 }
863
864 static int r600_init_tiling(struct r600_screen *rscreen)
865 {
866 uint32_t tiling_config = rscreen->info.r600_tiling_config;
867
868 /* set default group bytes, overridden by tiling info ioctl */
869 if (rscreen->chip_class <= R700) {
870 rscreen->tiling_info.group_bytes = 256;
871 } else {
872 rscreen->tiling_info.group_bytes = 512;
873 }
874
875 if (!tiling_config)
876 return 0;
877
878 if (rscreen->chip_class <= R700) {
879 return r600_interpret_tiling(rscreen, tiling_config);
880 } else {
881 return evergreen_interpret_tiling(rscreen, tiling_config);
882 }
883 }
884
885 static unsigned radeon_family_from_device(unsigned device)
886 {
887 switch (device) {
888 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
889 #include "pci_ids/r600_pci_ids.h"
890 #undef CHIPSET
891 default:
892 return CHIP_UNKNOWN;
893 }
894 }
895
896 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
897 {
898 struct r600_screen *rscreen = (struct r600_screen*)screen;
899
900 return 1000000 * rscreen->ws->query_timestamp(rscreen->ws) /
901 rscreen->info.r600_clock_crystal_freq;
902 }
903
904 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
905 {
906 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
907
908 if (rscreen == NULL) {
909 return NULL;
910 }
911
912 rscreen->ws = ws;
913 ws->query_info(ws, &rscreen->info);
914
915 rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
916 if (rscreen->family == CHIP_UNKNOWN) {
917 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
918 FREE(rscreen);
919 return NULL;
920 }
921
922 /* setup class */
923 if (rscreen->family >= CHIP_CAYMAN) {
924 rscreen->chip_class = CAYMAN;
925 } else if (rscreen->family >= CHIP_CEDAR) {
926 rscreen->chip_class = EVERGREEN;
927 } else if (rscreen->family >= CHIP_RV770) {
928 rscreen->chip_class = R700;
929 } else {
930 rscreen->chip_class = R600;
931 }
932
933 /* Figure out streamout kernel support. */
934 switch (rscreen->chip_class) {
935 case R600:
936 case EVERGREEN:
937 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
938 break;
939 case R700:
940 rscreen->has_streamout = rscreen->info.drm_minor >= 17;
941 break;
942 /* TODO: Cayman */
943 default:
944 rscreen->has_streamout = debug_get_bool_option("R600_STREAMOUT", FALSE);
945 }
946
947 if (r600_init_tiling(rscreen)) {
948 FREE(rscreen);
949 return NULL;
950 }
951
952 rscreen->screen.destroy = r600_destroy_screen;
953 rscreen->screen.get_name = r600_get_name;
954 rscreen->screen.get_vendor = r600_get_vendor;
955 rscreen->screen.get_param = r600_get_param;
956 rscreen->screen.get_shader_param = r600_get_shader_param;
957 rscreen->screen.get_paramf = r600_get_paramf;
958 rscreen->screen.get_video_param = r600_get_video_param;
959 rscreen->screen.get_compute_param = r600_get_compute_param;
960 rscreen->screen.get_timestamp = r600_get_timestamp;
961
962 if (rscreen->chip_class >= EVERGREEN) {
963 rscreen->screen.is_format_supported = evergreen_is_format_supported;
964 } else {
965 rscreen->screen.is_format_supported = r600_is_format_supported;
966 }
967 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
968 rscreen->screen.context_create = r600_create_context;
969 rscreen->screen.fence_reference = r600_fence_reference;
970 rscreen->screen.fence_signalled = r600_fence_signalled;
971 rscreen->screen.fence_finish = r600_fence_finish;
972 r600_init_screen_resource_functions(&rscreen->screen);
973
974 util_format_s3tc_init();
975
976 rscreen->fences.bo = NULL;
977 rscreen->fences.data = NULL;
978 rscreen->fences.next_index = 0;
979 LIST_INITHEAD(&rscreen->fences.pool);
980 LIST_INITHEAD(&rscreen->fences.blocks);
981 pipe_mutex_init(rscreen->fences.mutex);
982
983 rscreen->global_pool = compute_memory_pool_new(rscreen);
984
985 return &rscreen->screen;
986 }