gallium: remove PIPE_SHADER_CAP_OUTPUT_READ
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "tgsi/tgsi_scan.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31 #include "util/u_blitter.h"
32 #include "util/u_double_list.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_transfer.h"
36 #include "util/u_surface.h"
37 #include "util/u_pack_color.h"
38 #include "util/u_memory.h"
39 #include "util/u_inlines.h"
40 #include "util/u_upload_mgr.h"
41 #include "vl/vl_decoder.h"
42 #include "vl/vl_video_buffer.h"
43 #include "os/os_time.h"
44 #include "pipebuffer/pb_buffer.h"
45 #include "r600.h"
46 #include "r600d.h"
47 #include "r600_resource.h"
48 #include "r600_shader.h"
49 #include "r600_pipe.h"
50 #include "r600_hw_context_priv.h"
51
52 /*
53 * pipe_context
54 */
55 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
56 {
57 struct r600_screen *rscreen = rctx->screen;
58 struct r600_fence *fence = NULL;
59
60 pipe_mutex_lock(rscreen->fences.mutex);
61
62 if (!rscreen->fences.bo) {
63 /* Create the shared buffer object */
64 rscreen->fences.bo = (struct r600_resource*)
65 pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
66 PIPE_USAGE_STAGING, 4096);
67 if (!rscreen->fences.bo) {
68 R600_ERR("r600: failed to create bo for fence objects\n");
69 goto out;
70 }
71 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->buf,
72 rctx->cs,
73 PIPE_TRANSFER_READ_WRITE);
74 }
75
76 if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
77 struct r600_fence *entry;
78
79 /* Try to find a freed fence that has been signalled */
80 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
81 if (rscreen->fences.data[entry->index] != 0) {
82 LIST_DELINIT(&entry->head);
83 fence = entry;
84 break;
85 }
86 }
87 }
88
89 if (!fence) {
90 /* Allocate a new fence */
91 struct r600_fence_block *block;
92 unsigned index;
93
94 if ((rscreen->fences.next_index + 1) >= 1024) {
95 R600_ERR("r600: too many concurrent fences\n");
96 goto out;
97 }
98
99 index = rscreen->fences.next_index++;
100
101 if (!(index % FENCE_BLOCK_SIZE)) {
102 /* Allocate a new block */
103 block = CALLOC_STRUCT(r600_fence_block);
104 if (block == NULL)
105 goto out;
106
107 LIST_ADD(&block->head, &rscreen->fences.blocks);
108 } else {
109 block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
110 }
111
112 fence = &block->fences[index % FENCE_BLOCK_SIZE];
113 fence->index = index;
114 }
115
116 pipe_reference_init(&fence->reference, 1);
117
118 rscreen->fences.data[fence->index] = 0;
119 r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
120
121 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
122 fence->sleep_bo = (struct r600_resource*)
123 pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
124 PIPE_USAGE_STAGING, 1);
125 /* Add the fence as a dummy relocation. */
126 r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
127
128 out:
129 pipe_mutex_unlock(rscreen->fences.mutex);
130 return fence;
131 }
132
133
134 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
135 unsigned flags)
136 {
137 struct r600_context *rctx = (struct r600_context *)ctx;
138 struct r600_fence **rfence = (struct r600_fence**)fence;
139 struct pipe_query *render_cond = NULL;
140 unsigned render_cond_mode = 0;
141
142 if (rfence)
143 *rfence = r600_create_fence(rctx);
144
145 /* Disable render condition. */
146 if (rctx->current_render_cond) {
147 render_cond = rctx->current_render_cond;
148 render_cond_mode = rctx->current_render_cond_mode;
149 ctx->render_condition(ctx, NULL, 0);
150 }
151
152 r600_context_flush(rctx, flags);
153
154 /* Re-enable render condition. */
155 if (render_cond) {
156 ctx->render_condition(ctx, render_cond, render_cond_mode);
157 }
158 }
159
160 static void r600_flush_from_st(struct pipe_context *ctx,
161 struct pipe_fence_handle **fence)
162 {
163 r600_flush(ctx, fence, 0);
164 }
165
166 static void r600_flush_from_winsys(void *ctx, unsigned flags)
167 {
168 r600_flush((struct pipe_context*)ctx, NULL, flags);
169 }
170
171 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
172 {
173 pipe_mutex_lock(rscreen->mutex_num_contexts);
174 if (diff > 0) {
175 rscreen->num_contexts++;
176
177 if (rscreen->num_contexts > 1)
178 util_slab_set_thread_safety(&rscreen->pool_buffers,
179 UTIL_SLAB_MULTITHREADED);
180 } else {
181 rscreen->num_contexts--;
182
183 if (rscreen->num_contexts <= 1)
184 util_slab_set_thread_safety(&rscreen->pool_buffers,
185 UTIL_SLAB_SINGLETHREADED);
186 }
187 pipe_mutex_unlock(rscreen->mutex_num_contexts);
188 }
189
190 static void r600_destroy_context(struct pipe_context *context)
191 {
192 struct r600_context *rctx = (struct r600_context *)context;
193
194 if (rctx->custom_dsa_flush) {
195 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
196 }
197 util_unreference_framebuffer_state(&rctx->framebuffer);
198
199 r600_context_fini(rctx);
200
201 if (rctx->blitter) {
202 util_blitter_destroy(rctx->blitter);
203 }
204 for (int i = 0; i < R600_PIPE_NSTATES; i++) {
205 free(rctx->states[i]);
206 }
207
208 if (rctx->vbuf_mgr) {
209 u_vbuf_destroy(rctx->vbuf_mgr);
210 }
211 util_slab_destroy(&rctx->pool_transfers);
212
213 r600_update_num_contexts(rctx->screen, -1);
214
215 r600_release_command_buffer(&rctx->atom_start_cs);
216
217 if (rctx->cs) {
218 rctx->ws->cs_destroy(rctx->cs);
219 }
220
221 FREE(rctx->range);
222 FREE(rctx);
223 }
224
225 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
226 {
227 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
228 struct r600_screen* rscreen = (struct r600_screen *)screen;
229
230 if (rctx == NULL)
231 return NULL;
232
233 util_slab_create(&rctx->pool_transfers,
234 sizeof(struct pipe_transfer), 64,
235 UTIL_SLAB_SINGLETHREADED);
236
237 r600_update_num_contexts(rscreen, 1);
238
239 rctx->context.screen = screen;
240 rctx->context.priv = priv;
241 rctx->context.destroy = r600_destroy_context;
242 rctx->context.flush = r600_flush_from_st;
243
244 /* Easy accessing of screen/winsys. */
245 rctx->screen = rscreen;
246 rctx->ws = rscreen->ws;
247 rctx->family = rscreen->family;
248 rctx->chip_class = rscreen->chip_class;
249
250 LIST_INITHEAD(&rctx->dirty_states);
251 LIST_INITHEAD(&rctx->active_query_list);
252 LIST_INITHEAD(&rctx->dirty);
253 LIST_INITHEAD(&rctx->resource_dirty);
254 LIST_INITHEAD(&rctx->enable_list);
255
256 rctx->range = CALLOC(NUM_RANGES, sizeof(struct r600_range));
257 if (!rctx->range)
258 goto fail;
259
260 r600_init_blit_functions(rctx);
261 r600_init_query_functions(rctx);
262 r600_init_context_resource_functions(rctx);
263 r600_init_surface_functions(rctx);
264 rctx->context.draw_vbo = r600_draw_vbo;
265
266 rctx->context.create_video_decoder = vl_create_decoder;
267 rctx->context.create_video_buffer = vl_video_buffer_create;
268
269 r600_init_common_atoms(rctx);
270
271 switch (rctx->chip_class) {
272 case R600:
273 case R700:
274 r600_init_state_functions(rctx);
275 r600_init_atom_start_cs(rctx);
276 if (r600_context_init(rctx))
277 goto fail;
278 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
279 break;
280 case EVERGREEN:
281 case CAYMAN:
282 evergreen_init_state_functions(rctx);
283 evergreen_init_atom_start_cs(rctx);
284 if (evergreen_context_init(rctx))
285 goto fail;
286 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
287 break;
288 default:
289 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
290 goto fail;
291 }
292
293 rctx->cs = rctx->ws->cs_create(rctx->ws);
294 rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
295 r600_emit_atom(rctx, &rctx->atom_start_cs.atom);
296
297 rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256,
298 PIPE_BIND_VERTEX_BUFFER |
299 PIPE_BIND_INDEX_BUFFER |
300 PIPE_BIND_CONSTANT_BUFFER,
301 U_VERTEX_FETCH_DWORD_ALIGNED);
302 if (!rctx->vbuf_mgr)
303 goto fail;
304 rctx->vbuf_mgr->caps.format_fixed32 = 0;
305
306 rctx->blitter = util_blitter_create(&rctx->context);
307 if (rctx->blitter == NULL)
308 goto fail;
309
310 r600_get_backend_mask(rctx); /* this emits commands and must be last */
311
312 return &rctx->context;
313
314 fail:
315 r600_destroy_context(&rctx->context);
316 return NULL;
317 }
318
319 /*
320 * pipe_screen
321 */
322 static const char* r600_get_vendor(struct pipe_screen* pscreen)
323 {
324 return "X.Org";
325 }
326
327 static const char *r600_get_family_name(enum radeon_family family)
328 {
329 switch(family) {
330 case CHIP_R600: return "AMD R600";
331 case CHIP_RV610: return "AMD RV610";
332 case CHIP_RV630: return "AMD RV630";
333 case CHIP_RV670: return "AMD RV670";
334 case CHIP_RV620: return "AMD RV620";
335 case CHIP_RV635: return "AMD RV635";
336 case CHIP_RS780: return "AMD RS780";
337 case CHIP_RS880: return "AMD RS880";
338 case CHIP_RV770: return "AMD RV770";
339 case CHIP_RV730: return "AMD RV730";
340 case CHIP_RV710: return "AMD RV710";
341 case CHIP_RV740: return "AMD RV740";
342 case CHIP_CEDAR: return "AMD CEDAR";
343 case CHIP_REDWOOD: return "AMD REDWOOD";
344 case CHIP_JUNIPER: return "AMD JUNIPER";
345 case CHIP_CYPRESS: return "AMD CYPRESS";
346 case CHIP_HEMLOCK: return "AMD HEMLOCK";
347 case CHIP_PALM: return "AMD PALM";
348 case CHIP_SUMO: return "AMD SUMO";
349 case CHIP_SUMO2: return "AMD SUMO2";
350 case CHIP_BARTS: return "AMD BARTS";
351 case CHIP_TURKS: return "AMD TURKS";
352 case CHIP_CAICOS: return "AMD CAICOS";
353 case CHIP_CAYMAN: return "AMD CAYMAN";
354 default: return "AMD unknown";
355 }
356 }
357
358 static const char* r600_get_name(struct pipe_screen* pscreen)
359 {
360 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
361
362 return r600_get_family_name(rscreen->family);
363 }
364
365 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
366 {
367 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
368 enum radeon_family family = rscreen->family;
369
370 switch (param) {
371 /* Supported features (boolean caps). */
372 case PIPE_CAP_NPOT_TEXTURES:
373 case PIPE_CAP_TWO_SIDED_STENCIL:
374 case PIPE_CAP_DUAL_SOURCE_BLEND:
375 case PIPE_CAP_ANISOTROPIC_FILTER:
376 case PIPE_CAP_POINT_SPRITE:
377 case PIPE_CAP_OCCLUSION_QUERY:
378 case PIPE_CAP_TEXTURE_SHADOW_MAP:
379 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
380 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
381 case PIPE_CAP_TEXTURE_SWIZZLE:
382 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
383 case PIPE_CAP_DEPTH_CLIP_DISABLE:
384 case PIPE_CAP_SHADER_STENCIL_EXPORT:
385 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
386 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
387 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
388 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
389 case PIPE_CAP_SM3:
390 case PIPE_CAP_SEAMLESS_CUBE_MAP:
391 case PIPE_CAP_PRIMITIVE_RESTART:
392 case PIPE_CAP_CONDITIONAL_RENDER:
393 case PIPE_CAP_TEXTURE_BARRIER:
394 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
395 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
396 return 1;
397
398 case PIPE_CAP_GLSL_FEATURE_LEVEL:
399 return debug_get_bool_option("R600_GLSL130", FALSE) ? 130 : 120;
400
401 /* Supported except the original R600. */
402 case PIPE_CAP_INDEP_BLEND_ENABLE:
403 case PIPE_CAP_INDEP_BLEND_FUNC:
404 /* R600 doesn't support per-MRT blends */
405 return family == CHIP_R600 ? 0 : 1;
406
407 /* Supported on Evergreen. */
408 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
409 return family >= CHIP_CEDAR ? 1 : 0;
410
411 /* Unsupported features. */
412 case PIPE_CAP_TGSI_INSTANCEID:
413 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
414 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
415 case PIPE_CAP_SCALED_RESOLVE:
416 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
417 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
418 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
419 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
420 return 0;
421
422 /* Stream output. */
423 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
424 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0;
425 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
426 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0;
427 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
428 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
429 return 16*4;
430
431 /* Texturing. */
432 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
433 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
434 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
435 if (family >= CHIP_CEDAR)
436 return 15;
437 else
438 return 14;
439 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
440 return rscreen->info.drm_minor >= 9 ?
441 (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
442 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
443 return 32;
444
445 /* Render targets. */
446 case PIPE_CAP_MAX_RENDER_TARGETS:
447 /* FIXME some r6xx are buggy and can only do 4 */
448 return 8;
449
450 /* Timer queries, present when the clock frequency is non zero. */
451 case PIPE_CAP_TIMER_QUERY:
452 return rscreen->info.r600_clock_crystal_freq != 0;
453
454 case PIPE_CAP_MIN_TEXEL_OFFSET:
455 return -8;
456
457 case PIPE_CAP_MAX_TEXEL_OFFSET:
458 return 7;
459 }
460 return 0;
461 }
462
463 static float r600_get_paramf(struct pipe_screen* pscreen,
464 enum pipe_capf param)
465 {
466 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
467 enum radeon_family family = rscreen->family;
468
469 switch (param) {
470 case PIPE_CAPF_MAX_LINE_WIDTH:
471 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
472 case PIPE_CAPF_MAX_POINT_WIDTH:
473 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
474 if (family >= CHIP_CEDAR)
475 return 16384.0f;
476 else
477 return 8192.0f;
478 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
479 return 16.0f;
480 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
481 return 16.0f;
482 case PIPE_CAPF_GUARD_BAND_LEFT:
483 case PIPE_CAPF_GUARD_BAND_TOP:
484 case PIPE_CAPF_GUARD_BAND_RIGHT:
485 case PIPE_CAPF_GUARD_BAND_BOTTOM:
486 return 0.0f;
487 }
488 return 0.0f;
489 }
490
491 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
492 {
493 switch(shader)
494 {
495 case PIPE_SHADER_FRAGMENT:
496 case PIPE_SHADER_VERTEX:
497 break;
498 case PIPE_SHADER_GEOMETRY:
499 /* TODO: support and enable geometry programs */
500 return 0;
501 default:
502 /* TODO: support tessellation on Evergreen */
503 return 0;
504 }
505
506 /* TODO: all these should be fixed, since r600 surely supports much more! */
507 switch (param) {
508 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
509 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
510 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
511 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
512 return 16384;
513 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
514 return 8; /* FIXME */
515 case PIPE_SHADER_CAP_MAX_INPUTS:
516 if(shader == PIPE_SHADER_FRAGMENT)
517 return 34;
518 else
519 return 32;
520 case PIPE_SHADER_CAP_MAX_TEMPS:
521 return 256; /* Max native temporaries. */
522 case PIPE_SHADER_CAP_MAX_ADDRS:
523 /* FIXME Isn't this equal to TEMPS? */
524 return 1; /* Max native address registers */
525 case PIPE_SHADER_CAP_MAX_CONSTS:
526 return R600_MAX_CONST_BUFFER_SIZE;
527 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
528 return R600_MAX_CONST_BUFFERS-1;
529 case PIPE_SHADER_CAP_MAX_PREDS:
530 return 0; /* FIXME */
531 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
532 return 1;
533 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
534 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
535 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
536 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
537 return 1;
538 case PIPE_SHADER_CAP_SUBROUTINES:
539 return 0;
540 case PIPE_SHADER_CAP_INTEGERS:
541 return 0;
542 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
543 return 16;
544 }
545 return 0;
546 }
547
548 static int r600_get_video_param(struct pipe_screen *screen,
549 enum pipe_video_profile profile,
550 enum pipe_video_cap param)
551 {
552 switch (param) {
553 case PIPE_VIDEO_CAP_SUPPORTED:
554 return vl_profile_supported(screen, profile);
555 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
556 return 1;
557 case PIPE_VIDEO_CAP_MAX_WIDTH:
558 case PIPE_VIDEO_CAP_MAX_HEIGHT:
559 return vl_video_buffer_max_size(screen);
560 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
561 return PIPE_FORMAT_NV12;
562 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
563 return false;
564 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
565 return false;
566 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
567 return true;
568 default:
569 return 0;
570 }
571 }
572
573 static void r600_destroy_screen(struct pipe_screen* pscreen)
574 {
575 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
576
577 if (rscreen == NULL)
578 return;
579
580 if (rscreen->fences.bo) {
581 struct r600_fence_block *entry, *tmp;
582
583 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
584 LIST_DEL(&entry->head);
585 FREE(entry);
586 }
587
588 rscreen->ws->buffer_unmap(rscreen->fences.bo->buf);
589 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
590 }
591 pipe_mutex_destroy(rscreen->fences.mutex);
592
593 rscreen->ws->destroy(rscreen->ws);
594
595 util_slab_destroy(&rscreen->pool_buffers);
596 pipe_mutex_destroy(rscreen->mutex_num_contexts);
597 FREE(rscreen);
598 }
599
600 static void r600_fence_reference(struct pipe_screen *pscreen,
601 struct pipe_fence_handle **ptr,
602 struct pipe_fence_handle *fence)
603 {
604 struct r600_fence **oldf = (struct r600_fence**)ptr;
605 struct r600_fence *newf = (struct r600_fence*)fence;
606
607 if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
608 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
609 pipe_mutex_lock(rscreen->fences.mutex);
610 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
611 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
612 pipe_mutex_unlock(rscreen->fences.mutex);
613 }
614
615 *ptr = fence;
616 }
617
618 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
619 struct pipe_fence_handle *fence)
620 {
621 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
622 struct r600_fence *rfence = (struct r600_fence*)fence;
623
624 return rscreen->fences.data[rfence->index];
625 }
626
627 static boolean r600_fence_finish(struct pipe_screen *pscreen,
628 struct pipe_fence_handle *fence,
629 uint64_t timeout)
630 {
631 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
632 struct r600_fence *rfence = (struct r600_fence*)fence;
633 int64_t start_time = 0;
634 unsigned spins = 0;
635
636 if (timeout != PIPE_TIMEOUT_INFINITE) {
637 start_time = os_time_get();
638
639 /* Convert to microseconds. */
640 timeout /= 1000;
641 }
642
643 while (rscreen->fences.data[rfence->index] == 0) {
644 /* Special-case infinite timeout - wait for the dummy BO to become idle */
645 if (timeout == PIPE_TIMEOUT_INFINITE) {
646 rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
647 break;
648 }
649
650 /* The dummy BO will be busy until the CS including the fence has completed, or
651 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
652 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
653 break;
654
655 if (++spins % 256)
656 continue;
657 #ifdef PIPE_OS_UNIX
658 sched_yield();
659 #else
660 os_time_sleep(10);
661 #endif
662 if (timeout != PIPE_TIMEOUT_INFINITE &&
663 os_time_get() - start_time >= timeout) {
664 break;
665 }
666 }
667
668 return rscreen->fences.data[rfence->index] != 0;
669 }
670
671 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
672 {
673 switch ((tiling_config & 0xe) >> 1) {
674 case 0:
675 rscreen->tiling_info.num_channels = 1;
676 break;
677 case 1:
678 rscreen->tiling_info.num_channels = 2;
679 break;
680 case 2:
681 rscreen->tiling_info.num_channels = 4;
682 break;
683 case 3:
684 rscreen->tiling_info.num_channels = 8;
685 break;
686 default:
687 return -EINVAL;
688 }
689
690 switch ((tiling_config & 0x30) >> 4) {
691 case 0:
692 rscreen->tiling_info.num_banks = 4;
693 break;
694 case 1:
695 rscreen->tiling_info.num_banks = 8;
696 break;
697 default:
698 return -EINVAL;
699
700 }
701 switch ((tiling_config & 0xc0) >> 6) {
702 case 0:
703 rscreen->tiling_info.group_bytes = 256;
704 break;
705 case 1:
706 rscreen->tiling_info.group_bytes = 512;
707 break;
708 default:
709 return -EINVAL;
710 }
711 return 0;
712 }
713
714 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
715 {
716 switch (tiling_config & 0xf) {
717 case 0:
718 rscreen->tiling_info.num_channels = 1;
719 break;
720 case 1:
721 rscreen->tiling_info.num_channels = 2;
722 break;
723 case 2:
724 rscreen->tiling_info.num_channels = 4;
725 break;
726 case 3:
727 rscreen->tiling_info.num_channels = 8;
728 break;
729 default:
730 return -EINVAL;
731 }
732
733 switch ((tiling_config & 0xf0) >> 4) {
734 case 0:
735 rscreen->tiling_info.num_banks = 4;
736 break;
737 case 1:
738 rscreen->tiling_info.num_banks = 8;
739 break;
740 case 2:
741 rscreen->tiling_info.num_banks = 16;
742 break;
743 default:
744 return -EINVAL;
745 }
746
747 switch ((tiling_config & 0xf00) >> 8) {
748 case 0:
749 rscreen->tiling_info.group_bytes = 256;
750 break;
751 case 1:
752 rscreen->tiling_info.group_bytes = 512;
753 break;
754 default:
755 return -EINVAL;
756 }
757 return 0;
758 }
759
760 static int r600_init_tiling(struct r600_screen *rscreen)
761 {
762 uint32_t tiling_config = rscreen->info.r600_tiling_config;
763
764 /* set default group bytes, overridden by tiling info ioctl */
765 if (rscreen->chip_class <= R700) {
766 rscreen->tiling_info.group_bytes = 256;
767 } else {
768 rscreen->tiling_info.group_bytes = 512;
769 }
770
771 if (!tiling_config)
772 return 0;
773
774 if (rscreen->chip_class <= R700) {
775 return r600_interpret_tiling(rscreen, tiling_config);
776 } else {
777 return evergreen_interpret_tiling(rscreen, tiling_config);
778 }
779 }
780
781 static unsigned radeon_family_from_device(unsigned device)
782 {
783 switch (device) {
784 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
785 #include "pci_ids/r600_pci_ids.h"
786 #undef CHIPSET
787 default:
788 return CHIP_UNKNOWN;
789 }
790 }
791
792 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
793 {
794 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
795 if (rscreen == NULL) {
796 return NULL;
797 }
798
799 rscreen->ws = ws;
800 ws->query_info(ws, &rscreen->info);
801
802 rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
803 if (rscreen->family == CHIP_UNKNOWN) {
804 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
805 FREE(rscreen);
806 return NULL;
807 }
808
809 /* setup class */
810 if (rscreen->family == CHIP_CAYMAN) {
811 rscreen->chip_class = CAYMAN;
812 } else if (rscreen->family >= CHIP_CEDAR) {
813 rscreen->chip_class = EVERGREEN;
814 } else if (rscreen->family >= CHIP_RV770) {
815 rscreen->chip_class = R700;
816 } else {
817 rscreen->chip_class = R600;
818 }
819
820 if (r600_init_tiling(rscreen)) {
821 FREE(rscreen);
822 return NULL;
823 }
824
825 rscreen->screen.destroy = r600_destroy_screen;
826 rscreen->screen.get_name = r600_get_name;
827 rscreen->screen.get_vendor = r600_get_vendor;
828 rscreen->screen.get_param = r600_get_param;
829 rscreen->screen.get_shader_param = r600_get_shader_param;
830 rscreen->screen.get_paramf = r600_get_paramf;
831 rscreen->screen.get_video_param = r600_get_video_param;
832 if (rscreen->chip_class >= EVERGREEN) {
833 rscreen->screen.is_format_supported = evergreen_is_format_supported;
834 } else {
835 rscreen->screen.is_format_supported = r600_is_format_supported;
836 }
837 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
838 rscreen->screen.context_create = r600_create_context;
839 rscreen->screen.fence_reference = r600_fence_reference;
840 rscreen->screen.fence_signalled = r600_fence_signalled;
841 rscreen->screen.fence_finish = r600_fence_finish;
842 r600_init_screen_resource_functions(&rscreen->screen);
843
844 util_format_s3tc_init();
845
846 util_slab_create(&rscreen->pool_buffers,
847 sizeof(struct r600_resource), 64,
848 UTIL_SLAB_SINGLETHREADED);
849
850 pipe_mutex_init(rscreen->mutex_num_contexts);
851
852 rscreen->fences.bo = NULL;
853 rscreen->fences.data = NULL;
854 rscreen->fences.next_index = 0;
855 LIST_INITHEAD(&rscreen->fences.pool);
856 LIST_INITHEAD(&rscreen->fences.blocks);
857 pipe_mutex_init(rscreen->fences.mutex);
858
859 return &rscreen->screen;
860 }