src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_debug.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_simple_shaders.h"
  36 #include "util/u_upload_mgr.h"
  37 #include "util/u_math.h"
  38 #include "vl/vl_decoder.h"
  39 #include "vl/vl_video_buffer.h"
  40 #include "radeon_video.h"
  41 #include "radeon_uvd.h"
  42 #include "util/os_time.h"
  43
  44 static const struct debug_named_value r600_debug_options[] = {
  45         /* features */
  46         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  47
  48         /* shader backend */
  49         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  50         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  51         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  52         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  53         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  54         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  55         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  56         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  57
  58         DEBUG_NAMED_VALUE_END /* must be last */
  59 };
  60
  61 /*
  62  * pipe_context
  63  */
  64
  65 static void r600_destroy_context(struct pipe_context *context)
  66 {
  67         struct r600_context *rctx = (struct r600_context *)context;
  68         unsigned sh;
  69
  70         r600_isa_destroy(rctx->isa);
  71
  72         r600_sb_context_destroy(rctx->sb_context);
  73
  74         r600_resource_reference(&rctx->dummy_cmask, NULL);
  75         r600_resource_reference(&rctx->dummy_fmask, NULL);
  76
  77         if (rctx->append_fence)
  78                 pipe_resource_reference((struct pipe_resource**)&rctx->append_fence, NULL);
  79         for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
  80                 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, NULL);
  81                 free(rctx->driver_consts[sh].constants);
  82         }
  83
  84         if (rctx->fixed_func_tcs_shader)
  85                 rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
  86
  87         if (rctx->dummy_pixel_shader) {
  88                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
  89         }
  90         if (rctx->custom_dsa_flush) {
  91                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
  92         }
  93         if (rctx->custom_blend_resolve) {
  94                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
  95         }
  96         if (rctx->custom_blend_decompress) {
  97                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
  98         }
  99         if (rctx->custom_blend_fastclear) {
 100                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
 101         }
 102         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 103
 104         if (rctx->blitter) {
 105                 util_blitter_destroy(rctx->blitter);
 106         }
 107         if (rctx->allocator_fetch_shader) {
 108                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 109         }
 110
 111         r600_release_command_buffer(&rctx->start_cs_cmd);
 112
 113         FREE(rctx->start_compute_cs_cmd.buf);
 114
 115         r600_common_context_cleanup(&rctx->b);
 116
 117         r600_resource_reference(&rctx->trace_buf, NULL);
 118         r600_resource_reference(&rctx->last_trace_buf, NULL);
 119         radeon_clear_saved_cs(&rctx->last_gfx);
 120
 121         FREE(rctx);
 122 }
 123
 124 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
 125                                                 void *priv, unsigned flags)
 126 {
 127         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 128         struct r600_screen* rscreen = (struct r600_screen *)screen;
 129         struct radeon_winsys *ws = rscreen->b.ws;
 130
 131         if (!rctx)
 132                 return NULL;
 133
 134         rctx->b.b.screen = screen;
 135         assert(!priv);
 136         rctx->b.b.priv = NULL; /* for threaded_context_unwrap_sync */
 137         rctx->b.b.destroy = r600_destroy_context;
 138         rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
 139
 140         if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
 141                 goto fail;
 142
 143         rctx->screen = rscreen;
 144         LIST_INITHEAD(&rctx->texture_buffers);
 145
 146         r600_init_blit_functions(rctx);
 147
 148         if (rscreen->b.info.has_hw_decode) {
 149                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 150                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 151         } else {
 152                 rctx->b.b.create_video_codec = vl_create_decoder;
 153                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 154         }
 155
 156         if (getenv("R600_TRACE"))
 157                 rctx->is_debug = true;
 158         r600_init_common_state_functions(rctx);
 159
 160         switch (rctx->b.chip_class) {
 161         case R600:
 162         case R700:
 163                 r600_init_state_functions(rctx);
 164                 r600_init_atom_start_cs(rctx);
 165                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 166                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 167                                                                       : r600_create_resolve_blend(rctx);
 168                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 169                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 170                                            rctx->b.family == CHIP_RV620 ||
 171                                            rctx->b.family == CHIP_RS780 ||
 172                                            rctx->b.family == CHIP_RS880 ||
 173                                            rctx->b.family == CHIP_RV710);
 174                 break;
 175         case EVERGREEN:
 176         case CAYMAN:
 177                 evergreen_init_state_functions(rctx);
 178                 evergreen_init_atom_start_cs(rctx);
 179                 evergreen_init_atom_start_compute_cs(rctx);
 180                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 181                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 182                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 183                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 184                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 185                                            rctx->b.family == CHIP_PALM ||
 186                                            rctx->b.family == CHIP_SUMO ||
 187                                            rctx->b.family == CHIP_SUMO2 ||
 188                                            rctx->b.family == CHIP_CAICOS ||
 189                                            rctx->b.family == CHIP_CAYMAN ||
 190                                            rctx->b.family == CHIP_ARUBA);
 191
 192                 rctx->append_fence = pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
 193                                                          PIPE_USAGE_DEFAULT, 32);
 194                 break;
 195         default:
 196                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 197                 goto fail;
 198         }
 199
 200         rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
 201                                        r600_context_gfx_flush, rctx);
 202         rctx->b.gfx.flush = r600_context_gfx_flush;
 203
 204         rctx->allocator_fetch_shader =
 205                 u_suballocator_create(&rctx->b.b, 64 * 1024,
 206                                       0, PIPE_USAGE_DEFAULT, 0, FALSE);
 207         if (!rctx->allocator_fetch_shader)
 208                 goto fail;
 209
 210         rctx->isa = calloc(1, sizeof(struct r600_isa));
 211         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 212                 goto fail;
 213
 214         if (rscreen->b.debug_flags & DBG_FORCE_DMA)
 215                 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
 216
 217         rctx->blitter = util_blitter_create(&rctx->b.b);
 218         if (rctx->blitter == NULL)
 219                 goto fail;
 220         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 221         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 222
 223         r600_begin_new_cs(rctx);
 224
 225         rctx->dummy_pixel_shader =
 226                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 227                                                      TGSI_SEMANTIC_GENERIC,
 228                                                      TGSI_INTERPOLATE_CONSTANT);
 229         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 230
 231         return &rctx->b.b;
 232
 233 fail:
 234         r600_destroy_context(&rctx->b.b);
 235         return NULL;
 236 }
 237
 238 /*
 239  * pipe_screen
 240  */
 241
 242 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 243 {
 244         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 245         enum radeon_family family = rscreen->b.family;
 246
 247         switch (param) {
 248         /* Supported features (boolean caps). */
 249         case PIPE_CAP_NPOT_TEXTURES:
 250         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 251         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 252         case PIPE_CAP_TWO_SIDED_STENCIL:
 253         case PIPE_CAP_ANISOTROPIC_FILTER:
 254         case PIPE_CAP_POINT_SPRITE:
 255         case PIPE_CAP_OCCLUSION_QUERY:
 256         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 257         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 258         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 259         case PIPE_CAP_TEXTURE_SWIZZLE:
 260         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 261         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 262         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 263         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 264         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 265         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 266         case PIPE_CAP_SM3:
 267         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 268         case PIPE_CAP_PRIMITIVE_RESTART:
 269         case PIPE_CAP_CONDITIONAL_RENDER:
 270         case PIPE_CAP_TEXTURE_BARRIER:
 271         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 272         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 273         case PIPE_CAP_TGSI_INSTANCEID:
 274         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 275         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 276         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 277         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 278         case PIPE_CAP_START_INSTANCE:
 279         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 280         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 281         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 282         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 283         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 284         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 285         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 286         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 287         case PIPE_CAP_SAMPLE_SHADING:
 288         case PIPE_CAP_CLIP_HALFZ:
 289         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 290         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 291         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 292         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 293         case PIPE_CAP_TGSI_TXQS:
 294         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 295         case PIPE_CAP_INVALIDATE_BUFFER:
 296         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 297         case PIPE_CAP_QUERY_MEMORY_INFO:
 298         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 299         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 300         case PIPE_CAP_CLEAR_TEXTURE:
 301         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 302         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 303         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 304                 return 1;
 305
 306         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 307                 return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
 308
 309         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 310                 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
 311
 312         case PIPE_CAP_COMPUTE:
 313                 return rscreen->b.chip_class > R700;
 314
 315         case PIPE_CAP_TGSI_TEXCOORD:
 316                 return 0;
 317
 318         case PIPE_CAP_FAKE_SW_MSAA:
 319                 return 0;
 320
 321         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 322                 return MIN2(rscreen->b.info.max_alloc_size, INT_MAX);
 323
 324         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 325                 return R600_MAP_BUFFER_ALIGNMENT;
 326
 327         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 328                 return 256;
 329
 330         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 331                 return 1;
 332
 333         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 334                 if (family >= CHIP_CEDAR)
 335                    return 410;
 336                 /* pre-evergreen geom shaders need newer kernel */
 337                 if (rscreen->b.info.drm_minor >= 37)
 338                    return 330;
 339                 return 140;
 340
 341         /* Supported except the original R600. */
 342         case PIPE_CAP_INDEP_BLEND_ENABLE:
 343         case PIPE_CAP_INDEP_BLEND_FUNC:
 344                 /* R600 doesn't support per-MRT blends */
 345                 return family == CHIP_R600 ? 0 : 1;
 346
 347         /* Supported on Evergreen. */
 348         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 349         case PIPE_CAP_CUBE_MAP_ARRAY:
 350         case PIPE_CAP_TEXTURE_GATHER_SM5:
 351         case PIPE_CAP_TEXTURE_QUERY_LOD:
 352         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 353         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 354         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 355                 return family >= CHIP_CEDAR ? 1 : 0;
 356         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 357                 return family >= CHIP_CEDAR ? 4 : 0;
 358         case PIPE_CAP_DRAW_INDIRECT:
 359                 /* kernel command checker support is also required */
 360                 return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
 361
 362         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 363                 return family >= CHIP_CEDAR ? 0 : 1;
 364
 365         /* Unsupported features. */
 366         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 367         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 368         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 369         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 370         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 371         case PIPE_CAP_USER_VERTEX_BUFFERS:
 372         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 373         case PIPE_CAP_VERTEXID_NOBASE:
 374         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 375         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 376         case PIPE_CAP_SHAREABLE_SHADERS:
 377         case PIPE_CAP_DRAW_PARAMETERS:
 378         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 379         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 380         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 381         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 382         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 383         case PIPE_CAP_GENERATE_MIPMAP:
 384         case PIPE_CAP_STRING_MARKER:
 385         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 386         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 387         case PIPE_CAP_CULL_DISTANCE:
 388         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 389         case PIPE_CAP_TGSI_VOTE:
 390         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 391         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 392         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 393         case PIPE_CAP_NATIVE_FENCE_FD:
 394         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 395         case PIPE_CAP_TGSI_FS_FBFETCH:
 396         case PIPE_CAP_INT64:
 397         case PIPE_CAP_INT64_DIVMOD:
 398         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 399         case PIPE_CAP_TGSI_CLOCK:
 400         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 401         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 402         case PIPE_CAP_TGSI_BALLOT:
 403         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 404         case PIPE_CAP_POST_DEPTH_COVERAGE:
 405         case PIPE_CAP_BINDLESS_TEXTURE:
 406         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 407         case PIPE_CAP_QUERY_SO_OVERFLOW:
 408         case PIPE_CAP_MEMOBJ:
 409         case PIPE_CAP_LOAD_CONSTBUF:
 410         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 411         case PIPE_CAP_TILE_RASTER_ORDER:
 412         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 413         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 414                 return 0;
 415
 416         case PIPE_CAP_DOUBLES:
 417                 if (rscreen->b.family == CHIP_ARUBA ||
 418                     rscreen->b.family == CHIP_CAYMAN ||
 419                     rscreen->b.family == CHIP_CYPRESS ||
 420                     rscreen->b.family == CHIP_HEMLOCK)
 421                         return 1;
 422                 return 0;
 423
 424         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 425                 if (family >= CHIP_CEDAR)
 426                         return 30;
 427                 else
 428                         return 0;
 429         /* Stream output. */
 430         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 431                 return rscreen->b.has_streamout ? 4 : 0;
 432         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 433         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 434                 return rscreen->b.has_streamout ? 1 : 0;
 435         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 436         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 437                 return 32*4;
 438
 439         /* Geometry shader output. */
 440         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 441                 return 1024;
 442         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 443                 return 16384;
 444         case PIPE_CAP_MAX_VERTEX_STREAMS:
 445                 return family >= CHIP_CEDAR ? 4 : 1;
 446
 447         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 448                 return 2047;
 449
 450         /* Texturing. */
 451         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 452         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 453                 if (family >= CHIP_CEDAR)
 454                         return 15;
 455                 else
 456                         return 14;
 457         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 458                 /* textures support 8192, but layered rendering supports 2048 */
 459                 return 12;
 460         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 461                 /* textures support 8192, but layered rendering supports 2048 */
 462                 return 2048;
 463
 464         /* Render targets. */
 465         case PIPE_CAP_MAX_RENDER_TARGETS:
 466                 /* XXX some r6xx are buggy and can only do 4 */
 467                 return 8;
 468
 469         case PIPE_CAP_MAX_VIEWPORTS:
 470                 return R600_MAX_VIEWPORTS;
 471         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 472                 return 8;
 473
 474         /* Timer queries, present when the clock frequency is non zero. */
 475         case PIPE_CAP_QUERY_TIME_ELAPSED:
 476                 return rscreen->b.info.clock_crystal_freq != 0;
 477         case PIPE_CAP_QUERY_TIMESTAMP:
 478                 return rscreen->b.info.drm_minor >= 20 &&
 479                        rscreen->b.info.clock_crystal_freq != 0;
 480
 481         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 482         case PIPE_CAP_MIN_TEXEL_OFFSET:
 483                 return -8;
 484
 485         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 486         case PIPE_CAP_MAX_TEXEL_OFFSET:
 487                 return 7;
 488
 489         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 490                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 491         case PIPE_CAP_ENDIANNESS:
 492                 return PIPE_ENDIAN_LITTLE;
 493
 494         case PIPE_CAP_VENDOR_ID:
 495                 return ATI_VENDOR_ID;
 496         case PIPE_CAP_DEVICE_ID:
 497                 return rscreen->b.info.pci_id;
 498         case PIPE_CAP_ACCELERATED:
 499                 return 1;
 500         case PIPE_CAP_VIDEO_MEMORY:
 501                 return rscreen->b.info.vram_size >> 20;
 502         case PIPE_CAP_UMA:
 503                 return 0;
 504         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 505                 return rscreen->b.chip_class >= R700;
 506         case PIPE_CAP_PCI_GROUP:
 507                 return rscreen->b.info.pci_domain;
 508         case PIPE_CAP_PCI_BUS:
 509                 return rscreen->b.info.pci_bus;
 510         case PIPE_CAP_PCI_DEVICE:
 511                 return rscreen->b.info.pci_dev;
 512         case PIPE_CAP_PCI_FUNCTION:
 513                 return rscreen->b.info.pci_func;
 514         }
 515         return 0;
 516 }
 517
 518 static int r600_get_shader_param(struct pipe_screen* pscreen,
 519                                  enum pipe_shader_type shader,
 520                                  enum pipe_shader_cap param)
 521 {
 522         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 523
 524         switch(shader)
 525         {
 526         case PIPE_SHADER_FRAGMENT:
 527         case PIPE_SHADER_VERTEX:
 528         case PIPE_SHADER_COMPUTE:
 529                 break;
 530         case PIPE_SHADER_GEOMETRY:
 531                 if (rscreen->b.family >= CHIP_CEDAR)
 532                         break;
 533                 /* pre-evergreen geom shaders need newer kernel */
 534                 if (rscreen->b.info.drm_minor >= 37)
 535                         break;
 536                 return 0;
 537         case PIPE_SHADER_TESS_CTRL:
 538         case PIPE_SHADER_TESS_EVAL:
 539                 if (rscreen->b.family >= CHIP_CEDAR)
 540                         break;
 541         default:
 542                 return 0;
 543         }
 544
 545         switch (param) {
 546         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 547         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 548         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 549         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 550                 return 16384;
 551         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 552                 return 32;
 553         case PIPE_SHADER_CAP_MAX_INPUTS:
 554                 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
 555         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 556                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 557         case PIPE_SHADER_CAP_MAX_TEMPS:
 558                 return 256; /* Max native temporaries. */
 559         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 560                 if (shader == PIPE_SHADER_COMPUTE) {
 561                         uint64_t max_const_buffer_size;
 562                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 563                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 564                                 &max_const_buffer_size);
 565                         return MIN2(max_const_buffer_size, INT_MAX);
 566
 567                 } else {
 568                         return R600_MAX_CONST_BUFFER_SIZE;
 569                 }
 570         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 571                 return R600_MAX_USER_CONST_BUFFERS;
 572         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 573                 return 1;
 574         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 575                 return 1;
 576         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 577         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 578         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 579         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 580                 return 1;
 581         case PIPE_SHADER_CAP_SUBROUTINES:
 582         case PIPE_SHADER_CAP_INT64_ATOMICS:
 583         case PIPE_SHADER_CAP_FP16:
 584                 return 0;
 585         case PIPE_SHADER_CAP_INTEGERS:
 586         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 587                 return 1;
 588         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 589         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 590                 return 16;
 591         case PIPE_SHADER_CAP_PREFERRED_IR:
 592                 if (shader == PIPE_SHADER_COMPUTE) {
 593                         return PIPE_SHADER_IR_NATIVE;
 594                 } else {
 595                         return PIPE_SHADER_IR_TGSI;
 596                 }
 597         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 598                 return 0;
 599         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 600                 if (rscreen->b.family == CHIP_ARUBA ||
 601                     rscreen->b.family == CHIP_CAYMAN ||
 602                     rscreen->b.family == CHIP_CYPRESS ||
 603                     rscreen->b.family == CHIP_HEMLOCK)
 604                         return 1;
 605                 return 0;
 606         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 607         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 608         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 609         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 610         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 611         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 612         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 613                 return 0;
 614         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 615                 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
 616                         return 8;
 617                 return 0;
 618         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 619                 /* having to allocate the atomics out amongst shaders stages is messy,
 620                    so give compute 8 buffers and all the others one */
 621                 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) {
 622                         return EG_MAX_ATOMIC_BUFFERS;
 623                 }
 624                 return 0;
 625         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 626                 /* due to a bug in the shader compiler, some loops hang
 627                  * if they are not unrolled, see:
 628                  *    https://bugs.freedesktop.org/show_bug.cgi?id=86720
 629                  */
 630                 return 255;
 631         }
 632         return 0;
 633 }
 634
 635 static void r600_destroy_screen(struct pipe_screen* pscreen)
 636 {
 637         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 638
 639         if (!rscreen)
 640                 return;
 641
 642         if (!rscreen->b.ws->unref(rscreen->b.ws))
 643                 return;
 644
 645         if (rscreen->global_pool) {
 646                 compute_memory_pool_delete(rscreen->global_pool);
 647         }
 648
 649         r600_destroy_common_screen(&rscreen->b);
 650 }
 651
 652 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 653                                                   const struct pipe_resource *templ)
 654 {
 655         if (templ->target == PIPE_BUFFER &&
 656             (templ->bind & PIPE_BIND_GLOBAL))
 657                 return r600_compute_global_buffer_create(screen, templ);
 658
 659         return r600_resource_create_common(screen, templ);
 660 }
 661
 662 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws,
 663                                        const struct pipe_screen_config *config)
 664 {
 665         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 666
 667         if (!rscreen) {
 668                 return NULL;
 669         }
 670
 671         /* Set functions first. */
 672         rscreen->b.b.context_create = r600_create_context;
 673         rscreen->b.b.destroy = r600_destroy_screen;
 674         rscreen->b.b.get_param = r600_get_param;
 675         rscreen->b.b.get_shader_param = r600_get_shader_param;
 676         rscreen->b.b.resource_create = r600_resource_create;
 677
 678         if (!r600_common_screen_init(&rscreen->b, ws)) {
 679                 FREE(rscreen);
 680                 return NULL;
 681         }
 682
 683         if (rscreen->b.info.chip_class >= EVERGREEN) {
 684                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 685         } else {
 686                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 687         }
 688
 689         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 690         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 691                 rscreen->b.debug_flags |= DBG_COMPUTE;
 692         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 693                 rscreen->b.debug_flags |= DBG_ALL_SHADERS | DBG_FS;
 694         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
 695                 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
 696
 697         if (rscreen->b.family == CHIP_UNKNOWN) {
 698                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 699                 FREE(rscreen);
 700                 return NULL;
 701         }
 702
 703         /* Figure out streamout kernel support. */
 704         switch (rscreen->b.chip_class) {
 705         case R600:
 706                 if (rscreen->b.family < CHIP_RS780) {
 707                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 708                 } else {
 709                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 710                 }
 711                 break;
 712         case R700:
 713                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 714                 break;
 715         case EVERGREEN:
 716         case CAYMAN:
 717                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 718                 break;
 719         default:
 720                 rscreen->b.has_streamout = FALSE;
 721                 break;
 722         }
 723
 724         /* MSAA support. */
 725         switch (rscreen->b.chip_class) {
 726         case R600:
 727         case R700:
 728                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 729                 rscreen->has_compressed_msaa_texturing = false;
 730                 break;
 731         case EVERGREEN:
 732                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 733                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 734                 break;
 735         case CAYMAN:
 736                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 737                 rscreen->has_compressed_msaa_texturing = true;
 738                 break;
 739         default:
 740                 rscreen->has_msaa = FALSE;
 741                 rscreen->has_compressed_msaa_texturing = false;
 742         }
 743
 744         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 745                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 746
 747         rscreen->b.barrier_flags.cp_to_L2 =
 748                 R600_CONTEXT_INV_VERTEX_CACHE |
 749                 R600_CONTEXT_INV_TEX_CACHE |
 750                 R600_CONTEXT_INV_CONST_CACHE;
 751         rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_PS_PARTIAL_FLUSH;
 752
 753         rscreen->global_pool = compute_memory_pool_new(rscreen);
 754
 755         /* Create the auxiliary context. This must be done last. */
 756         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
 757
 758         rscreen->has_atomics = rscreen->b.info.drm_minor >= 44;
 759 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 760         struct pipe_resource templ = {};
 761
 762         templ.width0 = 4;
 763         templ.height0 = 2048;
 764         templ.depth0 = 1;
 765         templ.array_size = 1;
 766         templ.target = PIPE_TEXTURE_2D;
 767         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 768         templ.usage = PIPE_USAGE_DEFAULT;
 769
 770         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 771         unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_TRANSFER_WRITE);
 772
 773         memset(map, 0, 256);
 774
 775         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 776         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 777         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 778         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 779         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 780
 781         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 782
 783         int i;
 784         for (i = 0; i < 256; i++) {
 785                 printf("%02X", map[i]);
 786                 if (i % 16 == 15)
 787                         printf("\n");
 788         }
 789 #endif
 790
 791         if (rscreen->b.debug_flags & DBG_TEST_DMA)
 792                 r600_test_dma(&rscreen->b);
 793
 794         r600_query_fix_enabled_rb_mask(&rscreen->b);
 795         return &rscreen->b.b;
 796 }