src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_blitter.h"
  34 #include "util/u_debug.h"
  35 #include "util/u_memory.h"
  36 #include "util/u_simple_shaders.h"
  37 #include "util/u_upload_mgr.h"
  38 #include "util/u_math.h"
  39 #include "vl/vl_decoder.h"
  40 #include "vl/vl_video_buffer.h"
  41 #include "radeon/radeon_video.h"
  42 #include "radeon/radeon_uvd.h"
  43 #include "os/os_time.h"
  44
  45 static const struct debug_named_value r600_debug_options[] = {
  46         /* features */
  47 #if defined(R600_USE_LLVM)
  48         { "nollvm", DBG_NO_LLVM, "Disable the LLVM shader compiler" },
  49 #endif
  50         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  51
  52         /* shader backend */
  53         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  54         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  55         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  56         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  57         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  58         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  59         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  60         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  61
  62         DEBUG_NAMED_VALUE_END /* must be last */
  63 };
  64
  65 /*
  66  * pipe_context
  67  */
  68
  69 static void r600_flush(struct pipe_context *ctx, unsigned flags)
  70 {
  71         struct r600_context *rctx = (struct r600_context *)ctx;
  72         struct pipe_query *render_cond = NULL;
  73         unsigned render_cond_mode = 0;
  74         boolean render_cond_cond = FALSE;
  75
  76         if (rctx->b.rings.gfx.cs->cdw == rctx->b.initial_gfx_cs_size)
  77                 return;
  78
  79         rctx->b.rings.gfx.flushing = true;
  80         /* Disable render condition. */
  81         if (rctx->b.current_render_cond) {
  82                 render_cond = rctx->b.current_render_cond;
  83                 render_cond_cond = rctx->b.current_render_cond_cond;
  84                 render_cond_mode = rctx->b.current_render_cond_mode;
  85                 ctx->render_condition(ctx, NULL, FALSE, 0);
  86         }
  87
  88         r600_context_flush(rctx, flags);
  89         rctx->b.rings.gfx.flushing = false;
  90         r600_begin_new_cs(rctx);
  91
  92         /* Re-enable render condition. */
  93         if (render_cond) {
  94                 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
  95         }
  96
  97         rctx->b.initial_gfx_cs_size = rctx->b.rings.gfx.cs->cdw;
  98 }
  99
 100 static void r600_flush_from_st(struct pipe_context *ctx,
 101                                struct pipe_fence_handle **fence,
 102                                unsigned flags)
 103 {
 104         struct r600_context *rctx = (struct r600_context *)ctx;
 105         unsigned fflags;
 106
 107         fflags = flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0;
 108         if (fence) {
 109                 *fence = rctx->b.ws->cs_create_fence(rctx->b.rings.gfx.cs);
 110         }
 111         /* flush gfx & dma ring, order does not matter as only one can be live */
 112         if (rctx->b.rings.dma.cs) {
 113                 rctx->b.rings.dma.flush(rctx, fflags);
 114         }
 115         rctx->b.rings.gfx.flush(rctx, fflags);
 116 }
 117
 118 static void r600_flush_gfx_ring(void *ctx, unsigned flags)
 119 {
 120         r600_flush((struct pipe_context*)ctx, flags);
 121 }
 122
 123 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 124 {
 125         struct r600_context *rctx = (struct r600_context *)ctx;
 126
 127         rctx->b.rings.gfx.flush(rctx, flags);
 128 }
 129
 130 static void r600_destroy_context(struct pipe_context *context)
 131 {
 132         struct r600_context *rctx = (struct r600_context *)context;
 133
 134         r600_isa_destroy(rctx->isa);
 135
 136         r600_sb_context_destroy(rctx->sb_context);
 137
 138         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
 139         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
 140
 141         if (rctx->dummy_pixel_shader) {
 142                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 143         }
 144         if (rctx->custom_dsa_flush) {
 145                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
 146         }
 147         if (rctx->custom_blend_resolve) {
 148                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
 149         }
 150         if (rctx->custom_blend_decompress) {
 151                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
 152         }
 153         if (rctx->custom_blend_fastclear) {
 154                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
 155         }
 156         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 157
 158         if (rctx->blitter) {
 159                 util_blitter_destroy(rctx->blitter);
 160         }
 161         if (rctx->allocator_fetch_shader) {
 162                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 163         }
 164
 165         r600_release_command_buffer(&rctx->start_cs_cmd);
 166
 167         FREE(rctx->start_compute_cs_cmd.buf);
 168
 169         r600_common_context_cleanup(&rctx->b);
 170         FREE(rctx);
 171 }
 172
 173 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 174 {
 175         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 176         struct r600_screen* rscreen = (struct r600_screen *)screen;
 177
 178         if (rctx == NULL)
 179                 return NULL;
 180
 181         rctx->b.b.screen = screen;
 182         rctx->b.b.priv = priv;
 183         rctx->b.b.destroy = r600_destroy_context;
 184         rctx->b.b.flush = r600_flush_from_st;
 185
 186         if (!r600_common_context_init(&rctx->b, &rscreen->b))
 187                 goto fail;
 188
 189         rctx->screen = rscreen;
 190         rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
 191
 192         r600_init_blit_functions(rctx);
 193
 194         if (rscreen->b.info.has_uvd) {
 195                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 196                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 197         } else {
 198                 rctx->b.b.create_video_codec = vl_create_decoder;
 199                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 200         }
 201
 202         r600_init_common_state_functions(rctx);
 203
 204         switch (rctx->b.chip_class) {
 205         case R600:
 206         case R700:
 207                 r600_init_state_functions(rctx);
 208                 r600_init_atom_start_cs(rctx);
 209                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 210                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 211                                                                       : r600_create_resolve_blend(rctx);
 212                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 213                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 214                                            rctx->b.family == CHIP_RV620 ||
 215                                            rctx->b.family == CHIP_RS780 ||
 216                                            rctx->b.family == CHIP_RS880 ||
 217                                            rctx->b.family == CHIP_RV710);
 218                 break;
 219         case EVERGREEN:
 220         case CAYMAN:
 221                 evergreen_init_state_functions(rctx);
 222                 evergreen_init_atom_start_cs(rctx);
 223                 evergreen_init_atom_start_compute_cs(rctx);
 224                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 225                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 226                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 227                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 228                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 229                                            rctx->b.family == CHIP_PALM ||
 230                                            rctx->b.family == CHIP_SUMO ||
 231                                            rctx->b.family == CHIP_SUMO2 ||
 232                                            rctx->b.family == CHIP_CAICOS ||
 233                                            rctx->b.family == CHIP_CAYMAN ||
 234                                            rctx->b.family == CHIP_ARUBA);
 235                 break;
 236         default:
 237                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 238                 goto fail;
 239         }
 240
 241         if (rscreen->b.trace_bo) {
 242                 rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, rscreen->b.trace_bo->cs_buf);
 243         } else {
 244                 rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, NULL);
 245         }
 246         rctx->b.rings.gfx.flush = r600_flush_gfx_ring;
 247         rctx->b.ws->cs_set_flush_callback(rctx->b.rings.gfx.cs, r600_flush_from_winsys, rctx);
 248         rctx->b.rings.gfx.flushing = false;
 249
 250         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
 251                                                              0, PIPE_USAGE_DEFAULT, FALSE);
 252         if (!rctx->allocator_fetch_shader)
 253                 goto fail;
 254
 255         rctx->isa = calloc(1, sizeof(struct r600_isa));
 256         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 257                 goto fail;
 258
 259         rctx->blitter = util_blitter_create(&rctx->b.b);
 260         if (rctx->blitter == NULL)
 261                 goto fail;
 262         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 263         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 264
 265         r600_begin_new_cs(rctx);
 266         r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
 267
 268         rctx->dummy_pixel_shader =
 269                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 270                                                      TGSI_SEMANTIC_GENERIC,
 271                                                      TGSI_INTERPOLATE_CONSTANT);
 272         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 273
 274         return &rctx->b.b;
 275
 276 fail:
 277         r600_destroy_context(&rctx->b.b);
 278         return NULL;
 279 }
 280
 281 /*
 282  * pipe_screen
 283  */
 284
 285 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 286 {
 287         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 288         enum radeon_family family = rscreen->b.family;
 289
 290         switch (param) {
 291         /* Supported features (boolean caps). */
 292         case PIPE_CAP_NPOT_TEXTURES:
 293         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 294         case PIPE_CAP_TWO_SIDED_STENCIL:
 295         case PIPE_CAP_ANISOTROPIC_FILTER:
 296         case PIPE_CAP_POINT_SPRITE:
 297         case PIPE_CAP_OCCLUSION_QUERY:
 298         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 299         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 300         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 301         case PIPE_CAP_TEXTURE_SWIZZLE:
 302         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 303         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 304         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 305         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 306         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 307         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 308         case PIPE_CAP_SM3:
 309         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 310         case PIPE_CAP_PRIMITIVE_RESTART:
 311         case PIPE_CAP_CONDITIONAL_RENDER:
 312         case PIPE_CAP_TEXTURE_BARRIER:
 313         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 314         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 315         case PIPE_CAP_TGSI_INSTANCEID:
 316         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 317         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 318         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 319         case PIPE_CAP_USER_INDEX_BUFFERS:
 320         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 321         case PIPE_CAP_START_INSTANCE:
 322         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 323         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 324         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 325         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 326         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 327         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 328                 return 1;
 329
 330         case PIPE_CAP_COMPUTE:
 331                 return rscreen->b.chip_class > R700;
 332
 333         case PIPE_CAP_TGSI_TEXCOORD:
 334                 return 0;
 335
 336         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 337                 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
 338
 339         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 340                 return R600_MAP_BUFFER_ALIGNMENT;
 341
 342         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 343                 return 256;
 344
 345         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 346                 return 1;
 347
 348         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 349                 if (family >= CHIP_CEDAR)
 350                    return 330;
 351                 /* pre-evergreen geom shaders need newer kernel */
 352                 if (rscreen->b.info.drm_minor >= 37)
 353                    return 330;
 354                 return 140;
 355
 356         /* Supported except the original R600. */
 357         case PIPE_CAP_INDEP_BLEND_ENABLE:
 358         case PIPE_CAP_INDEP_BLEND_FUNC:
 359                 /* R600 doesn't support per-MRT blends */
 360                 return family == CHIP_R600 ? 0 : 1;
 361
 362         /* Supported on Evergreen. */
 363         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 364         case PIPE_CAP_CUBE_MAP_ARRAY:
 365         case PIPE_CAP_TGSI_VS_LAYER:
 366                 return family >= CHIP_CEDAR ? 1 : 0;
 367
 368         /* Unsupported features. */
 369         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 370         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 371         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 372         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 373         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 374         case PIPE_CAP_USER_VERTEX_BUFFERS:
 375         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 376         case PIPE_CAP_TEXTURE_GATHER_SM5:
 377                 return 0;
 378
 379         /* Stream output. */
 380         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 381                 return rscreen->b.has_streamout ? 4 : 0;
 382         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 383                 return rscreen->b.has_streamout ? 1 : 0;
 384         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 385         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 386                 return 32*4;
 387
 388         /* Geometry shader output. */
 389         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 390                 return 1024;
 391         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 392                 return 16384;
 393
 394         /* Texturing. */
 395         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 396         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 397                 if (family >= CHIP_CEDAR)
 398                         return 15;
 399                 else
 400                         return 14;
 401         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 402                 /* textures support 8192, but layered rendering supports 2048 */
 403                 return 12;
 404         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 405                 /* textures support 8192, but layered rendering supports 2048 */
 406                 return rscreen->b.info.drm_minor >= 9 ? 2048 : 0;
 407
 408         /* Render targets. */
 409         case PIPE_CAP_MAX_RENDER_TARGETS:
 410                 /* XXX some r6xx are buggy and can only do 4 */
 411                 return 8;
 412
 413         case PIPE_CAP_MAX_VIEWPORTS:
 414                 return 16;
 415
 416         /* Timer queries, present when the clock frequency is non zero. */
 417         case PIPE_CAP_QUERY_TIME_ELAPSED:
 418                 return rscreen->b.info.r600_clock_crystal_freq != 0;
 419         case PIPE_CAP_QUERY_TIMESTAMP:
 420                 return rscreen->b.info.drm_minor >= 20 &&
 421                        rscreen->b.info.r600_clock_crystal_freq != 0;
 422
 423         case PIPE_CAP_MIN_TEXEL_OFFSET:
 424                 return -8;
 425
 426         case PIPE_CAP_MAX_TEXEL_OFFSET:
 427                 return 7;
 428
 429         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 430                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 431         case PIPE_CAP_ENDIANNESS:
 432                 return PIPE_ENDIAN_LITTLE;
 433         }
 434         return 0;
 435 }
 436
 437 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 438 {
 439         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 440
 441         switch(shader)
 442         {
 443         case PIPE_SHADER_FRAGMENT:
 444         case PIPE_SHADER_VERTEX:
 445         case PIPE_SHADER_COMPUTE:
 446                 break;
 447         case PIPE_SHADER_GEOMETRY:
 448                 if (rscreen->b.family >= CHIP_CEDAR)
 449                         break;
 450                 /* pre-evergreen geom shaders need newer kernel */
 451                 if (rscreen->b.info.drm_minor >= 37)
 452                         break;
 453                 return 0;
 454         default:
 455                 /* XXX: support tessellation on Evergreen */
 456                 return 0;
 457         }
 458
 459         switch (param) {
 460         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 461         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 462         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 463         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 464                 return 16384;
 465         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 466                 return 32;
 467         case PIPE_SHADER_CAP_MAX_INPUTS:
 468                 return 32;
 469         case PIPE_SHADER_CAP_MAX_TEMPS:
 470                 return 256; /* Max native temporaries. */
 471         case PIPE_SHADER_CAP_MAX_ADDRS:
 472                 /* XXX Isn't this equal to TEMPS? */
 473                 return 1; /* Max native address registers */
 474         case PIPE_SHADER_CAP_MAX_CONSTS:
 475                 return R600_MAX_CONST_BUFFER_SIZE;
 476         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 477                 return R600_MAX_USER_CONST_BUFFERS;
 478         case PIPE_SHADER_CAP_MAX_PREDS:
 479                 return 0; /* nothing uses this */
 480         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 481                 return 1;
 482         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 483                 return 0;
 484         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 485         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 486         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 487         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 488                 return 1;
 489         case PIPE_SHADER_CAP_SUBROUTINES:
 490                 return 0;
 491         case PIPE_SHADER_CAP_INTEGERS:
 492                 return 1;
 493         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 494         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 495                 return 16;
 496         case PIPE_SHADER_CAP_PREFERRED_IR:
 497                 if (shader == PIPE_SHADER_COMPUTE) {
 498                         return PIPE_SHADER_IR_LLVM;
 499                 } else {
 500                         return PIPE_SHADER_IR_TGSI;
 501                 }
 502         }
 503         return 0;
 504 }
 505
 506 static void r600_destroy_screen(struct pipe_screen* pscreen)
 507 {
 508         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 509
 510         if (rscreen == NULL)
 511                 return;
 512
 513         if (!radeon_winsys_unref(rscreen->b.ws))
 514                 return;
 515
 516         if (rscreen->global_pool) {
 517                 compute_memory_pool_delete(rscreen->global_pool);
 518         }
 519
 520         r600_destroy_common_screen(&rscreen->b);
 521 }
 522
 523 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 524                                                   const struct pipe_resource *templ)
 525 {
 526         if (templ->target == PIPE_BUFFER &&
 527             (templ->bind & PIPE_BIND_GLOBAL))
 528                 return r600_compute_global_buffer_create(screen, templ);
 529
 530         return r600_resource_create_common(screen, templ);
 531 }
 532
 533 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 534 {
 535         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 536
 537         if (rscreen == NULL) {
 538                 return NULL;
 539         }
 540
 541         /* Set functions first. */
 542         rscreen->b.b.context_create = r600_create_context;
 543         rscreen->b.b.destroy = r600_destroy_screen;
 544         rscreen->b.b.get_param = r600_get_param;
 545         rscreen->b.b.get_shader_param = r600_get_shader_param;
 546         rscreen->b.b.resource_create = r600_resource_create;
 547
 548         if (!r600_common_screen_init(&rscreen->b, ws)) {
 549                 FREE(rscreen);
 550                 return NULL;
 551         }
 552
 553         if (rscreen->b.info.chip_class >= EVERGREEN) {
 554                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 555         } else {
 556                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 557         }
 558
 559         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 560         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 561                 rscreen->b.debug_flags |= DBG_COMPUTE;
 562         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 563                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 564         if (debug_get_bool_option("R600_HYPERZ", FALSE))
 565                 rscreen->b.debug_flags |= DBG_HYPERZ;
 566         if (!debug_get_bool_option("R600_LLVM", TRUE))
 567                 rscreen->b.debug_flags |= DBG_NO_LLVM;
 568
 569         if (rscreen->b.family == CHIP_UNKNOWN) {
 570                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 571                 FREE(rscreen);
 572                 return NULL;
 573         }
 574
 575         /* Figure out streamout kernel support. */
 576         switch (rscreen->b.chip_class) {
 577         case R600:
 578                 if (rscreen->b.family < CHIP_RS780) {
 579                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 580                 } else {
 581                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 582                 }
 583                 break;
 584         case R700:
 585                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 586                 break;
 587         case EVERGREEN:
 588         case CAYMAN:
 589                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 590                 break;
 591         default:
 592                 rscreen->b.has_streamout = FALSE;
 593                 break;
 594         }
 595
 596         /* MSAA support. */
 597         switch (rscreen->b.chip_class) {
 598         case R600:
 599         case R700:
 600                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 601                 rscreen->has_compressed_msaa_texturing = false;
 602                 break;
 603         case EVERGREEN:
 604                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 605                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 606                 break;
 607         case CAYMAN:
 608                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 609                 rscreen->has_compressed_msaa_texturing = true;
 610                 break;
 611         default:
 612                 rscreen->has_msaa = FALSE;
 613                 rscreen->has_compressed_msaa_texturing = false;
 614         }
 615
 616         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 617                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 618
 619         rscreen->global_pool = compute_memory_pool_new(rscreen);
 620
 621         /* Create the auxiliary context. This must be done last. */
 622         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
 623
 624 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 625         struct pipe_resource templ = {};
 626
 627         templ.width0 = 4;
 628         templ.height0 = 2048;
 629         templ.depth0 = 1;
 630         templ.array_size = 1;
 631         templ.target = PIPE_TEXTURE_2D;
 632         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 633         templ.usage = PIPE_USAGE_DEFAULT;
 634
 635         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 636         unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
 637
 638         memset(map, 0, 256);
 639
 640         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 641         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 642         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 643         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 644         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 645
 646         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 647
 648         int i;
 649         for (i = 0; i < 256; i++) {
 650                 printf("%02X", map[i]);
 651                 if (i % 16 == 15)
 652                         printf("\n");
 653         }
 654 #endif
 655
 656         return &rscreen->b.b;
 657 }