src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include <errno.h>
  30 #include "pipe/p_shader_tokens.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_debug.h"
  33 #include "util/u_format_s3tc.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_simple_shaders.h"
  36 #include "util/u_upload_mgr.h"
  37 #include "util/u_math.h"
  38 #include "vl/vl_decoder.h"
  39 #include "vl/vl_video_buffer.h"
  40 #include "os/os_time.h"
  41
  42 static const struct debug_named_value debug_options[] = {
  43         /* logging */
  44         { "texdepth", DBG_TEX_DEPTH, "Print texture depth info" },
  45         { "compute", DBG_COMPUTE, "Print compute info" },
  46
  47         /* shaders */
  48         { "fs", DBG_FS, "Print fetch shaders" },
  49         { "vs", DBG_VS, "Print vertex shaders" },
  50         { "gs", DBG_GS, "Print geometry shaders" },
  51         { "ps", DBG_PS, "Print pixel shaders" },
  52         { "cs", DBG_CS, "Print compute shaders" },
  53
  54         /* features */
  55         { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
  56 #if defined(R600_USE_LLVM)
  57         { "nollvm", DBG_NO_LLVM, "Disable the LLVM shader compiler" },
  58 #endif
  59         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  60         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
  61         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
  62         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
  63
  64         DEBUG_NAMED_VALUE_END /* must be last */
  65 };
  66
  67 /*
  68  * pipe_context
  69  */
  70 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  71 {
  72         struct r600_screen *rscreen = rctx->screen;
  73         struct r600_fence *fence = NULL;
  74
  75         pipe_mutex_lock(rscreen->fences.mutex);
  76
  77         if (!rscreen->fences.bo) {
  78                 /* Create the shared buffer object */
  79                 rscreen->fences.bo = (struct r600_resource*)
  80                         pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
  81                                            PIPE_USAGE_STAGING, 4096);
  82                 if (!rscreen->fences.bo) {
  83                         R600_ERR("r600: failed to create bo for fence objects\n");
  84                         goto out;
  85                 }
  86                 rscreen->fences.data = r600_buffer_mmap_sync_with_rings(rctx, rscreen->fences.bo, PIPE_TRANSFER_READ_WRITE);
  87         }
  88
  89         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  90                 struct r600_fence *entry;
  91
  92                 /* Try to find a freed fence that has been signalled */
  93                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  94                         if (rscreen->fences.data[entry->index] != 0) {
  95                                 LIST_DELINIT(&entry->head);
  96                                 fence = entry;
  97                                 break;
  98                         }
  99                 }
 100         }
 101
 102         if (!fence) {
 103                 /* Allocate a new fence */
 104                 struct r600_fence_block *block;
 105                 unsigned index;
 106
 107                 if ((rscreen->fences.next_index + 1) >= 1024) {
 108                         R600_ERR("r600: too many concurrent fences\n");
 109                         goto out;
 110                 }
 111
 112                 index = rscreen->fences.next_index++;
 113
 114                 if (!(index % FENCE_BLOCK_SIZE)) {
 115                         /* Allocate a new block */
 116                         block = CALLOC_STRUCT(r600_fence_block);
 117                         if (block == NULL)
 118                                 goto out;
 119
 120                         LIST_ADD(&block->head, &rscreen->fences.blocks);
 121                 } else {
 122                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
 123                 }
 124
 125                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 126                 fence->index = index;
 127         }
 128
 129         pipe_reference_init(&fence->reference, 1);
 130
 131         rscreen->fences.data[fence->index] = 0;
 132         r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 133
 134         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 135         fence->sleep_bo = (struct r600_resource*)
 136                         pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
 137                                            PIPE_USAGE_STAGING, 1);
 138         /* Add the fence as a dummy relocation. */
 139         r600_context_bo_reloc(rctx, &rctx->rings.gfx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 140
 141 out:
 142         pipe_mutex_unlock(rscreen->fences.mutex);
 143         return fence;
 144 }
 145
 146 static void r600_flush(struct pipe_context *ctx, unsigned flags)
 147 {
 148         struct r600_context *rctx = (struct r600_context *)ctx;
 149         struct pipe_query *render_cond = NULL;
 150         unsigned render_cond_mode = 0;
 151
 152         rctx->rings.gfx.flushing = true;
 153         /* Disable render condition. */
 154         if (rctx->current_render_cond) {
 155                 render_cond = rctx->current_render_cond;
 156                 render_cond_mode = rctx->current_render_cond_mode;
 157                 ctx->render_condition(ctx, NULL, 0);
 158         }
 159
 160         r600_context_flush(rctx, flags);
 161         rctx->rings.gfx.flushing = false;
 162         r600_begin_new_cs(rctx);
 163
 164         /* Re-enable render condition. */
 165         if (render_cond) {
 166                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 167         }
 168 }
 169
 170 static void r600_flush_from_st(struct pipe_context *ctx,
 171                                struct pipe_fence_handle **fence,
 172                                enum pipe_flush_flags flags)
 173 {
 174         struct r600_context *rctx = (struct r600_context *)ctx;
 175         struct r600_fence **rfence = (struct r600_fence**)fence;
 176         unsigned fflags;
 177
 178         fflags = flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0;
 179         if (rfence) {
 180                 *rfence = r600_create_fence(rctx);
 181         }
 182         /* flush gfx & dma ring, order does not matter as only one can be live */
 183         if (rctx->rings.dma.cs) {
 184                 rctx->rings.dma.flush(rctx, fflags);
 185         }
 186         rctx->rings.gfx.flush(rctx, fflags);
 187 }
 188
 189 static void r600_flush_gfx_ring(void *ctx, unsigned flags)
 190 {
 191         r600_flush((struct pipe_context*)ctx, flags);
 192 }
 193
 194 static void r600_flush_dma_ring(void *ctx, unsigned flags)
 195 {
 196         struct r600_context *rctx = (struct r600_context *)ctx;
 197         struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
 198         unsigned padding_dw, i;
 199
 200         if (!cs->cdw) {
 201                 return;
 202         }
 203
 204         /* Pad the DMA CS to a multiple of 8 dwords. */
 205         padding_dw = 8 - cs->cdw % 8;
 206         if (padding_dw < 8) {
 207                 for (i = 0; i < padding_dw; i++) {
 208                         cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
 209                 }
 210         }
 211
 212         rctx->rings.dma.flushing = true;
 213         rctx->ws->cs_flush(cs, flags);
 214         rctx->rings.dma.flushing = false;
 215 }
 216
 217 boolean r600_rings_is_buffer_referenced(struct r600_context *ctx,
 218                                         struct radeon_winsys_cs_handle *buf,
 219                                         enum radeon_bo_usage usage)
 220 {
 221         if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, buf, usage)) {
 222                 return TRUE;
 223         }
 224         if (ctx->rings.dma.cs) {
 225                 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, buf, usage)) {
 226                         return TRUE;
 227                 }
 228         }
 229         return FALSE;
 230 }
 231
 232 void *r600_buffer_mmap_sync_with_rings(struct r600_context *ctx,
 233                                         struct r600_resource *resource,
 234                                         unsigned usage)
 235 {
 236         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
 237         unsigned flags = 0;
 238         bool sync_flush = TRUE;
 239
 240         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 241                 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
 242         }
 243
 244         if (!(usage & PIPE_TRANSFER_WRITE)) {
 245                 /* have to wait for pending read */
 246                 rusage = RADEON_USAGE_WRITE;
 247         }
 248         if (usage & PIPE_TRANSFER_DONTBLOCK) {
 249                 flags |= RADEON_FLUSH_ASYNC;
 250         }
 251
 252         if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, resource->cs_buf, rusage) && ctx->rings.gfx.cs->cdw) {
 253                 ctx->rings.gfx.flush(ctx, flags);
 254                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
 255                         return NULL;
 256                 }
 257         }
 258         if (ctx->rings.dma.cs) {
 259                 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, resource->cs_buf, rusage) && ctx->rings.dma.cs->cdw) {
 260                         ctx->rings.dma.flush(ctx, flags);
 261                         if (usage & PIPE_TRANSFER_DONTBLOCK) {
 262                                 return NULL;
 263                         }
 264                 }
 265         }
 266
 267         if (usage & PIPE_TRANSFER_DONTBLOCK) {
 268                 if (ctx->ws->buffer_is_busy(resource->buf, rusage)) {
 269                         return NULL;
 270                 }
 271         }
 272         if (sync_flush) {
 273                 /* Try to avoid busy-waiting in radeon_bo_wait. */
 274                 ctx->ws->cs_sync_flush(ctx->rings.gfx.cs);
 275                 if (ctx->rings.dma.cs) {
 276                         ctx->ws->cs_sync_flush(ctx->rings.dma.cs);
 277                 }
 278         }
 279         ctx->ws->buffer_wait(resource->buf, rusage);
 280
 281         /* at this point everything is synchronized */
 282         return ctx->ws->buffer_map(resource->cs_buf, NULL, usage | PIPE_TRANSFER_UNSYNCHRONIZED);
 283 }
 284
 285 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 286 {
 287         struct r600_context *rctx = (struct r600_context *)ctx;
 288
 289         rctx->rings.gfx.flush(rctx, flags);
 290 }
 291
 292 static void r600_flush_dma_from_winsys(void *ctx, unsigned flags)
 293 {
 294         struct r600_context *rctx = (struct r600_context *)ctx;
 295
 296         rctx->rings.dma.flush(rctx, flags);
 297 }
 298
 299 static void r600_destroy_context(struct pipe_context *context)
 300 {
 301         struct r600_context *rctx = (struct r600_context *)context;
 302
 303         r600_isa_destroy(rctx->isa);
 304
 305         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
 306         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
 307
 308         if (rctx->dummy_pixel_shader) {
 309                 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 310         }
 311         if (rctx->custom_dsa_flush) {
 312                 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 313         }
 314         if (rctx->custom_blend_resolve) {
 315                 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve);
 316         }
 317         if (rctx->custom_blend_decompress) {
 318                 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_decompress);
 319         }
 320         if (rctx->custom_blend_fmask_decompress) {
 321                 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_fmask_decompress);
 322         }
 323         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 324
 325         if (rctx->blitter) {
 326                 util_blitter_destroy(rctx->blitter);
 327         }
 328         if (rctx->uploader) {
 329                 u_upload_destroy(rctx->uploader);
 330         }
 331         if (rctx->allocator_so_filled_size) {
 332                 u_suballocator_destroy(rctx->allocator_so_filled_size);
 333         }
 334         if (rctx->allocator_fetch_shader) {
 335                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 336         }
 337         util_slab_destroy(&rctx->pool_transfers);
 338
 339         r600_release_command_buffer(&rctx->start_cs_cmd);
 340
 341         if (rctx->rings.gfx.cs) {
 342                 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
 343         }
 344         if (rctx->rings.dma.cs) {
 345                 rctx->ws->cs_destroy(rctx->rings.dma.cs);
 346         }
 347
 348         FREE(rctx);
 349 }
 350
 351 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 352 {
 353         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 354         struct r600_screen* rscreen = (struct r600_screen *)screen;
 355
 356         if (rctx == NULL)
 357                 return NULL;
 358
 359         util_slab_create(&rctx->pool_transfers,
 360                          sizeof(struct r600_transfer), 64,
 361                          UTIL_SLAB_SINGLETHREADED);
 362
 363         rctx->context.screen = screen;
 364         rctx->context.priv = priv;
 365         rctx->context.destroy = r600_destroy_context;
 366         rctx->context.flush = r600_flush_from_st;
 367
 368         /* Easy accessing of screen/winsys. */
 369         rctx->screen = rscreen;
 370         rctx->ws = rscreen->ws;
 371         rctx->family = rscreen->family;
 372         rctx->chip_class = rscreen->chip_class;
 373         rctx->keep_tiling_flags = rscreen->info.drm_minor >= 12;
 374
 375         LIST_INITHEAD(&rctx->active_nontimer_queries);
 376
 377         r600_init_blit_functions(rctx);
 378         r600_init_query_functions(rctx);
 379         r600_init_context_resource_functions(rctx);
 380         r600_init_surface_functions(rctx);
 381
 382         rctx->context.create_video_decoder = vl_create_decoder;
 383         rctx->context.create_video_buffer = vl_video_buffer_create;
 384
 385         r600_init_common_state_functions(rctx);
 386
 387         switch (rctx->chip_class) {
 388         case R600:
 389         case R700:
 390                 r600_init_state_functions(rctx);
 391                 r600_init_atom_start_cs(rctx);
 392                 rctx->max_db = 4;
 393                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 394                 rctx->custom_blend_resolve = rctx->chip_class == R700 ? r700_create_resolve_blend(rctx)
 395                                                                       : r600_create_resolve_blend(rctx);
 396                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 397                 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
 398                                            rctx->family == CHIP_RV620 ||
 399                                            rctx->family == CHIP_RS780 ||
 400                                            rctx->family == CHIP_RS880 ||
 401                                            rctx->family == CHIP_RV710);
 402                 break;
 403         case EVERGREEN:
 404         case CAYMAN:
 405                 evergreen_init_state_functions(rctx);
 406                 evergreen_init_atom_start_cs(rctx);
 407                 evergreen_init_atom_start_compute_cs(rctx);
 408                 rctx->max_db = 8;
 409                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 410                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 411                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 412                 rctx->custom_blend_fmask_decompress = evergreen_create_fmask_decompress_blend(rctx);
 413                 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
 414                                            rctx->family == CHIP_PALM ||
 415                                            rctx->family == CHIP_SUMO ||
 416                                            rctx->family == CHIP_SUMO2 ||
 417                                            rctx->family == CHIP_CAICOS ||
 418                                            rctx->family == CHIP_CAYMAN ||
 419                                            rctx->family == CHIP_ARUBA);
 420                 break;
 421         default:
 422                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 423                 goto fail;
 424         }
 425
 426         rctx->rings.gfx.cs = rctx->ws->cs_create(rctx->ws, RING_GFX);
 427         rctx->rings.gfx.flush = r600_flush_gfx_ring;
 428         rctx->ws->cs_set_flush_callback(rctx->rings.gfx.cs, r600_flush_from_winsys, rctx);
 429         rctx->rings.gfx.flushing = false;
 430
 431         rctx->rings.dma.cs = NULL;
 432         if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
 433                 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA);
 434                 rctx->rings.dma.flush = r600_flush_dma_ring;
 435                 rctx->ws->cs_set_flush_callback(rctx->rings.dma.cs, r600_flush_dma_from_winsys, rctx);
 436                 rctx->rings.dma.flushing = false;
 437         }
 438
 439         rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
 440                                         PIPE_BIND_INDEX_BUFFER |
 441                                         PIPE_BIND_CONSTANT_BUFFER);
 442         if (!rctx->uploader)
 443                 goto fail;
 444
 445         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->context, 64 * 1024, 256,
 446                                                              0, PIPE_USAGE_STATIC, FALSE);
 447         if (!rctx->allocator_fetch_shader)
 448                 goto fail;
 449
 450         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->context, 4096, 4,
 451                                                                 0, PIPE_USAGE_STATIC, TRUE);
 452         if (!rctx->allocator_so_filled_size)
 453                 goto fail;
 454
 455         rctx->isa = calloc(1, sizeof(struct r600_isa));
 456         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 457                 goto fail;
 458
 459         rctx->blitter = util_blitter_create(&rctx->context);
 460         if (rctx->blitter == NULL)
 461                 goto fail;
 462         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 463         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 464
 465         r600_begin_new_cs(rctx);
 466         r600_get_backend_mask(rctx); /* this emits commands and must be last */
 467
 468         rctx->dummy_pixel_shader =
 469                 util_make_fragment_cloneinput_shader(&rctx->context, 0,
 470                                                      TGSI_SEMANTIC_GENERIC,
 471                                                      TGSI_INTERPOLATE_CONSTANT);
 472         rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 473
 474         return &rctx->context;
 475
 476 fail:
 477         r600_destroy_context(&rctx->context);
 478         return NULL;
 479 }
 480
 481 /*
 482  * pipe_screen
 483  */
 484 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 485 {
 486         return "X.Org";
 487 }
 488
 489 static const char *r600_get_family_name(enum radeon_family family)
 490 {
 491         switch(family) {
 492         case CHIP_R600: return "AMD R600";
 493         case CHIP_RV610: return "AMD RV610";
 494         case CHIP_RV630: return "AMD RV630";
 495         case CHIP_RV670: return "AMD RV670";
 496         case CHIP_RV620: return "AMD RV620";
 497         case CHIP_RV635: return "AMD RV635";
 498         case CHIP_RS780: return "AMD RS780";
 499         case CHIP_RS880: return "AMD RS880";
 500         case CHIP_RV770: return "AMD RV770";
 501         case CHIP_RV730: return "AMD RV730";
 502         case CHIP_RV710: return "AMD RV710";
 503         case CHIP_RV740: return "AMD RV740";
 504         case CHIP_CEDAR: return "AMD CEDAR";
 505         case CHIP_REDWOOD: return "AMD REDWOOD";
 506         case CHIP_JUNIPER: return "AMD JUNIPER";
 507         case CHIP_CYPRESS: return "AMD CYPRESS";
 508         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 509         case CHIP_PALM: return "AMD PALM";
 510         case CHIP_SUMO: return "AMD SUMO";
 511         case CHIP_SUMO2: return "AMD SUMO2";
 512         case CHIP_BARTS: return "AMD BARTS";
 513         case CHIP_TURKS: return "AMD TURKS";
 514         case CHIP_CAICOS: return "AMD CAICOS";
 515         case CHIP_CAYMAN: return "AMD CAYMAN";
 516         case CHIP_ARUBA: return "AMD ARUBA";
 517         default: return "AMD unknown";
 518         }
 519 }
 520
 521 static const char* r600_get_name(struct pipe_screen* pscreen)
 522 {
 523         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 524
 525         return r600_get_family_name(rscreen->family);
 526 }
 527
 528 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 529 {
 530         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 531         enum radeon_family family = rscreen->family;
 532
 533         switch (param) {
 534         /* Supported features (boolean caps). */
 535         case PIPE_CAP_NPOT_TEXTURES:
 536         case PIPE_CAP_TWO_SIDED_STENCIL:
 537         case PIPE_CAP_ANISOTROPIC_FILTER:
 538         case PIPE_CAP_POINT_SPRITE:
 539         case PIPE_CAP_OCCLUSION_QUERY:
 540         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 541         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 542         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 543         case PIPE_CAP_TEXTURE_SWIZZLE:
 544         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 545         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 546         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 547         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 548         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 549         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 550         case PIPE_CAP_SM3:
 551         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 552         case PIPE_CAP_PRIMITIVE_RESTART:
 553         case PIPE_CAP_CONDITIONAL_RENDER:
 554         case PIPE_CAP_TEXTURE_BARRIER:
 555         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 556         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 557         case PIPE_CAP_TGSI_INSTANCEID:
 558         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 559         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 560         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 561         case PIPE_CAP_USER_INDEX_BUFFERS:
 562         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 563         case PIPE_CAP_COMPUTE:
 564         case PIPE_CAP_START_INSTANCE:
 565         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 566         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 567                 return 1;
 568         case PIPE_CAP_TGSI_TEXCOORD:
 569                 return 0;
 570
 571         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 572                 return R600_MAP_BUFFER_ALIGNMENT;
 573
 574         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 575                 return 256;
 576
 577         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 578                 return 140;
 579
 580         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 581                 return rscreen->msaa_texture_support != MSAA_TEXTURE_SAMPLE_ZERO;
 582
 583         /* Supported except the original R600. */
 584         case PIPE_CAP_INDEP_BLEND_ENABLE:
 585         case PIPE_CAP_INDEP_BLEND_FUNC:
 586                 /* R600 doesn't support per-MRT blends */
 587                 return family == CHIP_R600 ? 0 : 1;
 588
 589         /* Supported on Evergreen. */
 590         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 591         case PIPE_CAP_CUBE_MAP_ARRAY:
 592                 return family >= CHIP_CEDAR ? 1 : 0;
 593
 594         /* Unsupported features. */
 595         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 596         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 597         case PIPE_CAP_SCALED_RESOLVE:
 598         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 599         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 600         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 601         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 602         case PIPE_CAP_USER_VERTEX_BUFFERS:
 603         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 604                 return 0;
 605
 606         /* Stream output. */
 607         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 608                 return rscreen->has_streamout ? 4 : 0;
 609         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 610                 return rscreen->has_streamout ? 1 : 0;
 611         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 612         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 613                 return 32*4;
 614
 615         /* Texturing. */
 616         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 617         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 618         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 619                 if (family >= CHIP_CEDAR)
 620                         return 15;
 621                 else
 622                         return 14;
 623         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 624                 return rscreen->info.drm_minor >= 9 ?
 625                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 626         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 627                 return 32;
 628
 629         /* Render targets. */
 630         case PIPE_CAP_MAX_RENDER_TARGETS:
 631                 /* XXX some r6xx are buggy and can only do 4 */
 632                 return 8;
 633
 634         /* Timer queries, present when the clock frequency is non zero. */
 635         case PIPE_CAP_QUERY_TIME_ELAPSED:
 636                 return rscreen->info.r600_clock_crystal_freq != 0;
 637         case PIPE_CAP_QUERY_TIMESTAMP:
 638                 return rscreen->info.drm_minor >= 20 &&
 639                        rscreen->info.r600_clock_crystal_freq != 0;
 640
 641         case PIPE_CAP_MIN_TEXEL_OFFSET:
 642                 return -8;
 643
 644         case PIPE_CAP_MAX_TEXEL_OFFSET:
 645                 return 7;
 646         }
 647         return 0;
 648 }
 649
 650 static float r600_get_paramf(struct pipe_screen* pscreen,
 651                              enum pipe_capf param)
 652 {
 653         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 654         enum radeon_family family = rscreen->family;
 655
 656         switch (param) {
 657         case PIPE_CAPF_MAX_LINE_WIDTH:
 658         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 659         case PIPE_CAPF_MAX_POINT_WIDTH:
 660         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 661                 if (family >= CHIP_CEDAR)
 662                         return 16384.0f;
 663                 else
 664                         return 8192.0f;
 665         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 666                 return 16.0f;
 667         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 668                 return 16.0f;
 669         case PIPE_CAPF_GUARD_BAND_LEFT:
 670         case PIPE_CAPF_GUARD_BAND_TOP:
 671         case PIPE_CAPF_GUARD_BAND_RIGHT:
 672         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 673                 return 0.0f;
 674         }
 675         return 0.0f;
 676 }
 677
 678 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 679 {
 680         switch(shader)
 681         {
 682         case PIPE_SHADER_FRAGMENT:
 683         case PIPE_SHADER_VERTEX:
 684         case PIPE_SHADER_COMPUTE:
 685                 break;
 686         case PIPE_SHADER_GEOMETRY:
 687                 /* XXX: support and enable geometry programs */
 688                 return 0;
 689         default:
 690                 /* XXX: support tessellation on Evergreen */
 691                 return 0;
 692         }
 693
 694         switch (param) {
 695         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 696         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 697         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 698         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 699                 return 16384;
 700         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 701                 return 32;
 702         case PIPE_SHADER_CAP_MAX_INPUTS:
 703                 return 32;
 704         case PIPE_SHADER_CAP_MAX_TEMPS:
 705                 return 256; /* Max native temporaries. */
 706         case PIPE_SHADER_CAP_MAX_ADDRS:
 707                 /* XXX Isn't this equal to TEMPS? */
 708                 return 1; /* Max native address registers */
 709         case PIPE_SHADER_CAP_MAX_CONSTS:
 710                 return R600_MAX_CONST_BUFFER_SIZE;
 711         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 712                 return R600_MAX_USER_CONST_BUFFERS;
 713         case PIPE_SHADER_CAP_MAX_PREDS:
 714                 return 0; /* nothing uses this */
 715         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 716                 return 1;
 717         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 718                 return 0;
 719         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 720         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 721         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 722         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 723                 return 1;
 724         case PIPE_SHADER_CAP_SUBROUTINES:
 725                 return 0;
 726         case PIPE_SHADER_CAP_INTEGERS:
 727                 return 1;
 728         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 729                 return 16;
 730         case PIPE_SHADER_CAP_PREFERRED_IR:
 731                 if (shader == PIPE_SHADER_COMPUTE) {
 732                         return PIPE_SHADER_IR_LLVM;
 733                 } else {
 734                         return PIPE_SHADER_IR_TGSI;
 735                 }
 736         }
 737         return 0;
 738 }
 739
 740 static int r600_get_video_param(struct pipe_screen *screen,
 741                                 enum pipe_video_profile profile,
 742                                 enum pipe_video_cap param)
 743 {
 744         switch (param) {
 745         case PIPE_VIDEO_CAP_SUPPORTED:
 746                 return vl_profile_supported(screen, profile);
 747         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 748                 return 1;
 749         case PIPE_VIDEO_CAP_MAX_WIDTH:
 750         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 751                 return vl_video_buffer_max_size(screen);
 752         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 753                 return PIPE_FORMAT_NV12;
 754         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 755                 return false;
 756         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 757                 return false;
 758         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 759                 return true;
 760         default:
 761                 return 0;
 762         }
 763 }
 764
 765 static int r600_get_compute_param(struct pipe_screen *screen,
 766         enum pipe_compute_cap param,
 767         void *ret)
 768 {
 769         //TODO: select these params by asic
 770         switch (param) {
 771         case PIPE_COMPUTE_CAP_IR_TARGET:
 772                 if (ret) {
 773                         strcpy(ret, "r600--");
 774                 }
 775                 return 7 * sizeof(char);
 776
 777         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 778                 if (ret) {
 779                         uint64_t * grid_dimension = ret;
 780                         grid_dimension[0] = 3;
 781                 }
 782                 return 1 * sizeof(uint64_t);
 783
 784         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 785                 if (ret) {
 786                         uint64_t * grid_size = ret;
 787                         grid_size[0] = 65535;
 788                         grid_size[1] = 65535;
 789                         grid_size[2] = 1;
 790                 }
 791                 return 3 * sizeof(uint64_t) ;
 792
 793         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 794                 if (ret) {
 795                         uint64_t * block_size = ret;
 796                         block_size[0] = 256;
 797                         block_size[1] = 256;
 798                         block_size[2] = 256;
 799                 }
 800                 return 3 * sizeof(uint64_t);
 801
 802         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 803                 if (ret) {
 804                         uint64_t * max_threads_per_block = ret;
 805                         *max_threads_per_block = 256;
 806                 }
 807                 return sizeof(uint64_t);
 808
 809         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 810                 if (ret) {
 811                         uint64_t * max_global_size = ret;
 812                         /* XXX: This is what the proprietary driver reports, we
 813                          * may want to use a different value. */
 814                         *max_global_size = 201326592;
 815                 }
 816                 return sizeof(uint64_t);
 817
 818         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 819                 if (ret) {
 820                         uint64_t * max_input_size = ret;
 821                         *max_input_size = 1024;
 822                 }
 823                 return sizeof(uint64_t);
 824
 825         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 826                 if (ret) {
 827                         uint64_t * max_local_size = ret;
 828                         /* XXX: This is what the proprietary driver reports, we
 829                          * may want to use a different value. */
 830                         *max_local_size = 32768;
 831                 }
 832                 return sizeof(uint64_t);
 833
 834         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 835                 if (ret) {
 836                         uint64_t max_global_size;
 837                         uint64_t * max_mem_alloc_size = ret;
 838                         r600_get_compute_param(screen,
 839                                         PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
 840                                         &max_global_size);
 841                         /* OpenCL requres this value be at least
 842                          * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
 843                          * I'm really not sure what value to report here, but
 844                          * MAX_GLOBAL_SIZE / 4 seems resonable.
 845                          */
 846                         *max_mem_alloc_size = max_global_size / 4;
 847                 }
 848                 return sizeof(uint64_t);
 849
 850         default:
 851                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 852                 return 0;
 853         }
 854 }
 855
 856 static void r600_destroy_screen(struct pipe_screen* pscreen)
 857 {
 858         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 859
 860         if (rscreen == NULL)
 861                 return;
 862
 863         if (rscreen->global_pool) {
 864                 compute_memory_pool_delete(rscreen->global_pool);
 865         }
 866
 867         if (rscreen->fences.bo) {
 868                 struct r600_fence_block *entry, *tmp;
 869
 870                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 871                         LIST_DEL(&entry->head);
 872                         FREE(entry);
 873                 }
 874
 875                 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
 876                 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
 877         }
 878 #if R600_TRACE_CS
 879         if (rscreen->trace_bo) {
 880                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 881                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 882         }
 883 #endif
 884         pipe_mutex_destroy(rscreen->fences.mutex);
 885
 886         rscreen->ws->destroy(rscreen->ws);
 887         FREE(rscreen);
 888 }
 889
 890 static void r600_fence_reference(struct pipe_screen *pscreen,
 891                                  struct pipe_fence_handle **ptr,
 892                                  struct pipe_fence_handle *fence)
 893 {
 894         struct r600_fence **oldf = (struct r600_fence**)ptr;
 895         struct r600_fence *newf = (struct r600_fence*)fence;
 896
 897         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 898                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 899                 pipe_mutex_lock(rscreen->fences.mutex);
 900                 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
 901                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 902                 pipe_mutex_unlock(rscreen->fences.mutex);
 903         }
 904
 905         *ptr = fence;
 906 }
 907
 908 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 909                                     struct pipe_fence_handle *fence)
 910 {
 911         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 912         struct r600_fence *rfence = (struct r600_fence*)fence;
 913
 914         return rscreen->fences.data[rfence->index] != 0;
 915 }
 916
 917 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 918                                  struct pipe_fence_handle *fence,
 919                                  uint64_t timeout)
 920 {
 921         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 922         struct r600_fence *rfence = (struct r600_fence*)fence;
 923         int64_t start_time = 0;
 924         unsigned spins = 0;
 925
 926         if (timeout != PIPE_TIMEOUT_INFINITE) {
 927                 start_time = os_time_get();
 928
 929                 /* Convert to microseconds. */
 930                 timeout /= 1000;
 931         }
 932
 933         while (rscreen->fences.data[rfence->index] == 0) {
 934                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
 935                 if (timeout == PIPE_TIMEOUT_INFINITE) {
 936                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
 937                         break;
 938                 }
 939
 940                 /* The dummy BO will be busy until the CS including the fence has completed, or
 941                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
 942                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
 943                         break;
 944
 945                 if (++spins % 256)
 946                         continue;
 947 #ifdef PIPE_OS_UNIX
 948                 sched_yield();
 949 #else
 950                 os_time_sleep(10);
 951 #endif
 952                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 953                     os_time_get() - start_time >= timeout) {
 954                         break;
 955                 }
 956         }
 957
 958         return rscreen->fences.data[rfence->index] != 0;
 959 }
 960
 961 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 962 {
 963         switch ((tiling_config & 0xe) >> 1) {
 964         case 0:
 965                 rscreen->tiling_info.num_channels = 1;
 966                 break;
 967         case 1:
 968                 rscreen->tiling_info.num_channels = 2;
 969                 break;
 970         case 2:
 971                 rscreen->tiling_info.num_channels = 4;
 972                 break;
 973         case 3:
 974                 rscreen->tiling_info.num_channels = 8;
 975                 break;
 976         default:
 977                 return -EINVAL;
 978         }
 979
 980         switch ((tiling_config & 0x30) >> 4) {
 981         case 0:
 982                 rscreen->tiling_info.num_banks = 4;
 983                 break;
 984         case 1:
 985                 rscreen->tiling_info.num_banks = 8;
 986                 break;
 987         default:
 988                 return -EINVAL;
 989
 990         }
 991         switch ((tiling_config & 0xc0) >> 6) {
 992         case 0:
 993                 rscreen->tiling_info.group_bytes = 256;
 994                 break;
 995         case 1:
 996                 rscreen->tiling_info.group_bytes = 512;
 997                 break;
 998         default:
 999                 return -EINVAL;
1000         }
1001         return 0;
1002 }
1003
1004 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
1005 {
1006         switch (tiling_config & 0xf) {
1007         case 0:
1008                 rscreen->tiling_info.num_channels = 1;
1009                 break;
1010         case 1:
1011                 rscreen->tiling_info.num_channels = 2;
1012                 break;
1013         case 2:
1014                 rscreen->tiling_info.num_channels = 4;
1015                 break;
1016         case 3:
1017                 rscreen->tiling_info.num_channels = 8;
1018                 break;
1019         default:
1020                 return -EINVAL;
1021         }
1022
1023         switch ((tiling_config & 0xf0) >> 4) {
1024         case 0:
1025                 rscreen->tiling_info.num_banks = 4;
1026                 break;
1027         case 1:
1028                 rscreen->tiling_info.num_banks = 8;
1029                 break;
1030         case 2:
1031                 rscreen->tiling_info.num_banks = 16;
1032                 break;
1033         default:
1034                 return -EINVAL;
1035         }
1036
1037         switch ((tiling_config & 0xf00) >> 8) {
1038         case 0:
1039                 rscreen->tiling_info.group_bytes = 256;
1040                 break;
1041         case 1:
1042                 rscreen->tiling_info.group_bytes = 512;
1043                 break;
1044         default:
1045                 return -EINVAL;
1046         }
1047         return 0;
1048 }
1049
1050 static int r600_init_tiling(struct r600_screen *rscreen)
1051 {
1052         uint32_t tiling_config = rscreen->info.r600_tiling_config;
1053
1054         /* set default group bytes, overridden by tiling info ioctl */
1055         if (rscreen->chip_class <= R700) {
1056                 rscreen->tiling_info.group_bytes = 256;
1057         } else {
1058                 rscreen->tiling_info.group_bytes = 512;
1059         }
1060
1061         if (!tiling_config)
1062                 return 0;
1063
1064         if (rscreen->chip_class <= R700) {
1065                 return r600_interpret_tiling(rscreen, tiling_config);
1066         } else {
1067                 return evergreen_interpret_tiling(rscreen, tiling_config);
1068         }
1069 }
1070
1071 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1072 {
1073         struct r600_screen *rscreen = (struct r600_screen*)screen;
1074
1075         return 1000000 * rscreen->ws->query_timestamp(rscreen->ws) /
1076                         rscreen->info.r600_clock_crystal_freq;
1077 }
1078
1079 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
1080 {
1081         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
1082
1083         if (rscreen == NULL) {
1084                 return NULL;
1085         }
1086
1087         rscreen->ws = ws;
1088         ws->query_info(ws, &rscreen->info);
1089
1090         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", debug_options, 0);
1091         rscreen->family = rscreen->info.family;
1092         rscreen->chip_class = rscreen->info.chip_class;
1093
1094         if (rscreen->family == CHIP_UNKNOWN) {
1095                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
1096                 FREE(rscreen);
1097                 return NULL;
1098         }
1099
1100         /* Figure out streamout kernel support. */
1101         switch (rscreen->chip_class) {
1102         case R600:
1103                 if (rscreen->family < CHIP_RS780) {
1104                         rscreen->has_streamout = rscreen->info.drm_minor >= 14;
1105                 } else {
1106                         rscreen->has_streamout = rscreen->info.drm_minor >= 23;
1107                 }
1108                 break;
1109         case R700:
1110                 rscreen->has_streamout = rscreen->info.drm_minor >= 17;
1111                 break;
1112         case EVERGREEN:
1113         case CAYMAN:
1114                 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
1115                 break;
1116         default:
1117                 rscreen->has_streamout = FALSE;
1118                 break;
1119         }
1120
1121         /* MSAA support. */
1122         switch (rscreen->chip_class) {
1123         case R600:
1124         case R700:
1125                 rscreen->has_msaa = rscreen->info.drm_minor >= 22;
1126                 rscreen->msaa_texture_support = MSAA_TEXTURE_DECOMPRESSED;
1127                 break;
1128         case EVERGREEN:
1129                 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
1130                 rscreen->msaa_texture_support =
1131                         rscreen->info.drm_minor >= 24 ? MSAA_TEXTURE_COMPRESSED :
1132                                                         MSAA_TEXTURE_DECOMPRESSED;
1133                 break;
1134         case CAYMAN:
1135                 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
1136                 /* We should be able to read compressed MSAA textures, but it doesn't work. */
1137                 rscreen->msaa_texture_support = MSAA_TEXTURE_SAMPLE_ZERO;
1138                 break;
1139         default:
1140                 rscreen->has_msaa = FALSE;
1141                 rscreen->msaa_texture_support = 0;
1142                 break;
1143         }
1144
1145         rscreen->has_cp_dma = rscreen->info.drm_minor >= 27 &&
1146                               !(rscreen->debug_flags & DBG_NO_CP_DMA);
1147
1148         if (r600_init_tiling(rscreen)) {
1149                 FREE(rscreen);
1150                 return NULL;
1151         }
1152
1153         rscreen->screen.destroy = r600_destroy_screen;
1154         rscreen->screen.get_name = r600_get_name;
1155         rscreen->screen.get_vendor = r600_get_vendor;
1156         rscreen->screen.get_param = r600_get_param;
1157         rscreen->screen.get_shader_param = r600_get_shader_param;
1158         rscreen->screen.get_paramf = r600_get_paramf;
1159         rscreen->screen.get_video_param = r600_get_video_param;
1160         rscreen->screen.get_compute_param = r600_get_compute_param;
1161         rscreen->screen.get_timestamp = r600_get_timestamp;
1162
1163         if (rscreen->chip_class >= EVERGREEN) {
1164                 rscreen->screen.is_format_supported = evergreen_is_format_supported;
1165                 rscreen->dma_blit = &evergreen_dma_blit;
1166         } else {
1167                 rscreen->screen.is_format_supported = r600_is_format_supported;
1168                 rscreen->dma_blit = &r600_dma_blit;
1169         }
1170         rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
1171         rscreen->screen.context_create = r600_create_context;
1172         rscreen->screen.fence_reference = r600_fence_reference;
1173         rscreen->screen.fence_signalled = r600_fence_signalled;
1174         rscreen->screen.fence_finish = r600_fence_finish;
1175         r600_init_screen_resource_functions(&rscreen->screen);
1176
1177         util_format_s3tc_init();
1178
1179         rscreen->fences.bo = NULL;
1180         rscreen->fences.data = NULL;
1181         rscreen->fences.next_index = 0;
1182         LIST_INITHEAD(&rscreen->fences.pool);
1183         LIST_INITHEAD(&rscreen->fences.blocks);
1184         pipe_mutex_init(rscreen->fences.mutex);
1185
1186         rscreen->global_pool = compute_memory_pool_new(rscreen);
1187
1188 #if R600_TRACE_CS
1189         rscreen->cs_count = 0;
1190         if (rscreen->info.drm_minor >= 28) {
1191                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->screen,
1192                                                                                 PIPE_BIND_CUSTOM,
1193                                                                                 PIPE_USAGE_STAGING,
1194                                                                                 4096);
1195                 if (rscreen->trace_bo) {
1196                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
1197                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
1198                 }
1199         }
1200 #endif
1201
1202         return &rscreen->screen;
1203 }