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[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_pipe.h"
24 #include "r600_public.h"
25 #include "r600_isa.h"
26 #include "evergreen_compute.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include <errno.h>
32 #include "pipe/p_shader_tokens.h"
33 #include "util/u_blitter.h"
34 #include "util/u_debug.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_simple_shaders.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_math.h"
40 #include "vl/vl_decoder.h"
41 #include "vl/vl_video_buffer.h"
42 #include "radeon/radeon_uvd.h"
43 #include "os/os_time.h"
44
45 static const struct debug_named_value debug_options[] = {
46 /* logging */
47 { "texdepth", DBG_TEX_DEPTH, "Print texture depth info" },
48 { "compute", DBG_COMPUTE, "Print compute info" },
49 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
50 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
51
52 /* shaders */
53 { "fs", DBG_FS, "Print fetch shaders" },
54 { "vs", DBG_VS, "Print vertex shaders" },
55 { "gs", DBG_GS, "Print geometry shaders" },
56 { "ps", DBG_PS, "Print pixel shaders" },
57 { "cs", DBG_CS, "Print compute shaders" },
58
59 /* features */
60 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
61 #if defined(R600_USE_LLVM)
62 { "nollvm", DBG_NO_LLVM, "Disable the LLVM shader compiler" },
63 #endif
64 { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
65 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
66 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
67 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
68
69 /* shader backend */
70 { "sb", DBG_SB, "Enable optimization of graphics shaders" },
71 { "sbcl", DBG_SB_CS, "Enable optimization of compute shaders" },
72 { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
73 { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
74 { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
75 { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
76 { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
77
78 DEBUG_NAMED_VALUE_END /* must be last */
79 };
80
81 /*
82 * pipe_context
83 */
84 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
85 {
86 struct r600_screen *rscreen = rctx->screen;
87 struct r600_fence *fence = NULL;
88
89 pipe_mutex_lock(rscreen->fences.mutex);
90
91 if (!rscreen->fences.bo) {
92 /* Create the shared buffer object */
93 rscreen->fences.bo = (struct r600_resource*)
94 pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
95 PIPE_USAGE_STAGING, 4096);
96 if (!rscreen->fences.bo) {
97 R600_ERR("r600: failed to create bo for fence objects\n");
98 goto out;
99 }
100 rscreen->fences.data = r600_buffer_mmap_sync_with_rings(rctx, rscreen->fences.bo, PIPE_TRANSFER_READ_WRITE);
101 }
102
103 if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
104 struct r600_fence *entry;
105
106 /* Try to find a freed fence that has been signalled */
107 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
108 if (rscreen->fences.data[entry->index] != 0) {
109 LIST_DELINIT(&entry->head);
110 fence = entry;
111 break;
112 }
113 }
114 }
115
116 if (!fence) {
117 /* Allocate a new fence */
118 struct r600_fence_block *block;
119 unsigned index;
120
121 if ((rscreen->fences.next_index + 1) >= 1024) {
122 R600_ERR("r600: too many concurrent fences\n");
123 goto out;
124 }
125
126 index = rscreen->fences.next_index++;
127
128 if (!(index % FENCE_BLOCK_SIZE)) {
129 /* Allocate a new block */
130 block = CALLOC_STRUCT(r600_fence_block);
131 if (block == NULL)
132 goto out;
133
134 LIST_ADD(&block->head, &rscreen->fences.blocks);
135 } else {
136 block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
137 }
138
139 fence = &block->fences[index % FENCE_BLOCK_SIZE];
140 fence->index = index;
141 }
142
143 pipe_reference_init(&fence->reference, 1);
144
145 rscreen->fences.data[fence->index] = 0;
146 r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
147
148 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
149 fence->sleep_bo = (struct r600_resource*)
150 pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
151 PIPE_USAGE_STAGING, 1);
152 /* Add the fence as a dummy relocation. */
153 r600_context_bo_reloc(rctx, &rctx->rings.gfx, fence->sleep_bo, RADEON_USAGE_READWRITE);
154
155 out:
156 pipe_mutex_unlock(rscreen->fences.mutex);
157 return fence;
158 }
159
160 static void r600_flush(struct pipe_context *ctx, unsigned flags)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct pipe_query *render_cond = NULL;
164 unsigned render_cond_mode = 0;
165 boolean render_cond_cond = FALSE;
166
167 if (rctx->rings.gfx.cs->cdw == rctx->initial_gfx_cs_size)
168 return;
169
170 rctx->rings.gfx.flushing = true;
171 /* Disable render condition. */
172 if (rctx->current_render_cond) {
173 render_cond = rctx->current_render_cond;
174 render_cond_cond = rctx->current_render_cond_cond;
175 render_cond_mode = rctx->current_render_cond_mode;
176 ctx->render_condition(ctx, NULL, FALSE, 0);
177 }
178
179 r600_context_flush(rctx, flags);
180 rctx->rings.gfx.flushing = false;
181 r600_begin_new_cs(rctx);
182
183 /* Re-enable render condition. */
184 if (render_cond) {
185 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
186 }
187
188 rctx->initial_gfx_cs_size = rctx->rings.gfx.cs->cdw;
189 }
190
191 static void r600_flush_from_st(struct pipe_context *ctx,
192 struct pipe_fence_handle **fence,
193 unsigned flags)
194 {
195 struct r600_context *rctx = (struct r600_context *)ctx;
196 struct r600_fence **rfence = (struct r600_fence**)fence;
197 unsigned fflags;
198
199 fflags = flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0;
200 if (rfence) {
201 *rfence = r600_create_fence(rctx);
202 }
203 /* flush gfx & dma ring, order does not matter as only one can be live */
204 if (rctx->rings.dma.cs) {
205 rctx->rings.dma.flush(rctx, fflags);
206 }
207 rctx->rings.gfx.flush(rctx, fflags);
208 }
209
210 static void r600_flush_gfx_ring(void *ctx, unsigned flags)
211 {
212 r600_flush((struct pipe_context*)ctx, flags);
213 }
214
215 static void r600_flush_dma_ring(void *ctx, unsigned flags)
216 {
217 struct r600_context *rctx = (struct r600_context *)ctx;
218 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
219 unsigned padding_dw, i;
220
221 if (!cs->cdw) {
222 return;
223 }
224
225 /* Pad the DMA CS to a multiple of 8 dwords. */
226 padding_dw = 8 - cs->cdw % 8;
227 if (padding_dw < 8) {
228 for (i = 0; i < padding_dw; i++) {
229 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
230 }
231 }
232
233 rctx->rings.dma.flushing = true;
234 rctx->ws->cs_flush(cs, flags, 0);
235 rctx->rings.dma.flushing = false;
236 }
237
238 boolean r600_rings_is_buffer_referenced(struct r600_context *ctx,
239 struct radeon_winsys_cs_handle *buf,
240 enum radeon_bo_usage usage)
241 {
242 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, buf, usage)) {
243 return TRUE;
244 }
245 if (ctx->rings.dma.cs) {
246 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, buf, usage)) {
247 return TRUE;
248 }
249 }
250 return FALSE;
251 }
252
253 void *r600_buffer_mmap_sync_with_rings(struct r600_context *ctx,
254 struct r600_resource *resource,
255 unsigned usage)
256 {
257 enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
258 unsigned flags = 0;
259 bool sync_flush = TRUE;
260
261 if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
262 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
263 }
264
265 if (!(usage & PIPE_TRANSFER_WRITE)) {
266 /* have to wait for pending read */
267 rusage = RADEON_USAGE_WRITE;
268 }
269 if (usage & PIPE_TRANSFER_DONTBLOCK) {
270 flags |= RADEON_FLUSH_ASYNC;
271 }
272
273 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, resource->cs_buf, rusage) && ctx->rings.gfx.cs->cdw) {
274 ctx->rings.gfx.flush(ctx, flags);
275 if (usage & PIPE_TRANSFER_DONTBLOCK) {
276 return NULL;
277 }
278 }
279 if (ctx->rings.dma.cs) {
280 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, resource->cs_buf, rusage) && ctx->rings.dma.cs->cdw) {
281 ctx->rings.dma.flush(ctx, flags);
282 if (usage & PIPE_TRANSFER_DONTBLOCK) {
283 return NULL;
284 }
285 }
286 }
287
288 if (usage & PIPE_TRANSFER_DONTBLOCK) {
289 if (ctx->ws->buffer_is_busy(resource->buf, rusage)) {
290 return NULL;
291 }
292 }
293 if (sync_flush) {
294 /* Try to avoid busy-waiting in radeon_bo_wait. */
295 ctx->ws->cs_sync_flush(ctx->rings.gfx.cs);
296 if (ctx->rings.dma.cs) {
297 ctx->ws->cs_sync_flush(ctx->rings.dma.cs);
298 }
299 }
300
301 /* at this point everything is synchronized */
302 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
303 }
304
305 static void r600_flush_from_winsys(void *ctx, unsigned flags)
306 {
307 struct r600_context *rctx = (struct r600_context *)ctx;
308
309 rctx->rings.gfx.flush(rctx, flags);
310 }
311
312 static void r600_flush_dma_from_winsys(void *ctx, unsigned flags)
313 {
314 struct r600_context *rctx = (struct r600_context *)ctx;
315
316 rctx->rings.dma.flush(rctx, flags);
317 }
318
319 static void r600_destroy_context(struct pipe_context *context)
320 {
321 struct r600_context *rctx = (struct r600_context *)context;
322
323 r600_isa_destroy(rctx->isa);
324
325 r600_sb_context_destroy(rctx->sb_context);
326
327 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
328 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
329
330 if (rctx->dummy_pixel_shader) {
331 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
332 }
333 if (rctx->custom_dsa_flush) {
334 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
335 }
336 if (rctx->custom_blend_resolve) {
337 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve);
338 }
339 if (rctx->custom_blend_decompress) {
340 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_decompress);
341 }
342 util_unreference_framebuffer_state(&rctx->framebuffer.state);
343
344 if (rctx->blitter) {
345 util_blitter_destroy(rctx->blitter);
346 }
347 if (rctx->uploader) {
348 u_upload_destroy(rctx->uploader);
349 }
350 if (rctx->allocator_so_filled_size) {
351 u_suballocator_destroy(rctx->allocator_so_filled_size);
352 }
353 if (rctx->allocator_fetch_shader) {
354 u_suballocator_destroy(rctx->allocator_fetch_shader);
355 }
356 util_slab_destroy(&rctx->pool_transfers);
357
358 r600_release_command_buffer(&rctx->start_cs_cmd);
359
360 if (rctx->rings.gfx.cs) {
361 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
362 }
363 if (rctx->rings.dma.cs) {
364 rctx->ws->cs_destroy(rctx->rings.dma.cs);
365 }
366
367 FREE(rctx);
368 }
369
370 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
371 {
372 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
373 struct r600_screen* rscreen = (struct r600_screen *)screen;
374
375 if (rctx == NULL)
376 return NULL;
377
378 util_slab_create(&rctx->pool_transfers,
379 sizeof(struct r600_transfer), 64,
380 UTIL_SLAB_SINGLETHREADED);
381
382 rctx->context.screen = screen;
383 rctx->context.priv = priv;
384 rctx->context.destroy = r600_destroy_context;
385 rctx->context.flush = r600_flush_from_st;
386
387 /* Easy accessing of screen/winsys. */
388 rctx->screen = rscreen;
389 rctx->ws = rscreen->ws;
390 rctx->family = rscreen->family;
391 rctx->chip_class = rscreen->chip_class;
392 rctx->keep_tiling_flags = rscreen->info.drm_minor >= 12;
393
394 LIST_INITHEAD(&rctx->active_nontimer_queries);
395
396 r600_init_blit_functions(rctx);
397 r600_init_query_functions(rctx);
398 r600_init_context_resource_functions(rctx);
399 r600_init_surface_functions(rctx);
400
401 if (rscreen->info.has_uvd) {
402 rctx->context.create_video_decoder = r600_uvd_create_decoder;
403 rctx->context.create_video_buffer = r600_video_buffer_create;
404 } else {
405 rctx->context.create_video_decoder = vl_create_decoder;
406 rctx->context.create_video_buffer = vl_video_buffer_create;
407 }
408
409 r600_init_common_state_functions(rctx);
410
411 switch (rctx->chip_class) {
412 case R600:
413 case R700:
414 r600_init_state_functions(rctx);
415 r600_init_atom_start_cs(rctx);
416 rctx->max_db = 4;
417 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
418 rctx->custom_blend_resolve = rctx->chip_class == R700 ? r700_create_resolve_blend(rctx)
419 : r600_create_resolve_blend(rctx);
420 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
421 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
422 rctx->family == CHIP_RV620 ||
423 rctx->family == CHIP_RS780 ||
424 rctx->family == CHIP_RS880 ||
425 rctx->family == CHIP_RV710);
426 break;
427 case EVERGREEN:
428 case CAYMAN:
429 evergreen_init_state_functions(rctx);
430 evergreen_init_atom_start_cs(rctx);
431 evergreen_init_atom_start_compute_cs(rctx);
432 rctx->max_db = 8;
433 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
434 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
435 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
436 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
437 rctx->family == CHIP_PALM ||
438 rctx->family == CHIP_SUMO ||
439 rctx->family == CHIP_SUMO2 ||
440 rctx->family == CHIP_CAICOS ||
441 rctx->family == CHIP_CAYMAN ||
442 rctx->family == CHIP_ARUBA);
443 break;
444 default:
445 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
446 goto fail;
447 }
448
449 if (rscreen->trace_bo) {
450 rctx->rings.gfx.cs = rctx->ws->cs_create(rctx->ws, RING_GFX, rscreen->trace_bo->cs_buf);
451 } else {
452 rctx->rings.gfx.cs = rctx->ws->cs_create(rctx->ws, RING_GFX, NULL);
453 }
454 rctx->rings.gfx.flush = r600_flush_gfx_ring;
455 rctx->ws->cs_set_flush_callback(rctx->rings.gfx.cs, r600_flush_from_winsys, rctx);
456 rctx->rings.gfx.flushing = false;
457
458 rctx->rings.dma.cs = NULL;
459 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
460 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA, NULL);
461 rctx->rings.dma.flush = r600_flush_dma_ring;
462 rctx->ws->cs_set_flush_callback(rctx->rings.dma.cs, r600_flush_dma_from_winsys, rctx);
463 rctx->rings.dma.flushing = false;
464 }
465
466 rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
467 PIPE_BIND_INDEX_BUFFER |
468 PIPE_BIND_CONSTANT_BUFFER);
469 if (!rctx->uploader)
470 goto fail;
471
472 rctx->allocator_fetch_shader = u_suballocator_create(&rctx->context, 64 * 1024, 256,
473 0, PIPE_USAGE_STATIC, FALSE);
474 if (!rctx->allocator_fetch_shader)
475 goto fail;
476
477 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->context, 4096, 4,
478 0, PIPE_USAGE_STATIC, TRUE);
479 if (!rctx->allocator_so_filled_size)
480 goto fail;
481
482 rctx->isa = calloc(1, sizeof(struct r600_isa));
483 if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
484 goto fail;
485
486 rctx->blitter = util_blitter_create(&rctx->context);
487 if (rctx->blitter == NULL)
488 goto fail;
489 util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
490 rctx->blitter->draw_rectangle = r600_draw_rectangle;
491
492 r600_begin_new_cs(rctx);
493 r600_get_backend_mask(rctx); /* this emits commands and must be last */
494
495 rctx->dummy_pixel_shader =
496 util_make_fragment_cloneinput_shader(&rctx->context, 0,
497 TGSI_SEMANTIC_GENERIC,
498 TGSI_INTERPOLATE_CONSTANT);
499 rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
500
501 return &rctx->context;
502
503 fail:
504 r600_destroy_context(&rctx->context);
505 return NULL;
506 }
507
508 /*
509 * pipe_screen
510 */
511 static const char* r600_get_vendor(struct pipe_screen* pscreen)
512 {
513 return "X.Org";
514 }
515
516 static const char *r600_get_family_name(enum radeon_family family)
517 {
518 switch(family) {
519 case CHIP_R600: return "AMD R600";
520 case CHIP_RV610: return "AMD RV610";
521 case CHIP_RV630: return "AMD RV630";
522 case CHIP_RV670: return "AMD RV670";
523 case CHIP_RV620: return "AMD RV620";
524 case CHIP_RV635: return "AMD RV635";
525 case CHIP_RS780: return "AMD RS780";
526 case CHIP_RS880: return "AMD RS880";
527 case CHIP_RV770: return "AMD RV770";
528 case CHIP_RV730: return "AMD RV730";
529 case CHIP_RV710: return "AMD RV710";
530 case CHIP_RV740: return "AMD RV740";
531 case CHIP_CEDAR: return "AMD CEDAR";
532 case CHIP_REDWOOD: return "AMD REDWOOD";
533 case CHIP_JUNIPER: return "AMD JUNIPER";
534 case CHIP_CYPRESS: return "AMD CYPRESS";
535 case CHIP_HEMLOCK: return "AMD HEMLOCK";
536 case CHIP_PALM: return "AMD PALM";
537 case CHIP_SUMO: return "AMD SUMO";
538 case CHIP_SUMO2: return "AMD SUMO2";
539 case CHIP_BARTS: return "AMD BARTS";
540 case CHIP_TURKS: return "AMD TURKS";
541 case CHIP_CAICOS: return "AMD CAICOS";
542 case CHIP_CAYMAN: return "AMD CAYMAN";
543 case CHIP_ARUBA: return "AMD ARUBA";
544 default: return "AMD unknown";
545 }
546 }
547
548 static const char* r600_get_name(struct pipe_screen* pscreen)
549 {
550 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
551
552 return r600_get_family_name(rscreen->family);
553 }
554
555 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
556 {
557 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
558 enum radeon_family family = rscreen->family;
559
560 switch (param) {
561 /* Supported features (boolean caps). */
562 case PIPE_CAP_NPOT_TEXTURES:
563 case PIPE_CAP_TWO_SIDED_STENCIL:
564 case PIPE_CAP_ANISOTROPIC_FILTER:
565 case PIPE_CAP_POINT_SPRITE:
566 case PIPE_CAP_OCCLUSION_QUERY:
567 case PIPE_CAP_TEXTURE_SHADOW_MAP:
568 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
569 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
570 case PIPE_CAP_TEXTURE_SWIZZLE:
571 case PIPE_CAP_DEPTH_CLIP_DISABLE:
572 case PIPE_CAP_SHADER_STENCIL_EXPORT:
573 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
574 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
575 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
576 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
577 case PIPE_CAP_SM3:
578 case PIPE_CAP_SEAMLESS_CUBE_MAP:
579 case PIPE_CAP_PRIMITIVE_RESTART:
580 case PIPE_CAP_CONDITIONAL_RENDER:
581 case PIPE_CAP_TEXTURE_BARRIER:
582 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
583 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
584 case PIPE_CAP_TGSI_INSTANCEID:
585 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
586 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
587 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
588 case PIPE_CAP_USER_INDEX_BUFFERS:
589 case PIPE_CAP_USER_CONSTANT_BUFFERS:
590 case PIPE_CAP_COMPUTE:
591 case PIPE_CAP_START_INSTANCE:
592 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
593 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
594 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
595 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
596 case PIPE_CAP_TEXTURE_MULTISAMPLE:
597 return 1;
598
599 case PIPE_CAP_TGSI_TEXCOORD:
600 return 0;
601
602 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
603 return MIN2(rscreen->info.vram_size, 0xFFFFFFFF);
604
605 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
606 return R600_MAP_BUFFER_ALIGNMENT;
607
608 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
609 return 256;
610
611 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
612 return 1;
613
614 case PIPE_CAP_GLSL_FEATURE_LEVEL:
615 return 140;
616
617 /* Supported except the original R600. */
618 case PIPE_CAP_INDEP_BLEND_ENABLE:
619 case PIPE_CAP_INDEP_BLEND_FUNC:
620 /* R600 doesn't support per-MRT blends */
621 return family == CHIP_R600 ? 0 : 1;
622
623 /* Supported on Evergreen. */
624 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
625 case PIPE_CAP_CUBE_MAP_ARRAY:
626 return family >= CHIP_CEDAR ? 1 : 0;
627
628 /* Unsupported features. */
629 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
630 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
631 case PIPE_CAP_SCALED_RESOLVE:
632 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
633 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
634 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
635 case PIPE_CAP_USER_VERTEX_BUFFERS:
636 return 0;
637
638 /* Stream output. */
639 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
640 return rscreen->has_streamout ? 4 : 0;
641 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
642 return rscreen->has_streamout ? 1 : 0;
643 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
644 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
645 return 32*4;
646
647 /* Texturing. */
648 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
649 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
650 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
651 if (family >= CHIP_CEDAR)
652 return 15;
653 else
654 return 14;
655 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
656 return rscreen->info.drm_minor >= 9 ?
657 (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
658 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
659 return 32;
660
661 /* Render targets. */
662 case PIPE_CAP_MAX_RENDER_TARGETS:
663 /* XXX some r6xx are buggy and can only do 4 */
664 return 8;
665
666 /* Timer queries, present when the clock frequency is non zero. */
667 case PIPE_CAP_QUERY_TIME_ELAPSED:
668 return rscreen->info.r600_clock_crystal_freq != 0;
669 case PIPE_CAP_QUERY_TIMESTAMP:
670 return rscreen->info.drm_minor >= 20 &&
671 rscreen->info.r600_clock_crystal_freq != 0;
672
673 case PIPE_CAP_MIN_TEXEL_OFFSET:
674 return -8;
675
676 case PIPE_CAP_MAX_TEXEL_OFFSET:
677 return 7;
678
679 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
680 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
681 }
682 return 0;
683 }
684
685 static float r600_get_paramf(struct pipe_screen* pscreen,
686 enum pipe_capf param)
687 {
688 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
689 enum radeon_family family = rscreen->family;
690
691 switch (param) {
692 case PIPE_CAPF_MAX_LINE_WIDTH:
693 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
694 case PIPE_CAPF_MAX_POINT_WIDTH:
695 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
696 if (family >= CHIP_CEDAR)
697 return 16384.0f;
698 else
699 return 8192.0f;
700 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
701 return 16.0f;
702 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
703 return 16.0f;
704 case PIPE_CAPF_GUARD_BAND_LEFT:
705 case PIPE_CAPF_GUARD_BAND_TOP:
706 case PIPE_CAPF_GUARD_BAND_RIGHT:
707 case PIPE_CAPF_GUARD_BAND_BOTTOM:
708 return 0.0f;
709 }
710 return 0.0f;
711 }
712
713 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
714 {
715 switch(shader)
716 {
717 case PIPE_SHADER_FRAGMENT:
718 case PIPE_SHADER_VERTEX:
719 case PIPE_SHADER_COMPUTE:
720 break;
721 case PIPE_SHADER_GEOMETRY:
722 /* XXX: support and enable geometry programs */
723 return 0;
724 default:
725 /* XXX: support tessellation on Evergreen */
726 return 0;
727 }
728
729 switch (param) {
730 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
731 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
732 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
733 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
734 return 16384;
735 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
736 return 32;
737 case PIPE_SHADER_CAP_MAX_INPUTS:
738 return 32;
739 case PIPE_SHADER_CAP_MAX_TEMPS:
740 return 256; /* Max native temporaries. */
741 case PIPE_SHADER_CAP_MAX_ADDRS:
742 /* XXX Isn't this equal to TEMPS? */
743 return 1; /* Max native address registers */
744 case PIPE_SHADER_CAP_MAX_CONSTS:
745 return R600_MAX_CONST_BUFFER_SIZE;
746 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
747 return R600_MAX_USER_CONST_BUFFERS;
748 case PIPE_SHADER_CAP_MAX_PREDS:
749 return 0; /* nothing uses this */
750 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
751 return 1;
752 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
753 return 0;
754 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
755 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
756 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
757 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
758 return 1;
759 case PIPE_SHADER_CAP_SUBROUTINES:
760 return 0;
761 case PIPE_SHADER_CAP_INTEGERS:
762 return 1;
763 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
764 return 16;
765 case PIPE_SHADER_CAP_PREFERRED_IR:
766 if (shader == PIPE_SHADER_COMPUTE) {
767 return PIPE_SHADER_IR_LLVM;
768 } else {
769 return PIPE_SHADER_IR_TGSI;
770 }
771 }
772 return 0;
773 }
774
775 static int r600_get_video_param(struct pipe_screen *screen,
776 enum pipe_video_profile profile,
777 enum pipe_video_cap param)
778 {
779 switch (param) {
780 case PIPE_VIDEO_CAP_SUPPORTED:
781 return vl_profile_supported(screen, profile);
782 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
783 return 1;
784 case PIPE_VIDEO_CAP_MAX_WIDTH:
785 case PIPE_VIDEO_CAP_MAX_HEIGHT:
786 return vl_video_buffer_max_size(screen);
787 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
788 return PIPE_FORMAT_NV12;
789 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
790 return false;
791 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
792 return false;
793 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
794 return true;
795 default:
796 return 0;
797 }
798 }
799
800 const char * r600_llvm_gpu_string(enum radeon_family family)
801 {
802 const char * gpu_family;
803
804 switch (family) {
805 case CHIP_R600:
806 case CHIP_RV630:
807 case CHIP_RV635:
808 case CHIP_RV670:
809 gpu_family = "r600";
810 break;
811 case CHIP_RV610:
812 case CHIP_RV620:
813 case CHIP_RS780:
814 case CHIP_RS880:
815 gpu_family = "rs880";
816 break;
817 case CHIP_RV710:
818 gpu_family = "rv710";
819 break;
820 case CHIP_RV730:
821 gpu_family = "rv730";
822 break;
823 case CHIP_RV740:
824 case CHIP_RV770:
825 gpu_family = "rv770";
826 break;
827 case CHIP_PALM:
828 case CHIP_CEDAR:
829 gpu_family = "cedar";
830 break;
831 case CHIP_SUMO:
832 case CHIP_SUMO2:
833 gpu_family = "sumo";
834 break;
835 case CHIP_REDWOOD:
836 gpu_family = "redwood";
837 break;
838 case CHIP_JUNIPER:
839 gpu_family = "juniper";
840 break;
841 case CHIP_HEMLOCK:
842 case CHIP_CYPRESS:
843 gpu_family = "cypress";
844 break;
845 case CHIP_BARTS:
846 gpu_family = "barts";
847 break;
848 case CHIP_TURKS:
849 gpu_family = "turks";
850 break;
851 case CHIP_CAICOS:
852 gpu_family = "caicos";
853 break;
854 case CHIP_CAYMAN:
855 case CHIP_ARUBA:
856 gpu_family = "cayman";
857 break;
858 default:
859 gpu_family = "";
860 fprintf(stderr, "Chip not supported by r600 llvm "
861 "backend, please file a bug at " PACKAGE_BUGREPORT "\n");
862 break;
863 }
864 return gpu_family;
865 }
866
867
868 static int r600_get_compute_param(struct pipe_screen *screen,
869 enum pipe_compute_cap param,
870 void *ret)
871 {
872 struct r600_screen *rscreen = (struct r600_screen *)screen;
873 //TODO: select these params by asic
874 switch (param) {
875 case PIPE_COMPUTE_CAP_IR_TARGET: {
876 const char *gpu = r600_llvm_gpu_string(rscreen->family);
877 if (ret) {
878 sprintf(ret, "%s-r600--", gpu);
879 }
880 return (8 + strlen(gpu)) * sizeof(char);
881 }
882 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
883 if (ret) {
884 uint64_t * grid_dimension = ret;
885 grid_dimension[0] = 3;
886 }
887 return 1 * sizeof(uint64_t);
888
889 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
890 if (ret) {
891 uint64_t * grid_size = ret;
892 grid_size[0] = 65535;
893 grid_size[1] = 65535;
894 grid_size[2] = 1;
895 }
896 return 3 * sizeof(uint64_t) ;
897
898 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
899 if (ret) {
900 uint64_t * block_size = ret;
901 block_size[0] = 256;
902 block_size[1] = 256;
903 block_size[2] = 256;
904 }
905 return 3 * sizeof(uint64_t);
906
907 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
908 if (ret) {
909 uint64_t * max_threads_per_block = ret;
910 *max_threads_per_block = 256;
911 }
912 return sizeof(uint64_t);
913
914 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
915 if (ret) {
916 uint64_t * max_global_size = ret;
917 /* XXX: This is what the proprietary driver reports, we
918 * may want to use a different value. */
919 *max_global_size = 201326592;
920 }
921 return sizeof(uint64_t);
922
923 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
924 if (ret) {
925 uint64_t * max_input_size = ret;
926 *max_input_size = 1024;
927 }
928 return sizeof(uint64_t);
929
930 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
931 if (ret) {
932 uint64_t * max_local_size = ret;
933 /* XXX: This is what the proprietary driver reports, we
934 * may want to use a different value. */
935 *max_local_size = 32768;
936 }
937 return sizeof(uint64_t);
938
939 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
940 if (ret) {
941 uint64_t max_global_size;
942 uint64_t * max_mem_alloc_size = ret;
943 r600_get_compute_param(screen,
944 PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
945 &max_global_size);
946 /* OpenCL requres this value be at least
947 * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
948 * I'm really not sure what value to report here, but
949 * MAX_GLOBAL_SIZE / 4 seems resonable.
950 */
951 *max_mem_alloc_size = max_global_size / 4;
952 }
953 return sizeof(uint64_t);
954
955 default:
956 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
957 return 0;
958 }
959 }
960
961 static void r600_destroy_screen(struct pipe_screen* pscreen)
962 {
963 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
964
965 if (rscreen == NULL)
966 return;
967
968 pipe_mutex_destroy(rscreen->aux_context_lock);
969 rscreen->aux_context->destroy(rscreen->aux_context);
970
971 if (rscreen->global_pool) {
972 compute_memory_pool_delete(rscreen->global_pool);
973 }
974
975 if (rscreen->fences.bo) {
976 struct r600_fence_block *entry, *tmp;
977
978 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
979 LIST_DEL(&entry->head);
980 FREE(entry);
981 }
982
983 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
984 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
985 }
986 if (rscreen->trace_bo) {
987 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
988 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
989 }
990 pipe_mutex_destroy(rscreen->fences.mutex);
991
992 rscreen->ws->destroy(rscreen->ws);
993 FREE(rscreen);
994 }
995
996 static void r600_fence_reference(struct pipe_screen *pscreen,
997 struct pipe_fence_handle **ptr,
998 struct pipe_fence_handle *fence)
999 {
1000 struct r600_fence **oldf = (struct r600_fence**)ptr;
1001 struct r600_fence *newf = (struct r600_fence*)fence;
1002
1003 if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
1004 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
1005 pipe_mutex_lock(rscreen->fences.mutex);
1006 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
1007 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
1008 pipe_mutex_unlock(rscreen->fences.mutex);
1009 }
1010
1011 *ptr = fence;
1012 }
1013
1014 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
1015 struct pipe_fence_handle *fence)
1016 {
1017 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
1018 struct r600_fence *rfence = (struct r600_fence*)fence;
1019
1020 return rscreen->fences.data[rfence->index] != 0;
1021 }
1022
1023 static boolean r600_fence_finish(struct pipe_screen *pscreen,
1024 struct pipe_fence_handle *fence,
1025 uint64_t timeout)
1026 {
1027 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
1028 struct r600_fence *rfence = (struct r600_fence*)fence;
1029 int64_t start_time = 0;
1030 unsigned spins = 0;
1031
1032 if (timeout != PIPE_TIMEOUT_INFINITE) {
1033 start_time = os_time_get();
1034
1035 /* Convert to microseconds. */
1036 timeout /= 1000;
1037 }
1038
1039 while (rscreen->fences.data[rfence->index] == 0) {
1040 /* Special-case infinite timeout - wait for the dummy BO to become idle */
1041 if (timeout == PIPE_TIMEOUT_INFINITE) {
1042 rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
1043 break;
1044 }
1045
1046 /* The dummy BO will be busy until the CS including the fence has completed, or
1047 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
1048 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
1049 break;
1050
1051 if (++spins % 256)
1052 continue;
1053 #ifdef PIPE_OS_UNIX
1054 sched_yield();
1055 #else
1056 os_time_sleep(10);
1057 #endif
1058 if (timeout != PIPE_TIMEOUT_INFINITE &&
1059 os_time_get() - start_time >= timeout) {
1060 break;
1061 }
1062 }
1063
1064 return rscreen->fences.data[rfence->index] != 0;
1065 }
1066
1067 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
1068 {
1069 switch ((tiling_config & 0xe) >> 1) {
1070 case 0:
1071 rscreen->tiling_info.num_channels = 1;
1072 break;
1073 case 1:
1074 rscreen->tiling_info.num_channels = 2;
1075 break;
1076 case 2:
1077 rscreen->tiling_info.num_channels = 4;
1078 break;
1079 case 3:
1080 rscreen->tiling_info.num_channels = 8;
1081 break;
1082 default:
1083 return -EINVAL;
1084 }
1085
1086 switch ((tiling_config & 0x30) >> 4) {
1087 case 0:
1088 rscreen->tiling_info.num_banks = 4;
1089 break;
1090 case 1:
1091 rscreen->tiling_info.num_banks = 8;
1092 break;
1093 default:
1094 return -EINVAL;
1095
1096 }
1097 switch ((tiling_config & 0xc0) >> 6) {
1098 case 0:
1099 rscreen->tiling_info.group_bytes = 256;
1100 break;
1101 case 1:
1102 rscreen->tiling_info.group_bytes = 512;
1103 break;
1104 default:
1105 return -EINVAL;
1106 }
1107 return 0;
1108 }
1109
1110 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
1111 {
1112 switch (tiling_config & 0xf) {
1113 case 0:
1114 rscreen->tiling_info.num_channels = 1;
1115 break;
1116 case 1:
1117 rscreen->tiling_info.num_channels = 2;
1118 break;
1119 case 2:
1120 rscreen->tiling_info.num_channels = 4;
1121 break;
1122 case 3:
1123 rscreen->tiling_info.num_channels = 8;
1124 break;
1125 default:
1126 return -EINVAL;
1127 }
1128
1129 switch ((tiling_config & 0xf0) >> 4) {
1130 case 0:
1131 rscreen->tiling_info.num_banks = 4;
1132 break;
1133 case 1:
1134 rscreen->tiling_info.num_banks = 8;
1135 break;
1136 case 2:
1137 rscreen->tiling_info.num_banks = 16;
1138 break;
1139 default:
1140 return -EINVAL;
1141 }
1142
1143 switch ((tiling_config & 0xf00) >> 8) {
1144 case 0:
1145 rscreen->tiling_info.group_bytes = 256;
1146 break;
1147 case 1:
1148 rscreen->tiling_info.group_bytes = 512;
1149 break;
1150 default:
1151 return -EINVAL;
1152 }
1153 return 0;
1154 }
1155
1156 static int r600_init_tiling(struct r600_screen *rscreen)
1157 {
1158 uint32_t tiling_config = rscreen->info.r600_tiling_config;
1159
1160 /* set default group bytes, overridden by tiling info ioctl */
1161 if (rscreen->chip_class <= R700) {
1162 rscreen->tiling_info.group_bytes = 256;
1163 } else {
1164 rscreen->tiling_info.group_bytes = 512;
1165 }
1166
1167 if (!tiling_config)
1168 return 0;
1169
1170 if (rscreen->chip_class <= R700) {
1171 return r600_interpret_tiling(rscreen, tiling_config);
1172 } else {
1173 return evergreen_interpret_tiling(rscreen, tiling_config);
1174 }
1175 }
1176
1177 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1178 {
1179 struct r600_screen *rscreen = (struct r600_screen*)screen;
1180
1181 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1182 rscreen->info.r600_clock_crystal_freq;
1183 }
1184
1185 static int r600_get_driver_query_info(struct pipe_screen *screen,
1186 unsigned index,
1187 struct pipe_driver_query_info *info)
1188 {
1189 struct r600_screen *rscreen = (struct r600_screen*)screen;
1190 struct pipe_driver_query_info list[] = {
1191 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
1192 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
1193 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
1194 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE}
1195 };
1196
1197 if (!info)
1198 return Elements(list);
1199
1200 if (index >= Elements(list))
1201 return 0;
1202
1203 *info = list[index];
1204 return 1;
1205 }
1206
1207 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
1208 {
1209 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
1210
1211 if (rscreen == NULL) {
1212 return NULL;
1213 }
1214
1215 rscreen->ws = ws;
1216 ws->query_info(ws, &rscreen->info);
1217
1218 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", debug_options, 0);
1219 if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
1220 rscreen->debug_flags |= DBG_COMPUTE;
1221 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
1222 rscreen->debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
1223 if (!debug_get_bool_option("R600_HYPERZ", TRUE))
1224 rscreen->debug_flags |= DBG_NO_HYPERZ;
1225 if (!debug_get_bool_option("R600_LLVM", TRUE))
1226 rscreen->debug_flags |= DBG_NO_LLVM;
1227 if (debug_get_bool_option("R600_PRINT_TEXDEPTH", FALSE))
1228 rscreen->debug_flags |= DBG_TEX_DEPTH;
1229 rscreen->family = rscreen->info.family;
1230 rscreen->chip_class = rscreen->info.chip_class;
1231
1232 if (rscreen->family == CHIP_UNKNOWN) {
1233 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
1234 FREE(rscreen);
1235 return NULL;
1236 }
1237
1238 /* Figure out streamout kernel support. */
1239 switch (rscreen->chip_class) {
1240 case R600:
1241 if (rscreen->family < CHIP_RS780) {
1242 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
1243 } else {
1244 rscreen->has_streamout = rscreen->info.drm_minor >= 23;
1245 }
1246 break;
1247 case R700:
1248 rscreen->has_streamout = rscreen->info.drm_minor >= 17;
1249 break;
1250 case EVERGREEN:
1251 case CAYMAN:
1252 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
1253 break;
1254 default:
1255 rscreen->has_streamout = FALSE;
1256 break;
1257 }
1258
1259 /* MSAA support. */
1260 switch (rscreen->chip_class) {
1261 case R600:
1262 case R700:
1263 rscreen->has_msaa = rscreen->info.drm_minor >= 22;
1264 rscreen->has_compressed_msaa_texturing = false;
1265 break;
1266 case EVERGREEN:
1267 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
1268 rscreen->has_compressed_msaa_texturing = rscreen->info.drm_minor >= 24;
1269 break;
1270 case CAYMAN:
1271 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
1272 rscreen->has_compressed_msaa_texturing = true;
1273 break;
1274 default:
1275 rscreen->has_msaa = FALSE;
1276 rscreen->has_compressed_msaa_texturing = false;
1277 }
1278
1279 rscreen->has_cp_dma = rscreen->info.drm_minor >= 27 &&
1280 !(rscreen->debug_flags & DBG_NO_CP_DMA);
1281
1282 if (r600_init_tiling(rscreen)) {
1283 FREE(rscreen);
1284 return NULL;
1285 }
1286
1287 rscreen->screen.destroy = r600_destroy_screen;
1288 rscreen->screen.get_name = r600_get_name;
1289 rscreen->screen.get_vendor = r600_get_vendor;
1290 rscreen->screen.get_param = r600_get_param;
1291 rscreen->screen.get_shader_param = r600_get_shader_param;
1292 rscreen->screen.get_paramf = r600_get_paramf;
1293 rscreen->screen.get_compute_param = r600_get_compute_param;
1294 rscreen->screen.get_timestamp = r600_get_timestamp;
1295
1296 if (rscreen->chip_class >= EVERGREEN) {
1297 rscreen->screen.is_format_supported = evergreen_is_format_supported;
1298 rscreen->dma_blit = &evergreen_dma_blit;
1299 } else {
1300 rscreen->screen.is_format_supported = r600_is_format_supported;
1301 rscreen->dma_blit = &r600_dma_blit;
1302 }
1303 rscreen->screen.context_create = r600_create_context;
1304 rscreen->screen.fence_reference = r600_fence_reference;
1305 rscreen->screen.fence_signalled = r600_fence_signalled;
1306 rscreen->screen.fence_finish = r600_fence_finish;
1307 rscreen->screen.get_driver_query_info = r600_get_driver_query_info;
1308
1309 if (rscreen->info.has_uvd) {
1310 rscreen->screen.get_video_param = r600_uvd_get_video_param;
1311 rscreen->screen.is_video_format_supported = ruvd_is_format_supported;
1312 } else {
1313 rscreen->screen.get_video_param = r600_get_video_param;
1314 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
1315 }
1316
1317 r600_init_screen_resource_functions(&rscreen->screen);
1318
1319 util_format_s3tc_init();
1320
1321 rscreen->fences.bo = NULL;
1322 rscreen->fences.data = NULL;
1323 rscreen->fences.next_index = 0;
1324 LIST_INITHEAD(&rscreen->fences.pool);
1325 LIST_INITHEAD(&rscreen->fences.blocks);
1326 pipe_mutex_init(rscreen->fences.mutex);
1327
1328 rscreen->global_pool = compute_memory_pool_new(rscreen);
1329
1330 rscreen->cs_count = 0;
1331 if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
1332 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->screen,
1333 PIPE_BIND_CUSTOM,
1334 PIPE_USAGE_STAGING,
1335 4096);
1336 if (rscreen->trace_bo) {
1337 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
1338 PIPE_TRANSFER_UNSYNCHRONIZED);
1339 }
1340 }
1341
1342 /* Create the auxiliary context. */
1343 pipe_mutex_init(rscreen->aux_context_lock);
1344 rscreen->aux_context = rscreen->screen.context_create(&rscreen->screen, NULL);
1345
1346 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
1347 struct pipe_resource templ = {};
1348
1349 templ.width0 = 4;
1350 templ.height0 = 2048;
1351 templ.depth0 = 1;
1352 templ.array_size = 1;
1353 templ.target = PIPE_TEXTURE_2D;
1354 templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1355 templ.usage = PIPE_USAGE_STATIC;
1356
1357 struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
1358 unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
1359
1360 memset(map, 0, 256);
1361
1362 r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
1363 r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
1364 r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
1365 r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
1366 r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
1367
1368 ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
1369
1370 int i;
1371 for (i = 0; i < 256; i++) {
1372 printf("%02X", map[i]);
1373 if (i % 16 == 15)
1374 printf("\n");
1375 }
1376 #endif
1377
1378 return &rscreen->screen;
1379 }