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[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_pipe.h"
24 #include "r600_public.h"
25
26 #include <errno.h>
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_blitter.h"
29 #include "util/u_format_s3tc.h"
30 #include "util/u_simple_shaders.h"
31 #include "util/u_upload_mgr.h"
32 #include "vl/vl_decoder.h"
33 #include "vl/vl_video_buffer.h"
34 #include "os/os_time.h"
35
36 /*
37 * pipe_context
38 */
39 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
40 {
41 struct r600_screen *rscreen = rctx->screen;
42 struct r600_fence *fence = NULL;
43
44 pipe_mutex_lock(rscreen->fences.mutex);
45
46 if (!rscreen->fences.bo) {
47 /* Create the shared buffer object */
48 rscreen->fences.bo = (struct r600_resource*)
49 pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
50 PIPE_USAGE_STAGING, 4096);
51 if (!rscreen->fences.bo) {
52 R600_ERR("r600: failed to create bo for fence objects\n");
53 goto out;
54 }
55 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf,
56 rctx->cs,
57 PIPE_TRANSFER_READ_WRITE);
58 }
59
60 if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
61 struct r600_fence *entry;
62
63 /* Try to find a freed fence that has been signalled */
64 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
65 if (rscreen->fences.data[entry->index] != 0) {
66 LIST_DELINIT(&entry->head);
67 fence = entry;
68 break;
69 }
70 }
71 }
72
73 if (!fence) {
74 /* Allocate a new fence */
75 struct r600_fence_block *block;
76 unsigned index;
77
78 if ((rscreen->fences.next_index + 1) >= 1024) {
79 R600_ERR("r600: too many concurrent fences\n");
80 goto out;
81 }
82
83 index = rscreen->fences.next_index++;
84
85 if (!(index % FENCE_BLOCK_SIZE)) {
86 /* Allocate a new block */
87 block = CALLOC_STRUCT(r600_fence_block);
88 if (block == NULL)
89 goto out;
90
91 LIST_ADD(&block->head, &rscreen->fences.blocks);
92 } else {
93 block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
94 }
95
96 fence = &block->fences[index % FENCE_BLOCK_SIZE];
97 fence->index = index;
98 }
99
100 pipe_reference_init(&fence->reference, 1);
101
102 rscreen->fences.data[fence->index] = 0;
103 r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
104
105 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
106 fence->sleep_bo = (struct r600_resource*)
107 pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
108 PIPE_USAGE_STAGING, 1);
109 /* Add the fence as a dummy relocation. */
110 r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
111
112 out:
113 pipe_mutex_unlock(rscreen->fences.mutex);
114 return fence;
115 }
116
117
118 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
119 unsigned flags)
120 {
121 struct r600_context *rctx = (struct r600_context *)ctx;
122 struct r600_fence **rfence = (struct r600_fence**)fence;
123 struct pipe_query *render_cond = NULL;
124 unsigned render_cond_mode = 0;
125
126 if (rfence)
127 *rfence = r600_create_fence(rctx);
128
129 /* Disable render condition. */
130 if (rctx->current_render_cond) {
131 render_cond = rctx->current_render_cond;
132 render_cond_mode = rctx->current_render_cond_mode;
133 ctx->render_condition(ctx, NULL, 0);
134 }
135
136 r600_context_flush(rctx, flags);
137
138 /* Re-enable render condition. */
139 if (render_cond) {
140 ctx->render_condition(ctx, render_cond, render_cond_mode);
141 }
142 }
143
144 static void r600_flush_from_st(struct pipe_context *ctx,
145 struct pipe_fence_handle **fence)
146 {
147 r600_flush(ctx, fence, 0);
148 }
149
150 static void r600_flush_from_winsys(void *ctx, unsigned flags)
151 {
152 r600_flush((struct pipe_context*)ctx, NULL, flags);
153 }
154
155 static void r600_destroy_context(struct pipe_context *context)
156 {
157 struct r600_context *rctx = (struct r600_context *)context;
158
159 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
160 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
161
162 if (rctx->dummy_pixel_shader) {
163 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
164 }
165 if (rctx->custom_dsa_flush) {
166 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
167 }
168 if (rctx->custom_blend_resolve) {
169 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve);
170 }
171 if (rctx->custom_blend_decompress) {
172 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_decompress);
173 }
174 if (rctx->custom_blend_fmask_decompress) {
175 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_fmask_decompress);
176 }
177 util_unreference_framebuffer_state(&rctx->framebuffer.state);
178
179 r600_context_fini(rctx);
180
181 if (rctx->blitter) {
182 util_blitter_destroy(rctx->blitter);
183 }
184 if (rctx->uploader) {
185 u_upload_destroy(rctx->uploader);
186 }
187 util_slab_destroy(&rctx->pool_transfers);
188
189 r600_release_command_buffer(&rctx->start_cs_cmd);
190
191 if (rctx->cs) {
192 rctx->ws->cs_destroy(rctx->cs);
193 }
194
195 FREE(rctx->range);
196 FREE(rctx);
197 }
198
199 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
200 {
201 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
202 struct r600_screen* rscreen = (struct r600_screen *)screen;
203
204 if (rctx == NULL)
205 return NULL;
206
207 util_slab_create(&rctx->pool_transfers,
208 sizeof(struct r600_transfer), 64,
209 UTIL_SLAB_SINGLETHREADED);
210
211 rctx->context.screen = screen;
212 rctx->context.priv = priv;
213 rctx->context.destroy = r600_destroy_context;
214 rctx->context.flush = r600_flush_from_st;
215
216 /* Easy accessing of screen/winsys. */
217 rctx->screen = rscreen;
218 rctx->ws = rscreen->ws;
219 rctx->family = rscreen->family;
220 rctx->chip_class = rscreen->chip_class;
221 rctx->keep_tiling_flags = rscreen->info.drm_minor >= 12;
222
223 LIST_INITHEAD(&rctx->active_timer_queries);
224 LIST_INITHEAD(&rctx->active_nontimer_queries);
225 LIST_INITHEAD(&rctx->dirty);
226 LIST_INITHEAD(&rctx->enable_list);
227
228 rctx->range = CALLOC(NUM_RANGES, sizeof(struct r600_range));
229 if (!rctx->range)
230 goto fail;
231
232 r600_init_blit_functions(rctx);
233 r600_init_query_functions(rctx);
234 r600_init_context_resource_functions(rctx);
235 r600_init_surface_functions(rctx);
236
237
238 rctx->context.create_video_decoder = vl_create_decoder;
239 rctx->context.create_video_buffer = vl_video_buffer_create;
240
241 r600_init_common_state_functions(rctx);
242
243 switch (rctx->chip_class) {
244 case R600:
245 case R700:
246 r600_init_state_functions(rctx);
247 r600_init_atom_start_cs(rctx);
248 if (r600_context_init(rctx))
249 goto fail;
250 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
251 rctx->custom_blend_resolve = rctx->chip_class == R700 ? r700_create_resolve_blend(rctx)
252 : r600_create_resolve_blend(rctx);
253 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
254 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
255 rctx->family == CHIP_RV620 ||
256 rctx->family == CHIP_RS780 ||
257 rctx->family == CHIP_RS880 ||
258 rctx->family == CHIP_RV710);
259 break;
260 case EVERGREEN:
261 case CAYMAN:
262 evergreen_init_state_functions(rctx);
263 evergreen_init_atom_start_cs(rctx);
264 evergreen_init_atom_start_compute_cs(rctx);
265 if (evergreen_context_init(rctx))
266 goto fail;
267 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
268 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
269 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
270 rctx->custom_blend_fmask_decompress = evergreen_create_fmask_decompress_blend(rctx);
271 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
272 rctx->family == CHIP_PALM ||
273 rctx->family == CHIP_SUMO ||
274 rctx->family == CHIP_SUMO2 ||
275 rctx->family == CHIP_CAICOS ||
276 rctx->family == CHIP_CAYMAN ||
277 rctx->family == CHIP_ARUBA);
278 break;
279 default:
280 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
281 goto fail;
282 }
283
284 rctx->cs = rctx->ws->cs_create(rctx->ws);
285 rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
286
287 rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
288 PIPE_BIND_INDEX_BUFFER |
289 PIPE_BIND_CONSTANT_BUFFER);
290 if (!rctx->uploader)
291 goto fail;
292
293 rctx->blitter = util_blitter_create(&rctx->context);
294 if (rctx->blitter == NULL)
295 goto fail;
296 util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
297 rctx->blitter->draw_rectangle = r600_draw_rectangle;
298
299 r600_begin_new_cs(rctx);
300 r600_get_backend_mask(rctx); /* this emits commands and must be last */
301
302 rctx->dummy_pixel_shader =
303 util_make_fragment_cloneinput_shader(&rctx->context, 0,
304 TGSI_SEMANTIC_GENERIC,
305 TGSI_INTERPOLATE_CONSTANT);
306 rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
307
308 return &rctx->context;
309
310 fail:
311 r600_destroy_context(&rctx->context);
312 return NULL;
313 }
314
315 /*
316 * pipe_screen
317 */
318 static const char* r600_get_vendor(struct pipe_screen* pscreen)
319 {
320 return "X.Org";
321 }
322
323 static const char *r600_get_family_name(enum radeon_family family)
324 {
325 switch(family) {
326 case CHIP_R600: return "AMD R600";
327 case CHIP_RV610: return "AMD RV610";
328 case CHIP_RV630: return "AMD RV630";
329 case CHIP_RV670: return "AMD RV670";
330 case CHIP_RV620: return "AMD RV620";
331 case CHIP_RV635: return "AMD RV635";
332 case CHIP_RS780: return "AMD RS780";
333 case CHIP_RS880: return "AMD RS880";
334 case CHIP_RV770: return "AMD RV770";
335 case CHIP_RV730: return "AMD RV730";
336 case CHIP_RV710: return "AMD RV710";
337 case CHIP_RV740: return "AMD RV740";
338 case CHIP_CEDAR: return "AMD CEDAR";
339 case CHIP_REDWOOD: return "AMD REDWOOD";
340 case CHIP_JUNIPER: return "AMD JUNIPER";
341 case CHIP_CYPRESS: return "AMD CYPRESS";
342 case CHIP_HEMLOCK: return "AMD HEMLOCK";
343 case CHIP_PALM: return "AMD PALM";
344 case CHIP_SUMO: return "AMD SUMO";
345 case CHIP_SUMO2: return "AMD SUMO2";
346 case CHIP_BARTS: return "AMD BARTS";
347 case CHIP_TURKS: return "AMD TURKS";
348 case CHIP_CAICOS: return "AMD CAICOS";
349 case CHIP_CAYMAN: return "AMD CAYMAN";
350 case CHIP_ARUBA: return "AMD ARUBA";
351 default: return "AMD unknown";
352 }
353 }
354
355 static const char* r600_get_name(struct pipe_screen* pscreen)
356 {
357 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
358
359 return r600_get_family_name(rscreen->family);
360 }
361
362 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
363 {
364 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
365 enum radeon_family family = rscreen->family;
366
367 switch (param) {
368 /* Supported features (boolean caps). */
369 case PIPE_CAP_NPOT_TEXTURES:
370 case PIPE_CAP_TWO_SIDED_STENCIL:
371 case PIPE_CAP_ANISOTROPIC_FILTER:
372 case PIPE_CAP_POINT_SPRITE:
373 case PIPE_CAP_OCCLUSION_QUERY:
374 case PIPE_CAP_TEXTURE_SHADOW_MAP:
375 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
376 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
377 case PIPE_CAP_TEXTURE_SWIZZLE:
378 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
379 case PIPE_CAP_DEPTH_CLIP_DISABLE:
380 case PIPE_CAP_SHADER_STENCIL_EXPORT:
381 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
382 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
383 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
384 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
385 case PIPE_CAP_SM3:
386 case PIPE_CAP_SEAMLESS_CUBE_MAP:
387 case PIPE_CAP_PRIMITIVE_RESTART:
388 case PIPE_CAP_CONDITIONAL_RENDER:
389 case PIPE_CAP_TEXTURE_BARRIER:
390 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
391 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
392 case PIPE_CAP_TGSI_INSTANCEID:
393 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
394 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
395 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
396 case PIPE_CAP_USER_INDEX_BUFFERS:
397 case PIPE_CAP_USER_CONSTANT_BUFFERS:
398 case PIPE_CAP_COMPUTE:
399 case PIPE_CAP_START_INSTANCE:
400 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
401 return 1;
402
403 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
404 return 64;
405
406 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
407 return 256;
408
409 case PIPE_CAP_GLSL_FEATURE_LEVEL:
410 return 130;
411
412 case PIPE_CAP_TEXTURE_MULTISAMPLE:
413 return rscreen->msaa_texture_support != MSAA_TEXTURE_SAMPLE_ZERO;
414
415 /* Supported except the original R600. */
416 case PIPE_CAP_INDEP_BLEND_ENABLE:
417 case PIPE_CAP_INDEP_BLEND_FUNC:
418 /* R600 doesn't support per-MRT blends */
419 return family == CHIP_R600 ? 0 : 1;
420
421 /* Supported on Evergreen. */
422 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
423 return family >= CHIP_CEDAR ? 1 : 0;
424
425 /* Unsupported features. */
426 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
427 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
428 case PIPE_CAP_SCALED_RESOLVE:
429 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
430 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
431 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
432 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
433 case PIPE_CAP_USER_VERTEX_BUFFERS:
434 return 0;
435
436 /* Stream output. */
437 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
438 return rscreen->has_streamout ? 4 : 0;
439 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
440 return rscreen->has_streamout ? 1 : 0;
441 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
442 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
443 return 32*4;
444
445 /* Texturing. */
446 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
447 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
448 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
449 if (family >= CHIP_CEDAR)
450 return 15;
451 else
452 return 14;
453 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
454 return rscreen->info.drm_minor >= 9 ?
455 (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
456 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
457 return 32;
458
459 /* Render targets. */
460 case PIPE_CAP_MAX_RENDER_TARGETS:
461 /* XXX some r6xx are buggy and can only do 4 */
462 return 8;
463
464 /* Timer queries, present when the clock frequency is non zero. */
465 case PIPE_CAP_TIMER_QUERY:
466 return rscreen->info.r600_clock_crystal_freq != 0;
467 case PIPE_CAP_QUERY_TIMESTAMP:
468 return rscreen->info.drm_minor >= 20 &&
469 rscreen->info.r600_clock_crystal_freq != 0;
470
471 case PIPE_CAP_MIN_TEXEL_OFFSET:
472 return -8;
473
474 case PIPE_CAP_MAX_TEXEL_OFFSET:
475 return 7;
476 }
477 return 0;
478 }
479
480 static float r600_get_paramf(struct pipe_screen* pscreen,
481 enum pipe_capf param)
482 {
483 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
484 enum radeon_family family = rscreen->family;
485
486 switch (param) {
487 case PIPE_CAPF_MAX_LINE_WIDTH:
488 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
489 case PIPE_CAPF_MAX_POINT_WIDTH:
490 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
491 if (family >= CHIP_CEDAR)
492 return 16384.0f;
493 else
494 return 8192.0f;
495 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
496 return 16.0f;
497 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
498 return 16.0f;
499 case PIPE_CAPF_GUARD_BAND_LEFT:
500 case PIPE_CAPF_GUARD_BAND_TOP:
501 case PIPE_CAPF_GUARD_BAND_RIGHT:
502 case PIPE_CAPF_GUARD_BAND_BOTTOM:
503 return 0.0f;
504 }
505 return 0.0f;
506 }
507
508 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
509 {
510 switch(shader)
511 {
512 case PIPE_SHADER_FRAGMENT:
513 case PIPE_SHADER_VERTEX:
514 case PIPE_SHADER_COMPUTE:
515 break;
516 case PIPE_SHADER_GEOMETRY:
517 /* XXX: support and enable geometry programs */
518 return 0;
519 default:
520 /* XXX: support tessellation on Evergreen */
521 return 0;
522 }
523
524 /* XXX: all these should be fixed, since r600 surely supports much more! */
525 switch (param) {
526 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
527 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
528 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
529 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
530 return 16384;
531 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
532 return 8; /* XXX */
533 case PIPE_SHADER_CAP_MAX_INPUTS:
534 return 32;
535 case PIPE_SHADER_CAP_MAX_TEMPS:
536 return 256; /* Max native temporaries. */
537 case PIPE_SHADER_CAP_MAX_ADDRS:
538 /* XXX Isn't this equal to TEMPS? */
539 return 1; /* Max native address registers */
540 case PIPE_SHADER_CAP_MAX_CONSTS:
541 return R600_MAX_CONST_BUFFER_SIZE;
542 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
543 return R600_MAX_CONST_BUFFERS-1;
544 case PIPE_SHADER_CAP_MAX_PREDS:
545 return 0; /* nothing uses this */
546 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
547 return 1;
548 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
549 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
550 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
551 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
552 return 1;
553 case PIPE_SHADER_CAP_SUBROUTINES:
554 return 0;
555 case PIPE_SHADER_CAP_INTEGERS:
556 return 1;
557 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
558 return 16;
559 case PIPE_SHADER_CAP_PREFERRED_IR:
560 if (shader == PIPE_SHADER_COMPUTE) {
561 return PIPE_SHADER_IR_LLVM;
562 } else {
563 return PIPE_SHADER_IR_TGSI;
564 }
565 }
566 return 0;
567 }
568
569 static int r600_get_video_param(struct pipe_screen *screen,
570 enum pipe_video_profile profile,
571 enum pipe_video_cap param)
572 {
573 switch (param) {
574 case PIPE_VIDEO_CAP_SUPPORTED:
575 return vl_profile_supported(screen, profile);
576 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
577 return 1;
578 case PIPE_VIDEO_CAP_MAX_WIDTH:
579 case PIPE_VIDEO_CAP_MAX_HEIGHT:
580 return vl_video_buffer_max_size(screen);
581 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
582 return PIPE_FORMAT_NV12;
583 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
584 return false;
585 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
586 return false;
587 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
588 return true;
589 default:
590 return 0;
591 }
592 }
593
594 static int r600_get_compute_param(struct pipe_screen *screen,
595 enum pipe_compute_cap param,
596 void *ret)
597 {
598 //TODO: select these params by asic
599 switch (param) {
600 case PIPE_COMPUTE_CAP_IR_TARGET:
601 if (ret) {
602 strcpy(ret, "r600--");
603 }
604 return 7 * sizeof(char);
605
606 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
607 if (ret) {
608 uint64_t * grid_dimension = ret;
609 grid_dimension[0] = 3;
610 }
611 return 1 * sizeof(uint64_t);
612
613 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
614 if (ret) {
615 uint64_t * grid_size = ret;
616 grid_size[0] = 65535;
617 grid_size[1] = 65535;
618 grid_size[2] = 1;
619 }
620 return 3 * sizeof(uint64_t) ;
621
622 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
623 if (ret) {
624 uint64_t * block_size = ret;
625 block_size[0] = 256;
626 block_size[1] = 256;
627 block_size[2] = 256;
628 }
629 return 3 * sizeof(uint64_t);
630
631 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
632 if (ret) {
633 uint64_t * max_threads_per_block = ret;
634 *max_threads_per_block = 256;
635 }
636 return sizeof(uint64_t);
637
638 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
639 if (ret) {
640 uint64_t * max_global_size = ret;
641 /* XXX: This is what the proprietary driver reports, we
642 * may want to use a different value. */
643 *max_global_size = 201326592;
644 }
645 return sizeof(uint64_t);
646
647 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
648 if (ret) {
649 uint64_t * max_input_size = ret;
650 *max_input_size = 1024;
651 }
652 return sizeof(uint64_t);
653
654 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
655 if (ret) {
656 uint64_t * max_local_size = ret;
657 /* XXX: This is what the proprietary driver reports, we
658 * may want to use a different value. */
659 *max_local_size = 32768;
660 }
661 return sizeof(uint64_t);
662
663 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
664 if (ret) {
665 uint64_t max_global_size;
666 uint64_t * max_mem_alloc_size = ret;
667 r600_get_compute_param(screen,
668 PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
669 &max_global_size);
670 /* OpenCL requres this value be at least
671 * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
672 * I'm really not sure what value to report here, but
673 * MAX_GLOBAL_SIZE / 4 seems resonable.
674 */
675 *max_mem_alloc_size = max_global_size / 4;
676 }
677 return sizeof(uint64_t);
678
679 default:
680 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
681 return 0;
682 }
683 }
684
685 static void r600_destroy_screen(struct pipe_screen* pscreen)
686 {
687 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
688
689 if (rscreen == NULL)
690 return;
691
692 if (rscreen->global_pool) {
693 compute_memory_pool_delete(rscreen->global_pool);
694 }
695
696 if (rscreen->fences.bo) {
697 struct r600_fence_block *entry, *tmp;
698
699 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
700 LIST_DEL(&entry->head);
701 FREE(entry);
702 }
703
704 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
705 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
706 }
707 pipe_mutex_destroy(rscreen->fences.mutex);
708
709 rscreen->ws->destroy(rscreen->ws);
710 FREE(rscreen);
711 }
712
713 static void r600_fence_reference(struct pipe_screen *pscreen,
714 struct pipe_fence_handle **ptr,
715 struct pipe_fence_handle *fence)
716 {
717 struct r600_fence **oldf = (struct r600_fence**)ptr;
718 struct r600_fence *newf = (struct r600_fence*)fence;
719
720 if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
721 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
722 pipe_mutex_lock(rscreen->fences.mutex);
723 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
724 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
725 pipe_mutex_unlock(rscreen->fences.mutex);
726 }
727
728 *ptr = fence;
729 }
730
731 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
732 struct pipe_fence_handle *fence)
733 {
734 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
735 struct r600_fence *rfence = (struct r600_fence*)fence;
736
737 return rscreen->fences.data[rfence->index];
738 }
739
740 static boolean r600_fence_finish(struct pipe_screen *pscreen,
741 struct pipe_fence_handle *fence,
742 uint64_t timeout)
743 {
744 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
745 struct r600_fence *rfence = (struct r600_fence*)fence;
746 int64_t start_time = 0;
747 unsigned spins = 0;
748
749 if (timeout != PIPE_TIMEOUT_INFINITE) {
750 start_time = os_time_get();
751
752 /* Convert to microseconds. */
753 timeout /= 1000;
754 }
755
756 while (rscreen->fences.data[rfence->index] == 0) {
757 /* Special-case infinite timeout - wait for the dummy BO to become idle */
758 if (timeout == PIPE_TIMEOUT_INFINITE) {
759 rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
760 break;
761 }
762
763 /* The dummy BO will be busy until the CS including the fence has completed, or
764 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
765 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
766 break;
767
768 if (++spins % 256)
769 continue;
770 #ifdef PIPE_OS_UNIX
771 sched_yield();
772 #else
773 os_time_sleep(10);
774 #endif
775 if (timeout != PIPE_TIMEOUT_INFINITE &&
776 os_time_get() - start_time >= timeout) {
777 break;
778 }
779 }
780
781 return rscreen->fences.data[rfence->index] != 0;
782 }
783
784 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
785 {
786 switch ((tiling_config & 0xe) >> 1) {
787 case 0:
788 rscreen->tiling_info.num_channels = 1;
789 break;
790 case 1:
791 rscreen->tiling_info.num_channels = 2;
792 break;
793 case 2:
794 rscreen->tiling_info.num_channels = 4;
795 break;
796 case 3:
797 rscreen->tiling_info.num_channels = 8;
798 break;
799 default:
800 return -EINVAL;
801 }
802
803 switch ((tiling_config & 0x30) >> 4) {
804 case 0:
805 rscreen->tiling_info.num_banks = 4;
806 break;
807 case 1:
808 rscreen->tiling_info.num_banks = 8;
809 break;
810 default:
811 return -EINVAL;
812
813 }
814 switch ((tiling_config & 0xc0) >> 6) {
815 case 0:
816 rscreen->tiling_info.group_bytes = 256;
817 break;
818 case 1:
819 rscreen->tiling_info.group_bytes = 512;
820 break;
821 default:
822 return -EINVAL;
823 }
824 return 0;
825 }
826
827 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
828 {
829 switch (tiling_config & 0xf) {
830 case 0:
831 rscreen->tiling_info.num_channels = 1;
832 break;
833 case 1:
834 rscreen->tiling_info.num_channels = 2;
835 break;
836 case 2:
837 rscreen->tiling_info.num_channels = 4;
838 break;
839 case 3:
840 rscreen->tiling_info.num_channels = 8;
841 break;
842 default:
843 return -EINVAL;
844 }
845
846 switch ((tiling_config & 0xf0) >> 4) {
847 case 0:
848 rscreen->tiling_info.num_banks = 4;
849 break;
850 case 1:
851 rscreen->tiling_info.num_banks = 8;
852 break;
853 case 2:
854 rscreen->tiling_info.num_banks = 16;
855 break;
856 default:
857 return -EINVAL;
858 }
859
860 switch ((tiling_config & 0xf00) >> 8) {
861 case 0:
862 rscreen->tiling_info.group_bytes = 256;
863 break;
864 case 1:
865 rscreen->tiling_info.group_bytes = 512;
866 break;
867 default:
868 return -EINVAL;
869 }
870 return 0;
871 }
872
873 static int r600_init_tiling(struct r600_screen *rscreen)
874 {
875 uint32_t tiling_config = rscreen->info.r600_tiling_config;
876
877 /* set default group bytes, overridden by tiling info ioctl */
878 if (rscreen->chip_class <= R700) {
879 rscreen->tiling_info.group_bytes = 256;
880 } else {
881 rscreen->tiling_info.group_bytes = 512;
882 }
883
884 if (!tiling_config)
885 return 0;
886
887 if (rscreen->chip_class <= R700) {
888 return r600_interpret_tiling(rscreen, tiling_config);
889 } else {
890 return evergreen_interpret_tiling(rscreen, tiling_config);
891 }
892 }
893
894 static unsigned radeon_family_from_device(unsigned device)
895 {
896 switch (device) {
897 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
898 #include "pci_ids/r600_pci_ids.h"
899 #undef CHIPSET
900 default:
901 return CHIP_UNKNOWN;
902 }
903 }
904
905 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
906 {
907 struct r600_screen *rscreen = (struct r600_screen*)screen;
908
909 return 1000000 * rscreen->ws->query_timestamp(rscreen->ws) /
910 rscreen->info.r600_clock_crystal_freq;
911 }
912
913 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
914 {
915 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
916
917 if (rscreen == NULL) {
918 return NULL;
919 }
920
921 rscreen->ws = ws;
922 ws->query_info(ws, &rscreen->info);
923
924 rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
925 if (rscreen->family == CHIP_UNKNOWN) {
926 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
927 FREE(rscreen);
928 return NULL;
929 }
930
931 /* setup class */
932 if (rscreen->family >= CHIP_CAYMAN) {
933 rscreen->chip_class = CAYMAN;
934 } else if (rscreen->family >= CHIP_CEDAR) {
935 rscreen->chip_class = EVERGREEN;
936 } else if (rscreen->family >= CHIP_RV770) {
937 rscreen->chip_class = R700;
938 } else {
939 rscreen->chip_class = R600;
940 }
941
942 /* Figure out streamout kernel support. */
943 switch (rscreen->chip_class) {
944 case R600:
945 if (rscreen->family < CHIP_RS780) {
946 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
947 } else {
948 rscreen->has_streamout = rscreen->info.drm_minor >= 23;
949 }
950 break;
951 case R700:
952 rscreen->has_streamout = rscreen->info.drm_minor >= 17;
953 break;
954 case EVERGREEN:
955 case CAYMAN:
956 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
957 break;
958 }
959
960 /* MSAA support. */
961 switch (rscreen->chip_class) {
962 case R600:
963 case R700:
964 rscreen->has_msaa = rscreen->info.drm_minor >= 22;
965 rscreen->msaa_texture_support = MSAA_TEXTURE_DECOMPRESSED;
966 break;
967 case EVERGREEN:
968 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
969 rscreen->msaa_texture_support =
970 rscreen->info.drm_minor >= 24 ? MSAA_TEXTURE_COMPRESSED :
971 MSAA_TEXTURE_DECOMPRESSED;
972 break;
973 case CAYMAN:
974 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
975 /* We should be able to read compressed MSAA textures, but it doesn't work. */
976 rscreen->msaa_texture_support = MSAA_TEXTURE_SAMPLE_ZERO;
977 break;
978 }
979
980 if (r600_init_tiling(rscreen)) {
981 FREE(rscreen);
982 return NULL;
983 }
984
985 rscreen->screen.destroy = r600_destroy_screen;
986 rscreen->screen.get_name = r600_get_name;
987 rscreen->screen.get_vendor = r600_get_vendor;
988 rscreen->screen.get_param = r600_get_param;
989 rscreen->screen.get_shader_param = r600_get_shader_param;
990 rscreen->screen.get_paramf = r600_get_paramf;
991 rscreen->screen.get_video_param = r600_get_video_param;
992 rscreen->screen.get_compute_param = r600_get_compute_param;
993 rscreen->screen.get_timestamp = r600_get_timestamp;
994
995 if (rscreen->chip_class >= EVERGREEN) {
996 rscreen->screen.is_format_supported = evergreen_is_format_supported;
997 } else {
998 rscreen->screen.is_format_supported = r600_is_format_supported;
999 }
1000 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
1001 rscreen->screen.context_create = r600_create_context;
1002 rscreen->screen.fence_reference = r600_fence_reference;
1003 rscreen->screen.fence_signalled = r600_fence_signalled;
1004 rscreen->screen.fence_finish = r600_fence_finish;
1005 r600_init_screen_resource_functions(&rscreen->screen);
1006
1007 util_format_s3tc_init();
1008
1009 rscreen->fences.bo = NULL;
1010 rscreen->fences.data = NULL;
1011 rscreen->fences.next_index = 0;
1012 LIST_INITHEAD(&rscreen->fences.pool);
1013 LIST_INITHEAD(&rscreen->fences.blocks);
1014 pipe_mutex_init(rscreen->fences.mutex);
1015
1016 rscreen->global_pool = compute_memory_pool_new(rscreen);
1017
1018 return &rscreen->screen;
1019 }