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[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_pipe.h"
24 #include "r600_public.h"
25
26 #include <errno.h>
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_blitter.h"
29 #include "util/u_format_s3tc.h"
30 #include "util/u_simple_shaders.h"
31 #include "util/u_upload_mgr.h"
32 #include "vl/vl_decoder.h"
33 #include "vl/vl_video_buffer.h"
34 #include "os/os_time.h"
35
36 /*
37 * pipe_context
38 */
39 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
40 {
41 struct r600_screen *rscreen = rctx->screen;
42 struct r600_fence *fence = NULL;
43
44 pipe_mutex_lock(rscreen->fences.mutex);
45
46 if (!rscreen->fences.bo) {
47 /* Create the shared buffer object */
48 rscreen->fences.bo = (struct r600_resource*)
49 pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
50 PIPE_USAGE_STAGING, 4096);
51 if (!rscreen->fences.bo) {
52 R600_ERR("r600: failed to create bo for fence objects\n");
53 goto out;
54 }
55 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf,
56 rctx->cs,
57 PIPE_TRANSFER_READ_WRITE);
58 }
59
60 if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
61 struct r600_fence *entry;
62
63 /* Try to find a freed fence that has been signalled */
64 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
65 if (rscreen->fences.data[entry->index] != 0) {
66 LIST_DELINIT(&entry->head);
67 fence = entry;
68 break;
69 }
70 }
71 }
72
73 if (!fence) {
74 /* Allocate a new fence */
75 struct r600_fence_block *block;
76 unsigned index;
77
78 if ((rscreen->fences.next_index + 1) >= 1024) {
79 R600_ERR("r600: too many concurrent fences\n");
80 goto out;
81 }
82
83 index = rscreen->fences.next_index++;
84
85 if (!(index % FENCE_BLOCK_SIZE)) {
86 /* Allocate a new block */
87 block = CALLOC_STRUCT(r600_fence_block);
88 if (block == NULL)
89 goto out;
90
91 LIST_ADD(&block->head, &rscreen->fences.blocks);
92 } else {
93 block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
94 }
95
96 fence = &block->fences[index % FENCE_BLOCK_SIZE];
97 fence->index = index;
98 }
99
100 pipe_reference_init(&fence->reference, 1);
101
102 rscreen->fences.data[fence->index] = 0;
103 r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
104
105 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
106 fence->sleep_bo = (struct r600_resource*)
107 pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
108 PIPE_USAGE_STAGING, 1);
109 /* Add the fence as a dummy relocation. */
110 r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
111
112 out:
113 pipe_mutex_unlock(rscreen->fences.mutex);
114 return fence;
115 }
116
117
118 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
119 unsigned flags)
120 {
121 struct r600_context *rctx = (struct r600_context *)ctx;
122 struct r600_fence **rfence = (struct r600_fence**)fence;
123 struct pipe_query *render_cond = NULL;
124 unsigned render_cond_mode = 0;
125
126 if (rfence)
127 *rfence = r600_create_fence(rctx);
128
129 /* Disable render condition. */
130 if (rctx->current_render_cond) {
131 render_cond = rctx->current_render_cond;
132 render_cond_mode = rctx->current_render_cond_mode;
133 ctx->render_condition(ctx, NULL, 0);
134 }
135
136 r600_context_flush(rctx, flags);
137
138 /* Re-enable render condition. */
139 if (render_cond) {
140 ctx->render_condition(ctx, render_cond, render_cond_mode);
141 }
142 }
143
144 static void r600_flush_from_st(struct pipe_context *ctx,
145 struct pipe_fence_handle **fence)
146 {
147 r600_flush(ctx, fence, 0);
148 }
149
150 static void r600_flush_from_winsys(void *ctx, unsigned flags)
151 {
152 r600_flush((struct pipe_context*)ctx, NULL, flags);
153 }
154
155 static void r600_destroy_context(struct pipe_context *context)
156 {
157 struct r600_context *rctx = (struct r600_context *)context;
158
159 if (rctx->dummy_pixel_shader) {
160 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
161 }
162 if (rctx->custom_dsa_flush) {
163 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
164 }
165 if (rctx->custom_blend_resolve) {
166 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve);
167 }
168 util_unreference_framebuffer_state(&rctx->framebuffer);
169
170 r600_context_fini(rctx);
171
172 if (rctx->blitter) {
173 util_blitter_destroy(rctx->blitter);
174 }
175 for (int i = 0; i < R600_PIPE_NSTATES; i++) {
176 free(rctx->states[i]);
177 }
178
179 if (rctx->uploader) {
180 u_upload_destroy(rctx->uploader);
181 }
182 util_slab_destroy(&rctx->pool_transfers);
183
184 r600_release_command_buffer(&rctx->start_cs_cmd);
185
186 if (rctx->cs) {
187 rctx->ws->cs_destroy(rctx->cs);
188 }
189
190 FREE(rctx->range);
191 FREE(rctx);
192 }
193
194 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
195 {
196 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
197 struct r600_screen* rscreen = (struct r600_screen *)screen;
198
199 if (rctx == NULL)
200 return NULL;
201
202 util_slab_create(&rctx->pool_transfers,
203 sizeof(struct r600_transfer), 64,
204 UTIL_SLAB_SINGLETHREADED);
205
206 rctx->context.screen = screen;
207 rctx->context.priv = priv;
208 rctx->context.destroy = r600_destroy_context;
209 rctx->context.flush = r600_flush_from_st;
210
211 /* Easy accessing of screen/winsys. */
212 rctx->screen = rscreen;
213 rctx->ws = rscreen->ws;
214 rctx->family = rscreen->family;
215 rctx->chip_class = rscreen->chip_class;
216
217 LIST_INITHEAD(&rctx->dirty_states);
218 LIST_INITHEAD(&rctx->active_timer_queries);
219 LIST_INITHEAD(&rctx->active_nontimer_queries);
220 LIST_INITHEAD(&rctx->dirty);
221 LIST_INITHEAD(&rctx->enable_list);
222
223 rctx->range = CALLOC(NUM_RANGES, sizeof(struct r600_range));
224 if (!rctx->range)
225 goto fail;
226
227 r600_init_blit_functions(rctx);
228 r600_init_query_functions(rctx);
229 r600_init_context_resource_functions(rctx);
230 r600_init_surface_functions(rctx);
231 rctx->context.draw_vbo = r600_draw_vbo;
232
233 rctx->context.create_video_decoder = vl_create_decoder;
234 rctx->context.create_video_buffer = vl_video_buffer_create;
235
236 r600_init_common_atoms(rctx);
237
238 switch (rctx->chip_class) {
239 case R600:
240 case R700:
241 r600_init_state_functions(rctx);
242 r600_init_atom_start_cs(rctx);
243 if (r600_context_init(rctx))
244 goto fail;
245 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
246 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
247 rctx->family == CHIP_RV620 ||
248 rctx->family == CHIP_RS780 ||
249 rctx->family == CHIP_RS880 ||
250 rctx->family == CHIP_RV710);
251 break;
252 case EVERGREEN:
253 case CAYMAN:
254 evergreen_init_state_functions(rctx);
255 evergreen_init_atom_start_cs(rctx);
256 evergreen_init_atom_start_compute_cs(rctx);
257 if (evergreen_context_init(rctx))
258 goto fail;
259 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
260 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
261 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
262 rctx->family == CHIP_PALM ||
263 rctx->family == CHIP_SUMO ||
264 rctx->family == CHIP_SUMO2 ||
265 rctx->family == CHIP_CAICOS ||
266 rctx->family == CHIP_CAYMAN ||
267 rctx->family == CHIP_ARUBA);
268 break;
269 default:
270 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
271 goto fail;
272 }
273
274 rctx->cs = rctx->ws->cs_create(rctx->ws);
275 rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
276 r600_emit_atom(rctx, &rctx->start_cs_cmd.atom);
277
278 rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
279 PIPE_BIND_INDEX_BUFFER |
280 PIPE_BIND_CONSTANT_BUFFER);
281 if (!rctx->uploader)
282 goto fail;
283
284 rctx->blitter = util_blitter_create(&rctx->context);
285 if (rctx->blitter == NULL)
286 goto fail;
287
288 r600_get_backend_mask(rctx); /* this emits commands and must be last */
289
290 if (rctx->chip_class == R600)
291 r600_set_max_scissor(rctx);
292
293 rctx->dummy_pixel_shader =
294 util_make_fragment_cloneinput_shader(&rctx->context, 0,
295 TGSI_SEMANTIC_GENERIC,
296 TGSI_INTERPOLATE_CONSTANT);
297 rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
298
299 return &rctx->context;
300
301 fail:
302 r600_destroy_context(&rctx->context);
303 return NULL;
304 }
305
306 /*
307 * pipe_screen
308 */
309 static const char* r600_get_vendor(struct pipe_screen* pscreen)
310 {
311 return "X.Org";
312 }
313
314 static const char *r600_get_family_name(enum radeon_family family)
315 {
316 switch(family) {
317 case CHIP_R600: return "AMD R600";
318 case CHIP_RV610: return "AMD RV610";
319 case CHIP_RV630: return "AMD RV630";
320 case CHIP_RV670: return "AMD RV670";
321 case CHIP_RV620: return "AMD RV620";
322 case CHIP_RV635: return "AMD RV635";
323 case CHIP_RS780: return "AMD RS780";
324 case CHIP_RS880: return "AMD RS880";
325 case CHIP_RV770: return "AMD RV770";
326 case CHIP_RV730: return "AMD RV730";
327 case CHIP_RV710: return "AMD RV710";
328 case CHIP_RV740: return "AMD RV740";
329 case CHIP_CEDAR: return "AMD CEDAR";
330 case CHIP_REDWOOD: return "AMD REDWOOD";
331 case CHIP_JUNIPER: return "AMD JUNIPER";
332 case CHIP_CYPRESS: return "AMD CYPRESS";
333 case CHIP_HEMLOCK: return "AMD HEMLOCK";
334 case CHIP_PALM: return "AMD PALM";
335 case CHIP_SUMO: return "AMD SUMO";
336 case CHIP_SUMO2: return "AMD SUMO2";
337 case CHIP_BARTS: return "AMD BARTS";
338 case CHIP_TURKS: return "AMD TURKS";
339 case CHIP_CAICOS: return "AMD CAICOS";
340 case CHIP_CAYMAN: return "AMD CAYMAN";
341 case CHIP_ARUBA: return "AMD ARUBA";
342 default: return "AMD unknown";
343 }
344 }
345
346 static const char* r600_get_name(struct pipe_screen* pscreen)
347 {
348 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
349
350 return r600_get_family_name(rscreen->family);
351 }
352
353 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
354 {
355 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
356 enum radeon_family family = rscreen->family;
357
358 switch (param) {
359 /* Supported features (boolean caps). */
360 case PIPE_CAP_NPOT_TEXTURES:
361 case PIPE_CAP_TWO_SIDED_STENCIL:
362 case PIPE_CAP_ANISOTROPIC_FILTER:
363 case PIPE_CAP_POINT_SPRITE:
364 case PIPE_CAP_OCCLUSION_QUERY:
365 case PIPE_CAP_TEXTURE_SHADOW_MAP:
366 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
367 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
368 case PIPE_CAP_TEXTURE_SWIZZLE:
369 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
370 case PIPE_CAP_DEPTH_CLIP_DISABLE:
371 case PIPE_CAP_SHADER_STENCIL_EXPORT:
372 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
373 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
374 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
375 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
376 case PIPE_CAP_SM3:
377 case PIPE_CAP_SEAMLESS_CUBE_MAP:
378 case PIPE_CAP_PRIMITIVE_RESTART:
379 case PIPE_CAP_CONDITIONAL_RENDER:
380 case PIPE_CAP_TEXTURE_BARRIER:
381 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
382 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
383 case PIPE_CAP_TGSI_INSTANCEID:
384 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
385 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
386 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
387 case PIPE_CAP_USER_INDEX_BUFFERS:
388 case PIPE_CAP_USER_CONSTANT_BUFFERS:
389 case PIPE_CAP_COMPUTE:
390 case PIPE_CAP_START_INSTANCE:
391 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
392 return 1;
393
394 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
395 return 256;
396
397 case PIPE_CAP_GLSL_FEATURE_LEVEL:
398 return 130;
399
400 /* Supported except the original R600. */
401 case PIPE_CAP_INDEP_BLEND_ENABLE:
402 case PIPE_CAP_INDEP_BLEND_FUNC:
403 /* R600 doesn't support per-MRT blends */
404 return family == CHIP_R600 ? 0 : 1;
405
406 /* Supported on Evergreen. */
407 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
408 return family >= CHIP_CEDAR ? 1 : 0;
409
410 /* Unsupported features. */
411 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
412 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
413 case PIPE_CAP_SCALED_RESOLVE:
414 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
415 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
416 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
417 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
418 case PIPE_CAP_USER_VERTEX_BUFFERS:
419 return 0;
420
421 /* Stream output. */
422 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
423 return rscreen->has_streamout ? 4 : 0;
424 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
425 return rscreen->has_streamout ? 1 : 0;
426 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
427 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
428 return 16*4;
429
430 /* Texturing. */
431 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
432 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
433 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
434 if (family >= CHIP_CEDAR)
435 return 15;
436 else
437 return 14;
438 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
439 return rscreen->info.drm_minor >= 9 ?
440 (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
441 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
442 return 32;
443
444 /* Render targets. */
445 case PIPE_CAP_MAX_RENDER_TARGETS:
446 /* XXX some r6xx are buggy and can only do 4 */
447 return 8;
448
449 /* Timer queries, present when the clock frequency is non zero. */
450 case PIPE_CAP_TIMER_QUERY:
451 return rscreen->info.r600_clock_crystal_freq != 0;
452 case PIPE_CAP_QUERY_TIMESTAMP:
453 return rscreen->info.drm_minor >= 20 &&
454 rscreen->info.r600_clock_crystal_freq != 0;
455
456 case PIPE_CAP_MIN_TEXEL_OFFSET:
457 return -8;
458
459 case PIPE_CAP_MAX_TEXEL_OFFSET:
460 return 7;
461 }
462 return 0;
463 }
464
465 static float r600_get_paramf(struct pipe_screen* pscreen,
466 enum pipe_capf param)
467 {
468 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
469 enum radeon_family family = rscreen->family;
470
471 switch (param) {
472 case PIPE_CAPF_MAX_LINE_WIDTH:
473 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
474 case PIPE_CAPF_MAX_POINT_WIDTH:
475 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
476 if (family >= CHIP_CEDAR)
477 return 16384.0f;
478 else
479 return 8192.0f;
480 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
481 return 16.0f;
482 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
483 return 16.0f;
484 case PIPE_CAPF_GUARD_BAND_LEFT:
485 case PIPE_CAPF_GUARD_BAND_TOP:
486 case PIPE_CAPF_GUARD_BAND_RIGHT:
487 case PIPE_CAPF_GUARD_BAND_BOTTOM:
488 return 0.0f;
489 }
490 return 0.0f;
491 }
492
493 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
494 {
495 switch(shader)
496 {
497 case PIPE_SHADER_FRAGMENT:
498 case PIPE_SHADER_VERTEX:
499 case PIPE_SHADER_COMPUTE:
500 break;
501 case PIPE_SHADER_GEOMETRY:
502 /* XXX: support and enable geometry programs */
503 return 0;
504 default:
505 /* XXX: support tessellation on Evergreen */
506 return 0;
507 }
508
509 /* XXX: all these should be fixed, since r600 surely supports much more! */
510 switch (param) {
511 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
512 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
513 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
514 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
515 return 16384;
516 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
517 return 8; /* XXX */
518 case PIPE_SHADER_CAP_MAX_INPUTS:
519 if(shader == PIPE_SHADER_FRAGMENT)
520 return 34;
521 else
522 return 32;
523 case PIPE_SHADER_CAP_MAX_TEMPS:
524 return 256; /* Max native temporaries. */
525 case PIPE_SHADER_CAP_MAX_ADDRS:
526 /* XXX Isn't this equal to TEMPS? */
527 return 1; /* Max native address registers */
528 case PIPE_SHADER_CAP_MAX_CONSTS:
529 return R600_MAX_CONST_BUFFER_SIZE;
530 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
531 return R600_MAX_CONST_BUFFERS-1;
532 case PIPE_SHADER_CAP_MAX_PREDS:
533 return 0; /* nothing uses this */
534 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
535 return 1;
536 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
537 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
538 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
539 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
540 return 1;
541 case PIPE_SHADER_CAP_SUBROUTINES:
542 return 0;
543 case PIPE_SHADER_CAP_INTEGERS:
544 return 1;
545 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
546 return 16;
547 case PIPE_SHADER_CAP_PREFERRED_IR:
548 if (shader == PIPE_SHADER_COMPUTE) {
549 return PIPE_SHADER_IR_LLVM;
550 } else {
551 return PIPE_SHADER_IR_TGSI;
552 }
553 }
554 return 0;
555 }
556
557 static int r600_get_video_param(struct pipe_screen *screen,
558 enum pipe_video_profile profile,
559 enum pipe_video_cap param)
560 {
561 switch (param) {
562 case PIPE_VIDEO_CAP_SUPPORTED:
563 return vl_profile_supported(screen, profile);
564 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
565 return 1;
566 case PIPE_VIDEO_CAP_MAX_WIDTH:
567 case PIPE_VIDEO_CAP_MAX_HEIGHT:
568 return vl_video_buffer_max_size(screen);
569 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
570 return PIPE_FORMAT_NV12;
571 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
572 return false;
573 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
574 return false;
575 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
576 return true;
577 default:
578 return 0;
579 }
580 }
581
582 static int r600_get_compute_param(struct pipe_screen *screen,
583 enum pipe_compute_cap param,
584 void *ret)
585 {
586 //TODO: select these params by asic
587 switch (param) {
588 case PIPE_COMPUTE_CAP_IR_TARGET:
589 if (ret) {
590 strcpy(ret, "r600--");
591 }
592 return 7 * sizeof(char);
593
594 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
595 if (ret) {
596 uint64_t * grid_dimension = ret;
597 grid_dimension[0] = 3;
598 }
599 return 1 * sizeof(uint64_t);
600
601 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
602 if (ret) {
603 uint64_t * grid_size = ret;
604 grid_size[0] = 65535;
605 grid_size[1] = 65535;
606 grid_size[2] = 1;
607 }
608 return 3 * sizeof(uint64_t) ;
609
610 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
611 if (ret) {
612 uint64_t * block_size = ret;
613 block_size[0] = 256;
614 block_size[1] = 256;
615 block_size[2] = 256;
616 }
617 return 3 * sizeof(uint64_t);
618
619 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
620 if (ret) {
621 uint64_t * max_threads_per_block = ret;
622 *max_threads_per_block = 256;
623 }
624 return sizeof(uint64_t);
625
626 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
627 if (ret) {
628 uint64_t * max_global_size = ret;
629 /* XXX: This is 64kb for now until we get the
630 * compute memory pool working correctly.
631 */
632 *max_global_size = 1024 * 16 * 4;
633 }
634 return sizeof(uint64_t);
635
636 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
637 if (ret) {
638 uint64_t * max_input_size = ret;
639 *max_input_size = 1024;
640 }
641 return sizeof(uint64_t);
642
643 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
644 if (ret) {
645 uint64_t * max_local_size = ret;
646 /* XXX: This is what the proprietary driver reports, we
647 * may want to use a different value. */
648 *max_local_size = 32768;
649 }
650 return sizeof(uint64_t);
651
652 default:
653 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
654 return 0;
655 }
656 }
657
658 static void r600_destroy_screen(struct pipe_screen* pscreen)
659 {
660 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
661
662 if (rscreen == NULL)
663 return;
664
665 if (rscreen->global_pool) {
666 compute_memory_pool_delete(rscreen->global_pool);
667 }
668
669 if (rscreen->fences.bo) {
670 struct r600_fence_block *entry, *tmp;
671
672 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
673 LIST_DEL(&entry->head);
674 FREE(entry);
675 }
676
677 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
678 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
679 }
680 pipe_mutex_destroy(rscreen->fences.mutex);
681
682 rscreen->ws->destroy(rscreen->ws);
683 FREE(rscreen);
684 }
685
686 static void r600_fence_reference(struct pipe_screen *pscreen,
687 struct pipe_fence_handle **ptr,
688 struct pipe_fence_handle *fence)
689 {
690 struct r600_fence **oldf = (struct r600_fence**)ptr;
691 struct r600_fence *newf = (struct r600_fence*)fence;
692
693 if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
694 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
695 pipe_mutex_lock(rscreen->fences.mutex);
696 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
697 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
698 pipe_mutex_unlock(rscreen->fences.mutex);
699 }
700
701 *ptr = fence;
702 }
703
704 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
705 struct pipe_fence_handle *fence)
706 {
707 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
708 struct r600_fence *rfence = (struct r600_fence*)fence;
709
710 return rscreen->fences.data[rfence->index];
711 }
712
713 static boolean r600_fence_finish(struct pipe_screen *pscreen,
714 struct pipe_fence_handle *fence,
715 uint64_t timeout)
716 {
717 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
718 struct r600_fence *rfence = (struct r600_fence*)fence;
719 int64_t start_time = 0;
720 unsigned spins = 0;
721
722 if (timeout != PIPE_TIMEOUT_INFINITE) {
723 start_time = os_time_get();
724
725 /* Convert to microseconds. */
726 timeout /= 1000;
727 }
728
729 while (rscreen->fences.data[rfence->index] == 0) {
730 /* Special-case infinite timeout - wait for the dummy BO to become idle */
731 if (timeout == PIPE_TIMEOUT_INFINITE) {
732 rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
733 break;
734 }
735
736 /* The dummy BO will be busy until the CS including the fence has completed, or
737 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
738 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
739 break;
740
741 if (++spins % 256)
742 continue;
743 #ifdef PIPE_OS_UNIX
744 sched_yield();
745 #else
746 os_time_sleep(10);
747 #endif
748 if (timeout != PIPE_TIMEOUT_INFINITE &&
749 os_time_get() - start_time >= timeout) {
750 break;
751 }
752 }
753
754 return rscreen->fences.data[rfence->index] != 0;
755 }
756
757 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
758 {
759 switch ((tiling_config & 0xe) >> 1) {
760 case 0:
761 rscreen->tiling_info.num_channels = 1;
762 break;
763 case 1:
764 rscreen->tiling_info.num_channels = 2;
765 break;
766 case 2:
767 rscreen->tiling_info.num_channels = 4;
768 break;
769 case 3:
770 rscreen->tiling_info.num_channels = 8;
771 break;
772 default:
773 return -EINVAL;
774 }
775
776 switch ((tiling_config & 0x30) >> 4) {
777 case 0:
778 rscreen->tiling_info.num_banks = 4;
779 break;
780 case 1:
781 rscreen->tiling_info.num_banks = 8;
782 break;
783 default:
784 return -EINVAL;
785
786 }
787 switch ((tiling_config & 0xc0) >> 6) {
788 case 0:
789 rscreen->tiling_info.group_bytes = 256;
790 break;
791 case 1:
792 rscreen->tiling_info.group_bytes = 512;
793 break;
794 default:
795 return -EINVAL;
796 }
797 return 0;
798 }
799
800 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
801 {
802 switch (tiling_config & 0xf) {
803 case 0:
804 rscreen->tiling_info.num_channels = 1;
805 break;
806 case 1:
807 rscreen->tiling_info.num_channels = 2;
808 break;
809 case 2:
810 rscreen->tiling_info.num_channels = 4;
811 break;
812 case 3:
813 rscreen->tiling_info.num_channels = 8;
814 break;
815 default:
816 return -EINVAL;
817 }
818
819 switch ((tiling_config & 0xf0) >> 4) {
820 case 0:
821 rscreen->tiling_info.num_banks = 4;
822 break;
823 case 1:
824 rscreen->tiling_info.num_banks = 8;
825 break;
826 case 2:
827 rscreen->tiling_info.num_banks = 16;
828 break;
829 default:
830 return -EINVAL;
831 }
832
833 switch ((tiling_config & 0xf00) >> 8) {
834 case 0:
835 rscreen->tiling_info.group_bytes = 256;
836 break;
837 case 1:
838 rscreen->tiling_info.group_bytes = 512;
839 break;
840 default:
841 return -EINVAL;
842 }
843 return 0;
844 }
845
846 static int r600_init_tiling(struct r600_screen *rscreen)
847 {
848 uint32_t tiling_config = rscreen->info.r600_tiling_config;
849
850 /* set default group bytes, overridden by tiling info ioctl */
851 if (rscreen->chip_class <= R700) {
852 rscreen->tiling_info.group_bytes = 256;
853 } else {
854 rscreen->tiling_info.group_bytes = 512;
855 }
856
857 if (!tiling_config)
858 return 0;
859
860 if (rscreen->chip_class <= R700) {
861 return r600_interpret_tiling(rscreen, tiling_config);
862 } else {
863 return evergreen_interpret_tiling(rscreen, tiling_config);
864 }
865 }
866
867 static unsigned radeon_family_from_device(unsigned device)
868 {
869 switch (device) {
870 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
871 #include "pci_ids/r600_pci_ids.h"
872 #undef CHIPSET
873 default:
874 return CHIP_UNKNOWN;
875 }
876 }
877
878 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
879 {
880 struct r600_screen *rscreen = (struct r600_screen*)screen;
881
882 return 1000000 * rscreen->ws->query_timestamp(rscreen->ws) /
883 rscreen->info.r600_clock_crystal_freq;
884 }
885
886 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
887 {
888 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
889
890 if (rscreen == NULL) {
891 return NULL;
892 }
893
894 rscreen->ws = ws;
895 ws->query_info(ws, &rscreen->info);
896
897 rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
898 if (rscreen->family == CHIP_UNKNOWN) {
899 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
900 FREE(rscreen);
901 return NULL;
902 }
903
904 /* setup class */
905 if (rscreen->family >= CHIP_CAYMAN) {
906 rscreen->chip_class = CAYMAN;
907 } else if (rscreen->family >= CHIP_CEDAR) {
908 rscreen->chip_class = EVERGREEN;
909 } else if (rscreen->family >= CHIP_RV770) {
910 rscreen->chip_class = R700;
911 } else {
912 rscreen->chip_class = R600;
913 }
914
915 /* Figure out streamout kernel support. */
916 switch (rscreen->chip_class) {
917 case R600:
918 case EVERGREEN:
919 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
920 break;
921 case R700:
922 rscreen->has_streamout = rscreen->info.drm_minor >= 17;
923 break;
924 /* TODO: Cayman */
925 default:
926 rscreen->has_streamout = debug_get_bool_option("R600_STREAMOUT", FALSE);
927 }
928
929 if (r600_init_tiling(rscreen)) {
930 FREE(rscreen);
931 return NULL;
932 }
933
934 rscreen->screen.destroy = r600_destroy_screen;
935 rscreen->screen.get_name = r600_get_name;
936 rscreen->screen.get_vendor = r600_get_vendor;
937 rscreen->screen.get_param = r600_get_param;
938 rscreen->screen.get_shader_param = r600_get_shader_param;
939 rscreen->screen.get_paramf = r600_get_paramf;
940 rscreen->screen.get_video_param = r600_get_video_param;
941 rscreen->screen.get_compute_param = r600_get_compute_param;
942 rscreen->screen.get_timestamp = r600_get_timestamp;
943
944 if (rscreen->chip_class >= EVERGREEN) {
945 rscreen->screen.is_format_supported = evergreen_is_format_supported;
946 } else {
947 rscreen->screen.is_format_supported = r600_is_format_supported;
948 }
949 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
950 rscreen->screen.context_create = r600_create_context;
951 rscreen->screen.fence_reference = r600_fence_reference;
952 rscreen->screen.fence_signalled = r600_fence_signalled;
953 rscreen->screen.fence_finish = r600_fence_finish;
954 r600_init_screen_resource_functions(&rscreen->screen);
955
956 util_format_s3tc_init();
957
958 rscreen->fences.bo = NULL;
959 rscreen->fences.data = NULL;
960 rscreen->fences.next_index = 0;
961 LIST_INITHEAD(&rscreen->fences.pool);
962 LIST_INITHEAD(&rscreen->fences.blocks);
963 pipe_mutex_init(rscreen->fences.mutex);
964
965 rscreen->global_pool = compute_memory_pool_new(rscreen);
966
967 return &rscreen->screen;
968 }