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[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_pipe.h"
24 #include "r600_public.h"
25 #include "r600_isa.h"
26 #include "evergreen_compute.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include <errno.h>
32 #include "pipe/p_shader_tokens.h"
33 #include "util/u_blitter.h"
34 #include "util/u_debug.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_simple_shaders.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_math.h"
40 #include "vl/vl_decoder.h"
41 #include "vl/vl_video_buffer.h"
42 #include "radeon/radeon_uvd.h"
43 #include "os/os_time.h"
44
45 static const struct debug_named_value debug_options[] = {
46 /* logging */
47 { "texdepth", DBG_TEX_DEPTH, "Print texture depth info" },
48 { "compute", DBG_COMPUTE, "Print compute info" },
49 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
50 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
51
52 /* shaders */
53 { "fs", DBG_FS, "Print fetch shaders" },
54 { "vs", DBG_VS, "Print vertex shaders" },
55 { "gs", DBG_GS, "Print geometry shaders" },
56 { "ps", DBG_PS, "Print pixel shaders" },
57 { "cs", DBG_CS, "Print compute shaders" },
58
59 /* features */
60 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
61 #if defined(R600_USE_LLVM)
62 { "nollvm", DBG_NO_LLVM, "Disable the LLVM shader compiler" },
63 #endif
64 { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
65 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
66 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
67 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
68
69 /* shader backend */
70 { "sb", DBG_SB, "Enable optimization of graphics shaders" },
71 { "sbcl", DBG_SB_CS, "Enable optimization of compute shaders" },
72 { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
73 { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
74 { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
75 { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
76 { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
77
78 DEBUG_NAMED_VALUE_END /* must be last */
79 };
80
81 /*
82 * pipe_context
83 */
84 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
85 {
86 struct r600_screen *rscreen = rctx->screen;
87 struct r600_fence *fence = NULL;
88
89 pipe_mutex_lock(rscreen->fences.mutex);
90
91 if (!rscreen->fences.bo) {
92 /* Create the shared buffer object */
93 rscreen->fences.bo = (struct r600_resource*)
94 pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
95 PIPE_USAGE_STAGING, 4096);
96 if (!rscreen->fences.bo) {
97 R600_ERR("r600: failed to create bo for fence objects\n");
98 goto out;
99 }
100 rscreen->fences.data = r600_buffer_mmap_sync_with_rings(rctx, rscreen->fences.bo, PIPE_TRANSFER_READ_WRITE);
101 }
102
103 if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
104 struct r600_fence *entry;
105
106 /* Try to find a freed fence that has been signalled */
107 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
108 if (rscreen->fences.data[entry->index] != 0) {
109 LIST_DELINIT(&entry->head);
110 fence = entry;
111 break;
112 }
113 }
114 }
115
116 if (!fence) {
117 /* Allocate a new fence */
118 struct r600_fence_block *block;
119 unsigned index;
120
121 if ((rscreen->fences.next_index + 1) >= 1024) {
122 R600_ERR("r600: too many concurrent fences\n");
123 goto out;
124 }
125
126 index = rscreen->fences.next_index++;
127
128 if (!(index % FENCE_BLOCK_SIZE)) {
129 /* Allocate a new block */
130 block = CALLOC_STRUCT(r600_fence_block);
131 if (block == NULL)
132 goto out;
133
134 LIST_ADD(&block->head, &rscreen->fences.blocks);
135 } else {
136 block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
137 }
138
139 fence = &block->fences[index % FENCE_BLOCK_SIZE];
140 fence->index = index;
141 }
142
143 pipe_reference_init(&fence->reference, 1);
144
145 rscreen->fences.data[fence->index] = 0;
146 r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
147
148 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
149 fence->sleep_bo = (struct r600_resource*)
150 pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
151 PIPE_USAGE_STAGING, 1);
152 /* Add the fence as a dummy relocation. */
153 r600_context_bo_reloc(rctx, &rctx->rings.gfx, fence->sleep_bo, RADEON_USAGE_READWRITE);
154
155 out:
156 pipe_mutex_unlock(rscreen->fences.mutex);
157 return fence;
158 }
159
160 static void r600_flush(struct pipe_context *ctx, unsigned flags)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct pipe_query *render_cond = NULL;
164 unsigned render_cond_mode = 0;
165
166 rctx->rings.gfx.flushing = true;
167 /* Disable render condition. */
168 if (rctx->current_render_cond) {
169 render_cond = rctx->current_render_cond;
170 render_cond_mode = rctx->current_render_cond_mode;
171 ctx->render_condition(ctx, NULL, 0);
172 }
173
174 r600_context_flush(rctx, flags);
175 rctx->rings.gfx.flushing = false;
176 r600_begin_new_cs(rctx);
177
178 /* Re-enable render condition. */
179 if (render_cond) {
180 ctx->render_condition(ctx, render_cond, render_cond_mode);
181 }
182 }
183
184 static void r600_flush_from_st(struct pipe_context *ctx,
185 struct pipe_fence_handle **fence,
186 enum pipe_flush_flags flags)
187 {
188 struct r600_context *rctx = (struct r600_context *)ctx;
189 struct r600_fence **rfence = (struct r600_fence**)fence;
190 unsigned fflags;
191
192 fflags = flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0;
193 if (rfence) {
194 *rfence = r600_create_fence(rctx);
195 }
196 /* flush gfx & dma ring, order does not matter as only one can be live */
197 if (rctx->rings.dma.cs) {
198 rctx->rings.dma.flush(rctx, fflags);
199 }
200 rctx->rings.gfx.flush(rctx, fflags);
201 }
202
203 static void r600_flush_gfx_ring(void *ctx, unsigned flags)
204 {
205 r600_flush((struct pipe_context*)ctx, flags);
206 }
207
208 static void r600_flush_dma_ring(void *ctx, unsigned flags)
209 {
210 struct r600_context *rctx = (struct r600_context *)ctx;
211 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
212 unsigned padding_dw, i;
213
214 if (!cs->cdw) {
215 return;
216 }
217
218 /* Pad the DMA CS to a multiple of 8 dwords. */
219 padding_dw = 8 - cs->cdw % 8;
220 if (padding_dw < 8) {
221 for (i = 0; i < padding_dw; i++) {
222 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
223 }
224 }
225
226 rctx->rings.dma.flushing = true;
227 rctx->ws->cs_flush(cs, flags, 0);
228 rctx->rings.dma.flushing = false;
229 }
230
231 boolean r600_rings_is_buffer_referenced(struct r600_context *ctx,
232 struct radeon_winsys_cs_handle *buf,
233 enum radeon_bo_usage usage)
234 {
235 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, buf, usage)) {
236 return TRUE;
237 }
238 if (ctx->rings.dma.cs) {
239 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, buf, usage)) {
240 return TRUE;
241 }
242 }
243 return FALSE;
244 }
245
246 void *r600_buffer_mmap_sync_with_rings(struct r600_context *ctx,
247 struct r600_resource *resource,
248 unsigned usage)
249 {
250 enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
251 unsigned flags = 0;
252 bool sync_flush = TRUE;
253
254 if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
255 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
256 }
257
258 if (!(usage & PIPE_TRANSFER_WRITE)) {
259 /* have to wait for pending read */
260 rusage = RADEON_USAGE_WRITE;
261 }
262 if (usage & PIPE_TRANSFER_DONTBLOCK) {
263 flags |= RADEON_FLUSH_ASYNC;
264 }
265
266 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, resource->cs_buf, rusage) && ctx->rings.gfx.cs->cdw) {
267 ctx->rings.gfx.flush(ctx, flags);
268 if (usage & PIPE_TRANSFER_DONTBLOCK) {
269 return NULL;
270 }
271 }
272 if (ctx->rings.dma.cs) {
273 if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, resource->cs_buf, rusage) && ctx->rings.dma.cs->cdw) {
274 ctx->rings.dma.flush(ctx, flags);
275 if (usage & PIPE_TRANSFER_DONTBLOCK) {
276 return NULL;
277 }
278 }
279 }
280
281 if (usage & PIPE_TRANSFER_DONTBLOCK) {
282 if (ctx->ws->buffer_is_busy(resource->buf, rusage)) {
283 return NULL;
284 }
285 }
286 if (sync_flush) {
287 /* Try to avoid busy-waiting in radeon_bo_wait. */
288 ctx->ws->cs_sync_flush(ctx->rings.gfx.cs);
289 if (ctx->rings.dma.cs) {
290 ctx->ws->cs_sync_flush(ctx->rings.dma.cs);
291 }
292 }
293 ctx->ws->buffer_wait(resource->buf, rusage);
294
295 /* at this point everything is synchronized */
296 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage | PIPE_TRANSFER_UNSYNCHRONIZED);
297 }
298
299 static void r600_flush_from_winsys(void *ctx, unsigned flags)
300 {
301 struct r600_context *rctx = (struct r600_context *)ctx;
302
303 rctx->rings.gfx.flush(rctx, flags);
304 }
305
306 static void r600_flush_dma_from_winsys(void *ctx, unsigned flags)
307 {
308 struct r600_context *rctx = (struct r600_context *)ctx;
309
310 rctx->rings.dma.flush(rctx, flags);
311 }
312
313 static void r600_destroy_context(struct pipe_context *context)
314 {
315 struct r600_context *rctx = (struct r600_context *)context;
316
317 r600_isa_destroy(rctx->isa);
318
319 r600_sb_context_destroy(rctx->sb_context);
320
321 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
322 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
323
324 if (rctx->dummy_pixel_shader) {
325 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
326 }
327 if (rctx->custom_dsa_flush) {
328 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
329 }
330 if (rctx->custom_blend_resolve) {
331 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve);
332 }
333 if (rctx->custom_blend_decompress) {
334 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_decompress);
335 }
336 if (rctx->custom_blend_fmask_decompress) {
337 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_fmask_decompress);
338 }
339 util_unreference_framebuffer_state(&rctx->framebuffer.state);
340
341 if (rctx->blitter) {
342 util_blitter_destroy(rctx->blitter);
343 }
344 if (rctx->uploader) {
345 u_upload_destroy(rctx->uploader);
346 }
347 if (rctx->allocator_so_filled_size) {
348 u_suballocator_destroy(rctx->allocator_so_filled_size);
349 }
350 if (rctx->allocator_fetch_shader) {
351 u_suballocator_destroy(rctx->allocator_fetch_shader);
352 }
353 util_slab_destroy(&rctx->pool_transfers);
354
355 r600_release_command_buffer(&rctx->start_cs_cmd);
356
357 if (rctx->rings.gfx.cs) {
358 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
359 }
360 if (rctx->rings.dma.cs) {
361 rctx->ws->cs_destroy(rctx->rings.dma.cs);
362 }
363
364 FREE(rctx);
365 }
366
367 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
368 {
369 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
370 struct r600_screen* rscreen = (struct r600_screen *)screen;
371
372 if (rctx == NULL)
373 return NULL;
374
375 util_slab_create(&rctx->pool_transfers,
376 sizeof(struct r600_transfer), 64,
377 UTIL_SLAB_SINGLETHREADED);
378
379 rctx->context.screen = screen;
380 rctx->context.priv = priv;
381 rctx->context.destroy = r600_destroy_context;
382 rctx->context.flush = r600_flush_from_st;
383
384 /* Easy accessing of screen/winsys. */
385 rctx->screen = rscreen;
386 rctx->ws = rscreen->ws;
387 rctx->family = rscreen->family;
388 rctx->chip_class = rscreen->chip_class;
389 rctx->keep_tiling_flags = rscreen->info.drm_minor >= 12;
390
391 LIST_INITHEAD(&rctx->active_nontimer_queries);
392
393 r600_init_blit_functions(rctx);
394 r600_init_query_functions(rctx);
395 r600_init_context_resource_functions(rctx);
396 r600_init_surface_functions(rctx);
397
398 if (rscreen->info.has_uvd) {
399 rctx->context.create_video_decoder = r600_uvd_create_decoder;
400 rctx->context.create_video_buffer = r600_video_buffer_create;
401 } else {
402 rctx->context.create_video_decoder = vl_create_decoder;
403 rctx->context.create_video_buffer = vl_video_buffer_create;
404 }
405
406 r600_init_common_state_functions(rctx);
407
408 switch (rctx->chip_class) {
409 case R600:
410 case R700:
411 r600_init_state_functions(rctx);
412 r600_init_atom_start_cs(rctx);
413 rctx->max_db = 4;
414 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
415 rctx->custom_blend_resolve = rctx->chip_class == R700 ? r700_create_resolve_blend(rctx)
416 : r600_create_resolve_blend(rctx);
417 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
418 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
419 rctx->family == CHIP_RV620 ||
420 rctx->family == CHIP_RS780 ||
421 rctx->family == CHIP_RS880 ||
422 rctx->family == CHIP_RV710);
423 break;
424 case EVERGREEN:
425 case CAYMAN:
426 evergreen_init_state_functions(rctx);
427 evergreen_init_atom_start_cs(rctx);
428 evergreen_init_atom_start_compute_cs(rctx);
429 rctx->max_db = 8;
430 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
431 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
432 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
433 rctx->custom_blend_fmask_decompress = evergreen_create_fmask_decompress_blend(rctx);
434 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
435 rctx->family == CHIP_PALM ||
436 rctx->family == CHIP_SUMO ||
437 rctx->family == CHIP_SUMO2 ||
438 rctx->family == CHIP_CAICOS ||
439 rctx->family == CHIP_CAYMAN ||
440 rctx->family == CHIP_ARUBA);
441 break;
442 default:
443 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
444 goto fail;
445 }
446
447 if (rscreen->trace_bo) {
448 rctx->rings.gfx.cs = rctx->ws->cs_create(rctx->ws, RING_GFX, rscreen->trace_bo->cs_buf);
449 } else {
450 rctx->rings.gfx.cs = rctx->ws->cs_create(rctx->ws, RING_GFX, NULL);
451 }
452 rctx->rings.gfx.flush = r600_flush_gfx_ring;
453 rctx->ws->cs_set_flush_callback(rctx->rings.gfx.cs, r600_flush_from_winsys, rctx);
454 rctx->rings.gfx.flushing = false;
455
456 rctx->rings.dma.cs = NULL;
457 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
458 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA, NULL);
459 rctx->rings.dma.flush = r600_flush_dma_ring;
460 rctx->ws->cs_set_flush_callback(rctx->rings.dma.cs, r600_flush_dma_from_winsys, rctx);
461 rctx->rings.dma.flushing = false;
462 }
463
464 rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
465 PIPE_BIND_INDEX_BUFFER |
466 PIPE_BIND_CONSTANT_BUFFER);
467 if (!rctx->uploader)
468 goto fail;
469
470 rctx->allocator_fetch_shader = u_suballocator_create(&rctx->context, 64 * 1024, 256,
471 0, PIPE_USAGE_STATIC, FALSE);
472 if (!rctx->allocator_fetch_shader)
473 goto fail;
474
475 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->context, 4096, 4,
476 0, PIPE_USAGE_STATIC, TRUE);
477 if (!rctx->allocator_so_filled_size)
478 goto fail;
479
480 rctx->isa = calloc(1, sizeof(struct r600_isa));
481 if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
482 goto fail;
483
484 rctx->blitter = util_blitter_create(&rctx->context);
485 if (rctx->blitter == NULL)
486 goto fail;
487 util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
488 rctx->blitter->draw_rectangle = r600_draw_rectangle;
489
490 r600_begin_new_cs(rctx);
491 r600_get_backend_mask(rctx); /* this emits commands and must be last */
492
493 rctx->dummy_pixel_shader =
494 util_make_fragment_cloneinput_shader(&rctx->context, 0,
495 TGSI_SEMANTIC_GENERIC,
496 TGSI_INTERPOLATE_CONSTANT);
497 rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
498
499 return &rctx->context;
500
501 fail:
502 r600_destroy_context(&rctx->context);
503 return NULL;
504 }
505
506 /*
507 * pipe_screen
508 */
509 static const char* r600_get_vendor(struct pipe_screen* pscreen)
510 {
511 return "X.Org";
512 }
513
514 static const char *r600_get_family_name(enum radeon_family family)
515 {
516 switch(family) {
517 case CHIP_R600: return "AMD R600";
518 case CHIP_RV610: return "AMD RV610";
519 case CHIP_RV630: return "AMD RV630";
520 case CHIP_RV670: return "AMD RV670";
521 case CHIP_RV620: return "AMD RV620";
522 case CHIP_RV635: return "AMD RV635";
523 case CHIP_RS780: return "AMD RS780";
524 case CHIP_RS880: return "AMD RS880";
525 case CHIP_RV770: return "AMD RV770";
526 case CHIP_RV730: return "AMD RV730";
527 case CHIP_RV710: return "AMD RV710";
528 case CHIP_RV740: return "AMD RV740";
529 case CHIP_CEDAR: return "AMD CEDAR";
530 case CHIP_REDWOOD: return "AMD REDWOOD";
531 case CHIP_JUNIPER: return "AMD JUNIPER";
532 case CHIP_CYPRESS: return "AMD CYPRESS";
533 case CHIP_HEMLOCK: return "AMD HEMLOCK";
534 case CHIP_PALM: return "AMD PALM";
535 case CHIP_SUMO: return "AMD SUMO";
536 case CHIP_SUMO2: return "AMD SUMO2";
537 case CHIP_BARTS: return "AMD BARTS";
538 case CHIP_TURKS: return "AMD TURKS";
539 case CHIP_CAICOS: return "AMD CAICOS";
540 case CHIP_CAYMAN: return "AMD CAYMAN";
541 case CHIP_ARUBA: return "AMD ARUBA";
542 default: return "AMD unknown";
543 }
544 }
545
546 static const char* r600_get_name(struct pipe_screen* pscreen)
547 {
548 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
549
550 return r600_get_family_name(rscreen->family);
551 }
552
553 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
554 {
555 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
556 enum radeon_family family = rscreen->family;
557
558 switch (param) {
559 /* Supported features (boolean caps). */
560 case PIPE_CAP_NPOT_TEXTURES:
561 case PIPE_CAP_TWO_SIDED_STENCIL:
562 case PIPE_CAP_ANISOTROPIC_FILTER:
563 case PIPE_CAP_POINT_SPRITE:
564 case PIPE_CAP_OCCLUSION_QUERY:
565 case PIPE_CAP_TEXTURE_SHADOW_MAP:
566 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
567 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
568 case PIPE_CAP_TEXTURE_SWIZZLE:
569 case PIPE_CAP_DEPTH_CLIP_DISABLE:
570 case PIPE_CAP_SHADER_STENCIL_EXPORT:
571 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
572 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
573 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
574 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
575 case PIPE_CAP_SM3:
576 case PIPE_CAP_SEAMLESS_CUBE_MAP:
577 case PIPE_CAP_PRIMITIVE_RESTART:
578 case PIPE_CAP_CONDITIONAL_RENDER:
579 case PIPE_CAP_TEXTURE_BARRIER:
580 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
581 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
582 case PIPE_CAP_TGSI_INSTANCEID:
583 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
584 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
585 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
586 case PIPE_CAP_USER_INDEX_BUFFERS:
587 case PIPE_CAP_USER_CONSTANT_BUFFERS:
588 case PIPE_CAP_COMPUTE:
589 case PIPE_CAP_START_INSTANCE:
590 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
591 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
592 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
593 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
594 return 1;
595 case PIPE_CAP_TGSI_TEXCOORD:
596 return 0;
597
598 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
599 return R600_MAP_BUFFER_ALIGNMENT;
600
601 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
602 return 256;
603
604 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
605 return 1;
606
607 case PIPE_CAP_GLSL_FEATURE_LEVEL:
608 return 140;
609
610 case PIPE_CAP_TEXTURE_MULTISAMPLE:
611 return rscreen->msaa_texture_support != MSAA_TEXTURE_SAMPLE_ZERO;
612
613 /* Supported except the original R600. */
614 case PIPE_CAP_INDEP_BLEND_ENABLE:
615 case PIPE_CAP_INDEP_BLEND_FUNC:
616 /* R600 doesn't support per-MRT blends */
617 return family == CHIP_R600 ? 0 : 1;
618
619 /* Supported on Evergreen. */
620 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
621 case PIPE_CAP_CUBE_MAP_ARRAY:
622 return family >= CHIP_CEDAR ? 1 : 0;
623
624 /* Unsupported features. */
625 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
626 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
627 case PIPE_CAP_SCALED_RESOLVE:
628 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
629 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
630 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
631 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
632 case PIPE_CAP_USER_VERTEX_BUFFERS:
633 return 0;
634
635 /* Stream output. */
636 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
637 return rscreen->has_streamout ? 4 : 0;
638 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
639 return rscreen->has_streamout ? 1 : 0;
640 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
641 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
642 return 32*4;
643
644 /* Texturing. */
645 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
646 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
647 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
648 if (family >= CHIP_CEDAR)
649 return 15;
650 else
651 return 14;
652 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
653 return rscreen->info.drm_minor >= 9 ?
654 (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
655 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
656 return 32;
657
658 /* Render targets. */
659 case PIPE_CAP_MAX_RENDER_TARGETS:
660 /* XXX some r6xx are buggy and can only do 4 */
661 return 8;
662
663 /* Timer queries, present when the clock frequency is non zero. */
664 case PIPE_CAP_QUERY_TIME_ELAPSED:
665 return rscreen->info.r600_clock_crystal_freq != 0;
666 case PIPE_CAP_QUERY_TIMESTAMP:
667 return rscreen->info.drm_minor >= 20 &&
668 rscreen->info.r600_clock_crystal_freq != 0;
669
670 case PIPE_CAP_MIN_TEXEL_OFFSET:
671 return -8;
672
673 case PIPE_CAP_MAX_TEXEL_OFFSET:
674 return 7;
675
676 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
677 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
678 }
679 return 0;
680 }
681
682 static float r600_get_paramf(struct pipe_screen* pscreen,
683 enum pipe_capf param)
684 {
685 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
686 enum radeon_family family = rscreen->family;
687
688 switch (param) {
689 case PIPE_CAPF_MAX_LINE_WIDTH:
690 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
691 case PIPE_CAPF_MAX_POINT_WIDTH:
692 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
693 if (family >= CHIP_CEDAR)
694 return 16384.0f;
695 else
696 return 8192.0f;
697 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
698 return 16.0f;
699 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
700 return 16.0f;
701 case PIPE_CAPF_GUARD_BAND_LEFT:
702 case PIPE_CAPF_GUARD_BAND_TOP:
703 case PIPE_CAPF_GUARD_BAND_RIGHT:
704 case PIPE_CAPF_GUARD_BAND_BOTTOM:
705 return 0.0f;
706 }
707 return 0.0f;
708 }
709
710 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
711 {
712 switch(shader)
713 {
714 case PIPE_SHADER_FRAGMENT:
715 case PIPE_SHADER_VERTEX:
716 case PIPE_SHADER_COMPUTE:
717 break;
718 case PIPE_SHADER_GEOMETRY:
719 /* XXX: support and enable geometry programs */
720 return 0;
721 default:
722 /* XXX: support tessellation on Evergreen */
723 return 0;
724 }
725
726 switch (param) {
727 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
728 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
729 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
730 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
731 return 16384;
732 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
733 return 32;
734 case PIPE_SHADER_CAP_MAX_INPUTS:
735 return 32;
736 case PIPE_SHADER_CAP_MAX_TEMPS:
737 return 256; /* Max native temporaries. */
738 case PIPE_SHADER_CAP_MAX_ADDRS:
739 /* XXX Isn't this equal to TEMPS? */
740 return 1; /* Max native address registers */
741 case PIPE_SHADER_CAP_MAX_CONSTS:
742 return R600_MAX_CONST_BUFFER_SIZE;
743 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
744 return R600_MAX_USER_CONST_BUFFERS;
745 case PIPE_SHADER_CAP_MAX_PREDS:
746 return 0; /* nothing uses this */
747 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
748 return 1;
749 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
750 return 0;
751 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
752 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
753 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
754 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
755 return 1;
756 case PIPE_SHADER_CAP_SUBROUTINES:
757 return 0;
758 case PIPE_SHADER_CAP_INTEGERS:
759 return 1;
760 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
761 return 16;
762 case PIPE_SHADER_CAP_PREFERRED_IR:
763 if (shader == PIPE_SHADER_COMPUTE) {
764 return PIPE_SHADER_IR_LLVM;
765 } else {
766 return PIPE_SHADER_IR_TGSI;
767 }
768 }
769 return 0;
770 }
771
772 static int r600_get_video_param(struct pipe_screen *screen,
773 enum pipe_video_profile profile,
774 enum pipe_video_cap param)
775 {
776 switch (param) {
777 case PIPE_VIDEO_CAP_SUPPORTED:
778 return vl_profile_supported(screen, profile);
779 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
780 return 1;
781 case PIPE_VIDEO_CAP_MAX_WIDTH:
782 case PIPE_VIDEO_CAP_MAX_HEIGHT:
783 return vl_video_buffer_max_size(screen);
784 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
785 return PIPE_FORMAT_NV12;
786 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
787 return false;
788 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
789 return false;
790 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
791 return true;
792 default:
793 return 0;
794 }
795 }
796
797 const char * r600_llvm_gpu_string(enum radeon_family family)
798 {
799 const char * gpu_family;
800
801 switch (family) {
802 case CHIP_R600:
803 case CHIP_RV610:
804 case CHIP_RV630:
805 case CHIP_RV620:
806 case CHIP_RV635:
807 case CHIP_RV670:
808 case CHIP_RS780:
809 case CHIP_RS880:
810 gpu_family = "r600";
811 break;
812 case CHIP_RV710:
813 gpu_family = "rv710";
814 break;
815 case CHIP_RV730:
816 gpu_family = "rv730";
817 break;
818 case CHIP_RV740:
819 case CHIP_RV770:
820 gpu_family = "rv770";
821 break;
822 case CHIP_PALM:
823 case CHIP_CEDAR:
824 gpu_family = "cedar";
825 break;
826 case CHIP_SUMO:
827 case CHIP_SUMO2:
828 case CHIP_REDWOOD:
829 gpu_family = "redwood";
830 break;
831 case CHIP_JUNIPER:
832 gpu_family = "juniper";
833 break;
834 case CHIP_HEMLOCK:
835 case CHIP_CYPRESS:
836 gpu_family = "cypress";
837 break;
838 case CHIP_BARTS:
839 gpu_family = "barts";
840 break;
841 case CHIP_TURKS:
842 gpu_family = "turks";
843 break;
844 case CHIP_CAICOS:
845 gpu_family = "caicos";
846 break;
847 case CHIP_CAYMAN:
848 case CHIP_ARUBA:
849 gpu_family = "cayman";
850 break;
851 default:
852 gpu_family = "";
853 fprintf(stderr, "Chip not supported by r600 llvm "
854 "backend, please file a bug at " PACKAGE_BUGREPORT "\n");
855 break;
856 }
857 return gpu_family;
858 }
859
860
861 static int r600_get_compute_param(struct pipe_screen *screen,
862 enum pipe_compute_cap param,
863 void *ret)
864 {
865 struct r600_screen *rscreen = (struct r600_screen *)screen;
866 //TODO: select these params by asic
867 switch (param) {
868 case PIPE_COMPUTE_CAP_IR_TARGET: {
869 const char *gpu = r600_llvm_gpu_string(rscreen->family);
870 if (ret) {
871 sprintf(ret, "%s-r600--", gpu);
872 }
873 return (8 + strlen(gpu)) * sizeof(char);
874 }
875 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
876 if (ret) {
877 uint64_t * grid_dimension = ret;
878 grid_dimension[0] = 3;
879 }
880 return 1 * sizeof(uint64_t);
881
882 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
883 if (ret) {
884 uint64_t * grid_size = ret;
885 grid_size[0] = 65535;
886 grid_size[1] = 65535;
887 grid_size[2] = 1;
888 }
889 return 3 * sizeof(uint64_t) ;
890
891 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
892 if (ret) {
893 uint64_t * block_size = ret;
894 block_size[0] = 256;
895 block_size[1] = 256;
896 block_size[2] = 256;
897 }
898 return 3 * sizeof(uint64_t);
899
900 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
901 if (ret) {
902 uint64_t * max_threads_per_block = ret;
903 *max_threads_per_block = 256;
904 }
905 return sizeof(uint64_t);
906
907 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
908 if (ret) {
909 uint64_t * max_global_size = ret;
910 /* XXX: This is what the proprietary driver reports, we
911 * may want to use a different value. */
912 *max_global_size = 201326592;
913 }
914 return sizeof(uint64_t);
915
916 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
917 if (ret) {
918 uint64_t * max_input_size = ret;
919 *max_input_size = 1024;
920 }
921 return sizeof(uint64_t);
922
923 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
924 if (ret) {
925 uint64_t * max_local_size = ret;
926 /* XXX: This is what the proprietary driver reports, we
927 * may want to use a different value. */
928 *max_local_size = 32768;
929 }
930 return sizeof(uint64_t);
931
932 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
933 if (ret) {
934 uint64_t max_global_size;
935 uint64_t * max_mem_alloc_size = ret;
936 r600_get_compute_param(screen,
937 PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
938 &max_global_size);
939 /* OpenCL requres this value be at least
940 * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
941 * I'm really not sure what value to report here, but
942 * MAX_GLOBAL_SIZE / 4 seems resonable.
943 */
944 *max_mem_alloc_size = max_global_size / 4;
945 }
946 return sizeof(uint64_t);
947
948 default:
949 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
950 return 0;
951 }
952 }
953
954 static void r600_destroy_screen(struct pipe_screen* pscreen)
955 {
956 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
957
958 if (rscreen == NULL)
959 return;
960
961 pipe_mutex_destroy(rscreen->aux_context_lock);
962 rscreen->aux_context->destroy(rscreen->aux_context);
963
964 if (rscreen->global_pool) {
965 compute_memory_pool_delete(rscreen->global_pool);
966 }
967
968 if (rscreen->fences.bo) {
969 struct r600_fence_block *entry, *tmp;
970
971 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
972 LIST_DEL(&entry->head);
973 FREE(entry);
974 }
975
976 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
977 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
978 }
979 if (rscreen->trace_bo) {
980 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
981 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
982 }
983 pipe_mutex_destroy(rscreen->fences.mutex);
984
985 rscreen->ws->destroy(rscreen->ws);
986 FREE(rscreen);
987 }
988
989 static void r600_fence_reference(struct pipe_screen *pscreen,
990 struct pipe_fence_handle **ptr,
991 struct pipe_fence_handle *fence)
992 {
993 struct r600_fence **oldf = (struct r600_fence**)ptr;
994 struct r600_fence *newf = (struct r600_fence*)fence;
995
996 if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
997 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
998 pipe_mutex_lock(rscreen->fences.mutex);
999 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
1000 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
1001 pipe_mutex_unlock(rscreen->fences.mutex);
1002 }
1003
1004 *ptr = fence;
1005 }
1006
1007 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
1008 struct pipe_fence_handle *fence)
1009 {
1010 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
1011 struct r600_fence *rfence = (struct r600_fence*)fence;
1012
1013 return rscreen->fences.data[rfence->index] != 0;
1014 }
1015
1016 static boolean r600_fence_finish(struct pipe_screen *pscreen,
1017 struct pipe_fence_handle *fence,
1018 uint64_t timeout)
1019 {
1020 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
1021 struct r600_fence *rfence = (struct r600_fence*)fence;
1022 int64_t start_time = 0;
1023 unsigned spins = 0;
1024
1025 if (timeout != PIPE_TIMEOUT_INFINITE) {
1026 start_time = os_time_get();
1027
1028 /* Convert to microseconds. */
1029 timeout /= 1000;
1030 }
1031
1032 while (rscreen->fences.data[rfence->index] == 0) {
1033 /* Special-case infinite timeout - wait for the dummy BO to become idle */
1034 if (timeout == PIPE_TIMEOUT_INFINITE) {
1035 rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
1036 break;
1037 }
1038
1039 /* The dummy BO will be busy until the CS including the fence has completed, or
1040 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
1041 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
1042 break;
1043
1044 if (++spins % 256)
1045 continue;
1046 #ifdef PIPE_OS_UNIX
1047 sched_yield();
1048 #else
1049 os_time_sleep(10);
1050 #endif
1051 if (timeout != PIPE_TIMEOUT_INFINITE &&
1052 os_time_get() - start_time >= timeout) {
1053 break;
1054 }
1055 }
1056
1057 return rscreen->fences.data[rfence->index] != 0;
1058 }
1059
1060 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
1061 {
1062 switch ((tiling_config & 0xe) >> 1) {
1063 case 0:
1064 rscreen->tiling_info.num_channels = 1;
1065 break;
1066 case 1:
1067 rscreen->tiling_info.num_channels = 2;
1068 break;
1069 case 2:
1070 rscreen->tiling_info.num_channels = 4;
1071 break;
1072 case 3:
1073 rscreen->tiling_info.num_channels = 8;
1074 break;
1075 default:
1076 return -EINVAL;
1077 }
1078
1079 switch ((tiling_config & 0x30) >> 4) {
1080 case 0:
1081 rscreen->tiling_info.num_banks = 4;
1082 break;
1083 case 1:
1084 rscreen->tiling_info.num_banks = 8;
1085 break;
1086 default:
1087 return -EINVAL;
1088
1089 }
1090 switch ((tiling_config & 0xc0) >> 6) {
1091 case 0:
1092 rscreen->tiling_info.group_bytes = 256;
1093 break;
1094 case 1:
1095 rscreen->tiling_info.group_bytes = 512;
1096 break;
1097 default:
1098 return -EINVAL;
1099 }
1100 return 0;
1101 }
1102
1103 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
1104 {
1105 switch (tiling_config & 0xf) {
1106 case 0:
1107 rscreen->tiling_info.num_channels = 1;
1108 break;
1109 case 1:
1110 rscreen->tiling_info.num_channels = 2;
1111 break;
1112 case 2:
1113 rscreen->tiling_info.num_channels = 4;
1114 break;
1115 case 3:
1116 rscreen->tiling_info.num_channels = 8;
1117 break;
1118 default:
1119 return -EINVAL;
1120 }
1121
1122 switch ((tiling_config & 0xf0) >> 4) {
1123 case 0:
1124 rscreen->tiling_info.num_banks = 4;
1125 break;
1126 case 1:
1127 rscreen->tiling_info.num_banks = 8;
1128 break;
1129 case 2:
1130 rscreen->tiling_info.num_banks = 16;
1131 break;
1132 default:
1133 return -EINVAL;
1134 }
1135
1136 switch ((tiling_config & 0xf00) >> 8) {
1137 case 0:
1138 rscreen->tiling_info.group_bytes = 256;
1139 break;
1140 case 1:
1141 rscreen->tiling_info.group_bytes = 512;
1142 break;
1143 default:
1144 return -EINVAL;
1145 }
1146 return 0;
1147 }
1148
1149 static int r600_init_tiling(struct r600_screen *rscreen)
1150 {
1151 uint32_t tiling_config = rscreen->info.r600_tiling_config;
1152
1153 /* set default group bytes, overridden by tiling info ioctl */
1154 if (rscreen->chip_class <= R700) {
1155 rscreen->tiling_info.group_bytes = 256;
1156 } else {
1157 rscreen->tiling_info.group_bytes = 512;
1158 }
1159
1160 if (!tiling_config)
1161 return 0;
1162
1163 if (rscreen->chip_class <= R700) {
1164 return r600_interpret_tiling(rscreen, tiling_config);
1165 } else {
1166 return evergreen_interpret_tiling(rscreen, tiling_config);
1167 }
1168 }
1169
1170 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1171 {
1172 struct r600_screen *rscreen = (struct r600_screen*)screen;
1173
1174 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1175 rscreen->info.r600_clock_crystal_freq;
1176 }
1177
1178 static int r600_get_driver_query_info(struct pipe_screen *screen,
1179 unsigned index,
1180 struct pipe_driver_query_info *info)
1181 {
1182 struct r600_screen *rscreen = (struct r600_screen*)screen;
1183 struct pipe_driver_query_info list[] = {
1184 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
1185 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
1186 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
1187 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE}
1188 };
1189
1190 if (!info)
1191 return Elements(list);
1192
1193 if (index >= Elements(list))
1194 return 0;
1195
1196 *info = list[index];
1197 return 1;
1198 }
1199
1200 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
1201 {
1202 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
1203
1204 if (rscreen == NULL) {
1205 return NULL;
1206 }
1207
1208 rscreen->ws = ws;
1209 ws->query_info(ws, &rscreen->info);
1210
1211 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", debug_options, 0);
1212 if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
1213 rscreen->debug_flags |= DBG_COMPUTE;
1214 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
1215 rscreen->debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
1216 if (!debug_get_bool_option("R600_HYPERZ", TRUE))
1217 rscreen->debug_flags |= DBG_NO_HYPERZ;
1218 if (!debug_get_bool_option("R600_LLVM", TRUE))
1219 rscreen->debug_flags |= DBG_NO_LLVM;
1220 if (debug_get_bool_option("R600_PRINT_TEXDEPTH", FALSE))
1221 rscreen->debug_flags |= DBG_TEX_DEPTH;
1222 rscreen->family = rscreen->info.family;
1223 rscreen->chip_class = rscreen->info.chip_class;
1224
1225 if (rscreen->family == CHIP_UNKNOWN) {
1226 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
1227 FREE(rscreen);
1228 return NULL;
1229 }
1230
1231 /* Figure out streamout kernel support. */
1232 switch (rscreen->chip_class) {
1233 case R600:
1234 if (rscreen->family < CHIP_RS780) {
1235 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
1236 } else {
1237 rscreen->has_streamout = rscreen->info.drm_minor >= 23;
1238 }
1239 break;
1240 case R700:
1241 rscreen->has_streamout = rscreen->info.drm_minor >= 17;
1242 break;
1243 case EVERGREEN:
1244 case CAYMAN:
1245 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
1246 break;
1247 default:
1248 rscreen->has_streamout = FALSE;
1249 break;
1250 }
1251
1252 /* MSAA support. */
1253 switch (rscreen->chip_class) {
1254 case R600:
1255 case R700:
1256 rscreen->has_msaa = rscreen->info.drm_minor >= 22;
1257 rscreen->msaa_texture_support = MSAA_TEXTURE_DECOMPRESSED;
1258 break;
1259 case EVERGREEN:
1260 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
1261 rscreen->msaa_texture_support =
1262 rscreen->info.drm_minor >= 24 ? MSAA_TEXTURE_COMPRESSED :
1263 MSAA_TEXTURE_DECOMPRESSED;
1264 break;
1265 case CAYMAN:
1266 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
1267 /* We should be able to read compressed MSAA textures, but it doesn't work. */
1268 rscreen->msaa_texture_support = MSAA_TEXTURE_SAMPLE_ZERO;
1269 break;
1270 default:
1271 rscreen->has_msaa = FALSE;
1272 rscreen->msaa_texture_support = 0;
1273 break;
1274 }
1275
1276 rscreen->has_cp_dma = rscreen->info.drm_minor >= 27 &&
1277 !(rscreen->debug_flags & DBG_NO_CP_DMA);
1278
1279 if (r600_init_tiling(rscreen)) {
1280 FREE(rscreen);
1281 return NULL;
1282 }
1283
1284 rscreen->screen.destroy = r600_destroy_screen;
1285 rscreen->screen.get_name = r600_get_name;
1286 rscreen->screen.get_vendor = r600_get_vendor;
1287 rscreen->screen.get_param = r600_get_param;
1288 rscreen->screen.get_shader_param = r600_get_shader_param;
1289 rscreen->screen.get_paramf = r600_get_paramf;
1290 rscreen->screen.get_compute_param = r600_get_compute_param;
1291 rscreen->screen.get_timestamp = r600_get_timestamp;
1292
1293 if (rscreen->chip_class >= EVERGREEN) {
1294 rscreen->screen.is_format_supported = evergreen_is_format_supported;
1295 rscreen->dma_blit = &evergreen_dma_blit;
1296 } else {
1297 rscreen->screen.is_format_supported = r600_is_format_supported;
1298 rscreen->dma_blit = &r600_dma_blit;
1299 }
1300 rscreen->screen.context_create = r600_create_context;
1301 rscreen->screen.fence_reference = r600_fence_reference;
1302 rscreen->screen.fence_signalled = r600_fence_signalled;
1303 rscreen->screen.fence_finish = r600_fence_finish;
1304 rscreen->screen.get_driver_query_info = r600_get_driver_query_info;
1305
1306 if (rscreen->info.has_uvd) {
1307 rscreen->screen.get_video_param = r600_uvd_get_video_param;
1308 rscreen->screen.is_video_format_supported = ruvd_is_format_supported;
1309 } else {
1310 rscreen->screen.get_video_param = r600_get_video_param;
1311 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
1312 }
1313
1314 r600_init_screen_resource_functions(&rscreen->screen);
1315
1316 util_format_s3tc_init();
1317
1318 rscreen->fences.bo = NULL;
1319 rscreen->fences.data = NULL;
1320 rscreen->fences.next_index = 0;
1321 LIST_INITHEAD(&rscreen->fences.pool);
1322 LIST_INITHEAD(&rscreen->fences.blocks);
1323 pipe_mutex_init(rscreen->fences.mutex);
1324
1325 rscreen->global_pool = compute_memory_pool_new(rscreen);
1326
1327 rscreen->cs_count = 0;
1328 if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
1329 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->screen,
1330 PIPE_BIND_CUSTOM,
1331 PIPE_USAGE_STAGING,
1332 4096);
1333 if (rscreen->trace_bo) {
1334 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
1335 PIPE_TRANSFER_UNSYNCHRONIZED);
1336 }
1337 }
1338
1339 /* Create the auxiliary context. */
1340 pipe_mutex_init(rscreen->aux_context_lock);
1341 rscreen->aux_context = rscreen->screen.context_create(&rscreen->screen, NULL);
1342
1343 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
1344 struct pipe_resource templ = {};
1345
1346 templ.width0 = 4;
1347 templ.height0 = 2048;
1348 templ.depth0 = 1;
1349 templ.array_size = 1;
1350 templ.target = PIPE_TEXTURE_2D;
1351 templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1352 templ.usage = PIPE_USAGE_STATIC;
1353
1354 struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
1355 unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
1356
1357 memset(map, 0, 256);
1358
1359 r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
1360 r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
1361 r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
1362 r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
1363 r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
1364
1365 ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
1366
1367 int i;
1368 for (i = 0; i < 256; i++) {
1369 printf("%02X", map[i]);
1370 if (i % 16 == 15)
1371 printf("\n");
1372 }
1373 #endif
1374
1375 return &rscreen->screen;
1376 }