src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25
  26 #include <errno.h>
  27 #include "pipe/p_shader_tokens.h"
  28 #include "util/u_blitter.h"
  29 #include "util/u_format_s3tc.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_simple_shaders.h"
  32 #include "util/u_upload_mgr.h"
  33 #include "vl/vl_decoder.h"
  34 #include "vl/vl_video_buffer.h"
  35 #include "os/os_time.h"
  36
  37 /*
  38  * pipe_context
  39  */
  40 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  41 {
  42         struct r600_screen *rscreen = rctx->screen;
  43         struct r600_fence *fence = NULL;
  44
  45         pipe_mutex_lock(rscreen->fences.mutex);
  46
  47         if (!rscreen->fences.bo) {
  48                 /* Create the shared buffer object */
  49                 rscreen->fences.bo = (struct r600_resource*)
  50                         pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
  51                                            PIPE_USAGE_STAGING, 4096);
  52                 if (!rscreen->fences.bo) {
  53                         R600_ERR("r600: failed to create bo for fence objects\n");
  54                         goto out;
  55                 }
  56                 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf,
  57                                                            rctx->cs,
  58                                                            PIPE_TRANSFER_READ_WRITE);
  59         }
  60
  61         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  62                 struct r600_fence *entry;
  63
  64                 /* Try to find a freed fence that has been signalled */
  65                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  66                         if (rscreen->fences.data[entry->index] != 0) {
  67                                 LIST_DELINIT(&entry->head);
  68                                 fence = entry;
  69                                 break;
  70                         }
  71                 }
  72         }
  73
  74         if (!fence) {
  75                 /* Allocate a new fence */
  76                 struct r600_fence_block *block;
  77                 unsigned index;
  78
  79                 if ((rscreen->fences.next_index + 1) >= 1024) {
  80                         R600_ERR("r600: too many concurrent fences\n");
  81                         goto out;
  82                 }
  83
  84                 index = rscreen->fences.next_index++;
  85
  86                 if (!(index % FENCE_BLOCK_SIZE)) {
  87                         /* Allocate a new block */
  88                         block = CALLOC_STRUCT(r600_fence_block);
  89                         if (block == NULL)
  90                                 goto out;
  91
  92                         LIST_ADD(&block->head, &rscreen->fences.blocks);
  93                 } else {
  94                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
  95                 }
  96
  97                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
  98                 fence->index = index;
  99         }
 100
 101         pipe_reference_init(&fence->reference, 1);
 102
 103         rscreen->fences.data[fence->index] = 0;
 104         r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 105
 106         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 107         fence->sleep_bo = (struct r600_resource*)
 108                         pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
 109                                            PIPE_USAGE_STAGING, 1);
 110         /* Add the fence as a dummy relocation. */
 111         r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 112
 113 out:
 114         pipe_mutex_unlock(rscreen->fences.mutex);
 115         return fence;
 116 }
 117
 118
 119 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 120                 unsigned flags)
 121 {
 122         struct r600_context *rctx = (struct r600_context *)ctx;
 123         struct r600_fence **rfence = (struct r600_fence**)fence;
 124         struct pipe_query *render_cond = NULL;
 125         unsigned render_cond_mode = 0;
 126
 127         if (rfence)
 128                 *rfence = r600_create_fence(rctx);
 129
 130         /* Disable render condition. */
 131         if (rctx->current_render_cond) {
 132                 render_cond = rctx->current_render_cond;
 133                 render_cond_mode = rctx->current_render_cond_mode;
 134                 ctx->render_condition(ctx, NULL, 0);
 135         }
 136
 137         r600_context_flush(rctx, flags);
 138
 139         /* Re-enable render condition. */
 140         if (render_cond) {
 141                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 142         }
 143 }
 144
 145 static void r600_flush_from_st(struct pipe_context *ctx,
 146                                struct pipe_fence_handle **fence)
 147 {
 148         r600_flush(ctx, fence, 0);
 149 }
 150
 151 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 152 {
 153         r600_flush((struct pipe_context*)ctx, NULL, flags);
 154 }
 155
 156 static void r600_destroy_context(struct pipe_context *context)
 157 {
 158         struct r600_context *rctx = (struct r600_context *)context;
 159
 160         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
 161         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
 162
 163         if (rctx->dummy_pixel_shader) {
 164                 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 165         }
 166         if (rctx->custom_dsa_flush) {
 167                 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 168         }
 169         if (rctx->custom_blend_resolve) {
 170                 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve);
 171         }
 172         if (rctx->custom_blend_decompress) {
 173                 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_decompress);
 174         }
 175         if (rctx->custom_blend_fmask_decompress) {
 176                 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_fmask_decompress);
 177         }
 178         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 179
 180         r600_context_fini(rctx);
 181
 182         if (rctx->blitter) {
 183                 util_blitter_destroy(rctx->blitter);
 184         }
 185         if (rctx->uploader) {
 186                 u_upload_destroy(rctx->uploader);
 187         }
 188         util_slab_destroy(&rctx->pool_transfers);
 189
 190         r600_release_command_buffer(&rctx->start_cs_cmd);
 191
 192         if (rctx->cs) {
 193                 rctx->ws->cs_destroy(rctx->cs);
 194         }
 195
 196         FREE(rctx->range);
 197         FREE(rctx);
 198 }
 199
 200 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 201 {
 202         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 203         struct r600_screen* rscreen = (struct r600_screen *)screen;
 204
 205         if (rctx == NULL)
 206                 return NULL;
 207
 208         util_slab_create(&rctx->pool_transfers,
 209                          sizeof(struct r600_transfer), 64,
 210                          UTIL_SLAB_SINGLETHREADED);
 211
 212         rctx->context.screen = screen;
 213         rctx->context.priv = priv;
 214         rctx->context.destroy = r600_destroy_context;
 215         rctx->context.flush = r600_flush_from_st;
 216
 217         /* Easy accessing of screen/winsys. */
 218         rctx->screen = rscreen;
 219         rctx->ws = rscreen->ws;
 220         rctx->family = rscreen->family;
 221         rctx->chip_class = rscreen->chip_class;
 222         rctx->keep_tiling_flags = rscreen->info.drm_minor >= 12;
 223
 224         LIST_INITHEAD(&rctx->active_timer_queries);
 225         LIST_INITHEAD(&rctx->active_nontimer_queries);
 226         LIST_INITHEAD(&rctx->dirty);
 227         LIST_INITHEAD(&rctx->enable_list);
 228
 229         rctx->range = CALLOC(NUM_RANGES, sizeof(struct r600_range));
 230         if (!rctx->range)
 231                 goto fail;
 232
 233         r600_init_blit_functions(rctx);
 234         r600_init_query_functions(rctx);
 235         r600_init_context_resource_functions(rctx);
 236         r600_init_surface_functions(rctx);
 237
 238
 239         rctx->context.create_video_decoder = vl_create_decoder;
 240         rctx->context.create_video_buffer = vl_video_buffer_create;
 241
 242         r600_init_common_state_functions(rctx);
 243
 244         switch (rctx->chip_class) {
 245         case R600:
 246         case R700:
 247                 r600_init_state_functions(rctx);
 248                 r600_init_atom_start_cs(rctx);
 249                 if (r600_context_init(rctx))
 250                         goto fail;
 251                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 252                 rctx->custom_blend_resolve = rctx->chip_class == R700 ? r700_create_resolve_blend(rctx)
 253                                                                       : r600_create_resolve_blend(rctx);
 254                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 255                 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
 256                                            rctx->family == CHIP_RV620 ||
 257                                            rctx->family == CHIP_RS780 ||
 258                                            rctx->family == CHIP_RS880 ||
 259                                            rctx->family == CHIP_RV710);
 260                 break;
 261         case EVERGREEN:
 262         case CAYMAN:
 263                 evergreen_init_state_functions(rctx);
 264                 evergreen_init_atom_start_cs(rctx);
 265                 evergreen_init_atom_start_compute_cs(rctx);
 266                 if (evergreen_context_init(rctx))
 267                         goto fail;
 268                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 269                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 270                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 271                 rctx->custom_blend_fmask_decompress = evergreen_create_fmask_decompress_blend(rctx);
 272                 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
 273                                            rctx->family == CHIP_PALM ||
 274                                            rctx->family == CHIP_SUMO ||
 275                                            rctx->family == CHIP_SUMO2 ||
 276                                            rctx->family == CHIP_CAICOS ||
 277                                            rctx->family == CHIP_CAYMAN ||
 278                                            rctx->family == CHIP_ARUBA);
 279                 break;
 280         default:
 281                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 282                 goto fail;
 283         }
 284
 285         rctx->cs = rctx->ws->cs_create(rctx->ws);
 286         rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
 287
 288         rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
 289                                          PIPE_BIND_INDEX_BUFFER |
 290                                          PIPE_BIND_CONSTANT_BUFFER);
 291         if (!rctx->uploader)
 292                 goto fail;
 293
 294         rctx->blitter = util_blitter_create(&rctx->context);
 295         if (rctx->blitter == NULL)
 296                 goto fail;
 297         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 298         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 299
 300         r600_begin_new_cs(rctx);
 301         r600_get_backend_mask(rctx); /* this emits commands and must be last */
 302
 303         rctx->dummy_pixel_shader =
 304                 util_make_fragment_cloneinput_shader(&rctx->context, 0,
 305                                                      TGSI_SEMANTIC_GENERIC,
 306                                                      TGSI_INTERPOLATE_CONSTANT);
 307         rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 308
 309         return &rctx->context;
 310
 311 fail:
 312         r600_destroy_context(&rctx->context);
 313         return NULL;
 314 }
 315
 316 /*
 317  * pipe_screen
 318  */
 319 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 320 {
 321         return "X.Org";
 322 }
 323
 324 static const char *r600_get_family_name(enum radeon_family family)
 325 {
 326         switch(family) {
 327         case CHIP_R600: return "AMD R600";
 328         case CHIP_RV610: return "AMD RV610";
 329         case CHIP_RV630: return "AMD RV630";
 330         case CHIP_RV670: return "AMD RV670";
 331         case CHIP_RV620: return "AMD RV620";
 332         case CHIP_RV635: return "AMD RV635";
 333         case CHIP_RS780: return "AMD RS780";
 334         case CHIP_RS880: return "AMD RS880";
 335         case CHIP_RV770: return "AMD RV770";
 336         case CHIP_RV730: return "AMD RV730";
 337         case CHIP_RV710: return "AMD RV710";
 338         case CHIP_RV740: return "AMD RV740";
 339         case CHIP_CEDAR: return "AMD CEDAR";
 340         case CHIP_REDWOOD: return "AMD REDWOOD";
 341         case CHIP_JUNIPER: return "AMD JUNIPER";
 342         case CHIP_CYPRESS: return "AMD CYPRESS";
 343         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 344         case CHIP_PALM: return "AMD PALM";
 345         case CHIP_SUMO: return "AMD SUMO";
 346         case CHIP_SUMO2: return "AMD SUMO2";
 347         case CHIP_BARTS: return "AMD BARTS";
 348         case CHIP_TURKS: return "AMD TURKS";
 349         case CHIP_CAICOS: return "AMD CAICOS";
 350         case CHIP_CAYMAN: return "AMD CAYMAN";
 351         case CHIP_ARUBA: return "AMD ARUBA";
 352         default: return "AMD unknown";
 353         }
 354 }
 355
 356 static const char* r600_get_name(struct pipe_screen* pscreen)
 357 {
 358         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 359
 360         return r600_get_family_name(rscreen->family);
 361 }
 362
 363 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 364 {
 365         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 366         enum radeon_family family = rscreen->family;
 367
 368         switch (param) {
 369         /* Supported features (boolean caps). */
 370         case PIPE_CAP_NPOT_TEXTURES:
 371         case PIPE_CAP_TWO_SIDED_STENCIL:
 372         case PIPE_CAP_ANISOTROPIC_FILTER:
 373         case PIPE_CAP_POINT_SPRITE:
 374         case PIPE_CAP_OCCLUSION_QUERY:
 375         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 376         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 377         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 378         case PIPE_CAP_TEXTURE_SWIZZLE:
 379         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 380         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 381         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 382         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 383         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 384         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 385         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 386         case PIPE_CAP_SM3:
 387         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 388         case PIPE_CAP_PRIMITIVE_RESTART:
 389         case PIPE_CAP_CONDITIONAL_RENDER:
 390         case PIPE_CAP_TEXTURE_BARRIER:
 391         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 392         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 393         case PIPE_CAP_TGSI_INSTANCEID:
 394         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 395         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 396         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 397         case PIPE_CAP_USER_INDEX_BUFFERS:
 398         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 399         case PIPE_CAP_COMPUTE:
 400         case PIPE_CAP_START_INSTANCE:
 401         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 402                 return 1;
 403
 404         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 405                 return R600_MAP_BUFFER_ALIGNMENT;
 406
 407         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 408                 return 256;
 409
 410         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 411                 return 130;
 412
 413         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 414                 return rscreen->msaa_texture_support != MSAA_TEXTURE_SAMPLE_ZERO;
 415
 416         /* Supported except the original R600. */
 417         case PIPE_CAP_INDEP_BLEND_ENABLE:
 418         case PIPE_CAP_INDEP_BLEND_FUNC:
 419                 /* R600 doesn't support per-MRT blends */
 420                 return family == CHIP_R600 ? 0 : 1;
 421
 422         /* Supported on Evergreen. */
 423         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 424         case PIPE_CAP_CUBE_MAP_ARRAY:
 425                 return family >= CHIP_CEDAR ? 1 : 0;
 426
 427         /* Unsupported features. */
 428         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 429         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 430         case PIPE_CAP_SCALED_RESOLVE:
 431         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 432         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 433         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 434         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 435         case PIPE_CAP_USER_VERTEX_BUFFERS:
 436         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 437                 return 0;
 438
 439         /* Stream output. */
 440         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 441                 return rscreen->has_streamout ? 4 : 0;
 442         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 443                 return rscreen->has_streamout ? 1 : 0;
 444         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 445         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 446                 return 32*4;
 447
 448         /* Texturing. */
 449         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 450         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 451         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 452                 if (family >= CHIP_CEDAR)
 453                         return 15;
 454                 else
 455                         return 14;
 456         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 457                 return rscreen->info.drm_minor >= 9 ?
 458                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 459         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 460                 return 32;
 461
 462         /* Render targets. */
 463         case PIPE_CAP_MAX_RENDER_TARGETS:
 464                 /* XXX some r6xx are buggy and can only do 4 */
 465                 return 8;
 466
 467         /* Timer queries, present when the clock frequency is non zero. */
 468         case PIPE_CAP_TIMER_QUERY:
 469                 return rscreen->info.r600_clock_crystal_freq != 0;
 470         case PIPE_CAP_QUERY_TIMESTAMP:
 471                 return rscreen->info.drm_minor >= 20 &&
 472                        rscreen->info.r600_clock_crystal_freq != 0;
 473
 474         case PIPE_CAP_MIN_TEXEL_OFFSET:
 475                 return -8;
 476
 477         case PIPE_CAP_MAX_TEXEL_OFFSET:
 478                 return 7;
 479         }
 480         return 0;
 481 }
 482
 483 static float r600_get_paramf(struct pipe_screen* pscreen,
 484                              enum pipe_capf param)
 485 {
 486         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 487         enum radeon_family family = rscreen->family;
 488
 489         switch (param) {
 490         case PIPE_CAPF_MAX_LINE_WIDTH:
 491         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 492         case PIPE_CAPF_MAX_POINT_WIDTH:
 493         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 494                 if (family >= CHIP_CEDAR)
 495                         return 16384.0f;
 496                 else
 497                         return 8192.0f;
 498         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 499                 return 16.0f;
 500         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 501                 return 16.0f;
 502         case PIPE_CAPF_GUARD_BAND_LEFT:
 503         case PIPE_CAPF_GUARD_BAND_TOP:
 504         case PIPE_CAPF_GUARD_BAND_RIGHT:
 505         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 506                 return 0.0f;
 507         }
 508         return 0.0f;
 509 }
 510
 511 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 512 {
 513         switch(shader)
 514         {
 515         case PIPE_SHADER_FRAGMENT:
 516         case PIPE_SHADER_VERTEX:
 517         case PIPE_SHADER_COMPUTE:
 518                 break;
 519         case PIPE_SHADER_GEOMETRY:
 520                 /* XXX: support and enable geometry programs */
 521                 return 0;
 522         default:
 523                 /* XXX: support tessellation on Evergreen */
 524                 return 0;
 525         }
 526
 527         /* XXX: all these should be fixed, since r600 surely supports much more! */
 528         switch (param) {
 529         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 530         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 531         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 532         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 533                 return 16384;
 534         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 535                 return 8; /* XXX */
 536         case PIPE_SHADER_CAP_MAX_INPUTS:
 537                 return 32;
 538         case PIPE_SHADER_CAP_MAX_TEMPS:
 539                 return 256; /* Max native temporaries. */
 540         case PIPE_SHADER_CAP_MAX_ADDRS:
 541                 /* XXX Isn't this equal to TEMPS? */
 542                 return 1; /* Max native address registers */
 543         case PIPE_SHADER_CAP_MAX_CONSTS:
 544                 return R600_MAX_CONST_BUFFER_SIZE;
 545         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 546                 return R600_MAX_USER_CONST_BUFFERS;
 547         case PIPE_SHADER_CAP_MAX_PREDS:
 548                 return 0; /* nothing uses this */
 549         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 550                 return 1;
 551         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 552         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 553         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 554         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 555                 return 1;
 556         case PIPE_SHADER_CAP_SUBROUTINES:
 557                 return 0;
 558         case PIPE_SHADER_CAP_INTEGERS:
 559                 return 1;
 560         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 561                 return 16;
 562         case PIPE_SHADER_CAP_PREFERRED_IR:
 563                 if (shader == PIPE_SHADER_COMPUTE) {
 564                         return PIPE_SHADER_IR_LLVM;
 565                 } else {
 566                         return PIPE_SHADER_IR_TGSI;
 567                 }
 568         }
 569         return 0;
 570 }
 571
 572 static int r600_get_video_param(struct pipe_screen *screen,
 573                                 enum pipe_video_profile profile,
 574                                 enum pipe_video_cap param)
 575 {
 576         switch (param) {
 577         case PIPE_VIDEO_CAP_SUPPORTED:
 578                 return vl_profile_supported(screen, profile);
 579         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 580                 return 1;
 581         case PIPE_VIDEO_CAP_MAX_WIDTH:
 582         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 583                 return vl_video_buffer_max_size(screen);
 584         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 585                 return PIPE_FORMAT_NV12;
 586         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 587                 return false;
 588         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 589                 return false;
 590         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 591                 return true;
 592         default:
 593                 return 0;
 594         }
 595 }
 596
 597 static int r600_get_compute_param(struct pipe_screen *screen,
 598         enum pipe_compute_cap param,
 599         void *ret)
 600 {
 601         //TODO: select these params by asic
 602         switch (param) {
 603         case PIPE_COMPUTE_CAP_IR_TARGET:
 604                 if (ret) {
 605                         strcpy(ret, "r600--");
 606                 }
 607                 return 7 * sizeof(char);
 608
 609         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 610                 if (ret) {
 611                         uint64_t * grid_dimension = ret;
 612                         grid_dimension[0] = 3;
 613                 }
 614                 return 1 * sizeof(uint64_t);
 615
 616         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 617                 if (ret) {
 618                         uint64_t * grid_size = ret;
 619                         grid_size[0] = 65535;
 620                         grid_size[1] = 65535;
 621                         grid_size[2] = 1;
 622                 }
 623                 return 3 * sizeof(uint64_t) ;
 624
 625         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 626                 if (ret) {
 627                         uint64_t * block_size = ret;
 628                         block_size[0] = 256;
 629                         block_size[1] = 256;
 630                         block_size[2] = 256;
 631                 }
 632                 return 3 * sizeof(uint64_t);
 633
 634         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 635                 if (ret) {
 636                         uint64_t * max_threads_per_block = ret;
 637                         *max_threads_per_block = 256;
 638                 }
 639                 return sizeof(uint64_t);
 640
 641         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 642                 if (ret) {
 643                         uint64_t * max_global_size = ret;
 644                         /* XXX: This is what the proprietary driver reports, we
 645                          * may want to use a different value. */
 646                         *max_global_size = 201326592;
 647                 }
 648                 return sizeof(uint64_t);
 649
 650         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 651                 if (ret) {
 652                         uint64_t * max_input_size = ret;
 653                         *max_input_size = 1024;
 654                 }
 655                 return sizeof(uint64_t);
 656
 657         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 658                 if (ret) {
 659                         uint64_t * max_local_size = ret;
 660                         /* XXX: This is what the proprietary driver reports, we
 661                          * may want to use a different value. */
 662                         *max_local_size = 32768;
 663                 }
 664                 return sizeof(uint64_t);
 665
 666         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 667                 if (ret) {
 668                         uint64_t max_global_size;
 669                         uint64_t * max_mem_alloc_size = ret;
 670                         r600_get_compute_param(screen,
 671                                         PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
 672                                         &max_global_size);
 673                         /* OpenCL requres this value be at least
 674                          * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
 675                          * I'm really not sure what value to report here, but
 676                          * MAX_GLOBAL_SIZE / 4 seems resonable.
 677                          */
 678                         *max_mem_alloc_size = max_global_size / 4;
 679                 }
 680                 return sizeof(uint64_t);
 681
 682         default:
 683                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 684                 return 0;
 685         }
 686 }
 687
 688 static void r600_destroy_screen(struct pipe_screen* pscreen)
 689 {
 690         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 691
 692         if (rscreen == NULL)
 693                 return;
 694
 695         if (rscreen->global_pool) {
 696                 compute_memory_pool_delete(rscreen->global_pool);
 697         }
 698
 699         if (rscreen->fences.bo) {
 700                 struct r600_fence_block *entry, *tmp;
 701
 702                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 703                         LIST_DEL(&entry->head);
 704                         FREE(entry);
 705                 }
 706
 707                 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
 708                 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
 709         }
 710         pipe_mutex_destroy(rscreen->fences.mutex);
 711
 712         rscreen->ws->destroy(rscreen->ws);
 713         FREE(rscreen);
 714 }
 715
 716 static void r600_fence_reference(struct pipe_screen *pscreen,
 717                                  struct pipe_fence_handle **ptr,
 718                                  struct pipe_fence_handle *fence)
 719 {
 720         struct r600_fence **oldf = (struct r600_fence**)ptr;
 721         struct r600_fence *newf = (struct r600_fence*)fence;
 722
 723         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 724                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 725                 pipe_mutex_lock(rscreen->fences.mutex);
 726                 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
 727                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 728                 pipe_mutex_unlock(rscreen->fences.mutex);
 729         }
 730
 731         *ptr = fence;
 732 }
 733
 734 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 735                                     struct pipe_fence_handle *fence)
 736 {
 737         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 738         struct r600_fence *rfence = (struct r600_fence*)fence;
 739
 740         return rscreen->fences.data[rfence->index];
 741 }
 742
 743 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 744                                  struct pipe_fence_handle *fence,
 745                                  uint64_t timeout)
 746 {
 747         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 748         struct r600_fence *rfence = (struct r600_fence*)fence;
 749         int64_t start_time = 0;
 750         unsigned spins = 0;
 751
 752         if (timeout != PIPE_TIMEOUT_INFINITE) {
 753                 start_time = os_time_get();
 754
 755                 /* Convert to microseconds. */
 756                 timeout /= 1000;
 757         }
 758
 759         while (rscreen->fences.data[rfence->index] == 0) {
 760                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
 761                 if (timeout == PIPE_TIMEOUT_INFINITE) {
 762                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
 763                         break;
 764                 }
 765
 766                 /* The dummy BO will be busy until the CS including the fence has completed, or
 767                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
 768                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
 769                         break;
 770
 771                 if (++spins % 256)
 772                         continue;
 773 #ifdef PIPE_OS_UNIX
 774                 sched_yield();
 775 #else
 776                 os_time_sleep(10);
 777 #endif
 778                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 779                     os_time_get() - start_time >= timeout) {
 780                         break;
 781                 }
 782         }
 783
 784         return rscreen->fences.data[rfence->index] != 0;
 785 }
 786
 787 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 788 {
 789         switch ((tiling_config & 0xe) >> 1) {
 790         case 0:
 791                 rscreen->tiling_info.num_channels = 1;
 792                 break;
 793         case 1:
 794                 rscreen->tiling_info.num_channels = 2;
 795                 break;
 796         case 2:
 797                 rscreen->tiling_info.num_channels = 4;
 798                 break;
 799         case 3:
 800                 rscreen->tiling_info.num_channels = 8;
 801                 break;
 802         default:
 803                 return -EINVAL;
 804         }
 805
 806         switch ((tiling_config & 0x30) >> 4) {
 807         case 0:
 808                 rscreen->tiling_info.num_banks = 4;
 809                 break;
 810         case 1:
 811                 rscreen->tiling_info.num_banks = 8;
 812                 break;
 813         default:
 814                 return -EINVAL;
 815
 816         }
 817         switch ((tiling_config & 0xc0) >> 6) {
 818         case 0:
 819                 rscreen->tiling_info.group_bytes = 256;
 820                 break;
 821         case 1:
 822                 rscreen->tiling_info.group_bytes = 512;
 823                 break;
 824         default:
 825                 return -EINVAL;
 826         }
 827         return 0;
 828 }
 829
 830 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 831 {
 832         switch (tiling_config & 0xf) {
 833         case 0:
 834                 rscreen->tiling_info.num_channels = 1;
 835                 break;
 836         case 1:
 837                 rscreen->tiling_info.num_channels = 2;
 838                 break;
 839         case 2:
 840                 rscreen->tiling_info.num_channels = 4;
 841                 break;
 842         case 3:
 843                 rscreen->tiling_info.num_channels = 8;
 844                 break;
 845         default:
 846                 return -EINVAL;
 847         }
 848
 849         switch ((tiling_config & 0xf0) >> 4) {
 850         case 0:
 851                 rscreen->tiling_info.num_banks = 4;
 852                 break;
 853         case 1:
 854                 rscreen->tiling_info.num_banks = 8;
 855                 break;
 856         case 2:
 857                 rscreen->tiling_info.num_banks = 16;
 858                 break;
 859         default:
 860                 return -EINVAL;
 861         }
 862
 863         switch ((tiling_config & 0xf00) >> 8) {
 864         case 0:
 865                 rscreen->tiling_info.group_bytes = 256;
 866                 break;
 867         case 1:
 868                 rscreen->tiling_info.group_bytes = 512;
 869                 break;
 870         default:
 871                 return -EINVAL;
 872         }
 873         return 0;
 874 }
 875
 876 static int r600_init_tiling(struct r600_screen *rscreen)
 877 {
 878         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 879
 880         /* set default group bytes, overridden by tiling info ioctl */
 881         if (rscreen->chip_class <= R700) {
 882                 rscreen->tiling_info.group_bytes = 256;
 883         } else {
 884                 rscreen->tiling_info.group_bytes = 512;
 885         }
 886
 887         if (!tiling_config)
 888                 return 0;
 889
 890         if (rscreen->chip_class <= R700) {
 891                 return r600_interpret_tiling(rscreen, tiling_config);
 892         } else {
 893                 return evergreen_interpret_tiling(rscreen, tiling_config);
 894         }
 895 }
 896
 897 static unsigned radeon_family_from_device(unsigned device)
 898 {
 899         switch (device) {
 900 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 901 #include "pci_ids/r600_pci_ids.h"
 902 #undef CHIPSET
 903         default:
 904                 return CHIP_UNKNOWN;
 905         }
 906 }
 907
 908 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 909 {
 910         struct r600_screen *rscreen = (struct r600_screen*)screen;
 911
 912         return 1000000 * rscreen->ws->query_timestamp(rscreen->ws) /
 913                         rscreen->info.r600_clock_crystal_freq;
 914 }
 915
 916 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 917 {
 918         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 919
 920         if (rscreen == NULL) {
 921                 return NULL;
 922         }
 923
 924         rscreen->ws = ws;
 925         ws->query_info(ws, &rscreen->info);
 926
 927         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 928         if (rscreen->family == CHIP_UNKNOWN) {
 929                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 930                 FREE(rscreen);
 931                 return NULL;
 932         }
 933
 934         /* setup class */
 935         if (rscreen->family >= CHIP_CAYMAN) {
 936                 rscreen->chip_class = CAYMAN;
 937         } else if (rscreen->family >= CHIP_CEDAR) {
 938                 rscreen->chip_class = EVERGREEN;
 939         } else if (rscreen->family >= CHIP_RV770) {
 940                 rscreen->chip_class = R700;
 941         } else {
 942                 rscreen->chip_class = R600;
 943         }
 944
 945         /* Figure out streamout kernel support. */
 946         switch (rscreen->chip_class) {
 947         case R600:
 948                 if (rscreen->family < CHIP_RS780) {
 949                         rscreen->has_streamout = rscreen->info.drm_minor >= 14;
 950                 } else {
 951                         rscreen->has_streamout = rscreen->info.drm_minor >= 23;
 952                 }
 953                 break;
 954         case R700:
 955                 rscreen->has_streamout = rscreen->info.drm_minor >= 17;
 956                 break;
 957         case EVERGREEN:
 958         case CAYMAN:
 959                 rscreen->has_streamout = rscreen->info.drm_minor >= 14;
 960                 break;
 961         }
 962
 963         /* MSAA support. */
 964         switch (rscreen->chip_class) {
 965         case R600:
 966         case R700:
 967                 rscreen->has_msaa = rscreen->info.drm_minor >= 22;
 968                 rscreen->msaa_texture_support = MSAA_TEXTURE_DECOMPRESSED;
 969                 break;
 970         case EVERGREEN:
 971                 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
 972                 rscreen->msaa_texture_support =
 973                         rscreen->info.drm_minor >= 24 ? MSAA_TEXTURE_COMPRESSED :
 974                                                         MSAA_TEXTURE_DECOMPRESSED;
 975                 break;
 976         case CAYMAN:
 977                 rscreen->has_msaa = rscreen->info.drm_minor >= 19;
 978                 /* We should be able to read compressed MSAA textures, but it doesn't work. */
 979                 rscreen->msaa_texture_support = MSAA_TEXTURE_SAMPLE_ZERO;
 980                 break;
 981         }
 982
 983         if (r600_init_tiling(rscreen)) {
 984                 FREE(rscreen);
 985                 return NULL;
 986         }
 987
 988         rscreen->screen.destroy = r600_destroy_screen;
 989         rscreen->screen.get_name = r600_get_name;
 990         rscreen->screen.get_vendor = r600_get_vendor;
 991         rscreen->screen.get_param = r600_get_param;
 992         rscreen->screen.get_shader_param = r600_get_shader_param;
 993         rscreen->screen.get_paramf = r600_get_paramf;
 994         rscreen->screen.get_video_param = r600_get_video_param;
 995         rscreen->screen.get_compute_param = r600_get_compute_param;
 996         rscreen->screen.get_timestamp = r600_get_timestamp;
 997
 998         if (rscreen->chip_class >= EVERGREEN) {
 999                 rscreen->screen.is_format_supported = evergreen_is_format_supported;
1000         } else {
1001                 rscreen->screen.is_format_supported = r600_is_format_supported;
1002         }
1003         rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
1004         rscreen->screen.context_create = r600_create_context;
1005         rscreen->screen.fence_reference = r600_fence_reference;
1006         rscreen->screen.fence_signalled = r600_fence_signalled;
1007         rscreen->screen.fence_finish = r600_fence_finish;
1008         r600_init_screen_resource_functions(&rscreen->screen);
1009
1010         util_format_s3tc_init();
1011
1012         rscreen->fences.bo = NULL;
1013         rscreen->fences.data = NULL;
1014         rscreen->fences.next_index = 0;
1015         LIST_INITHEAD(&rscreen->fences.pool);
1016         LIST_INITHEAD(&rscreen->fences.blocks);
1017         pipe_mutex_init(rscreen->fences.mutex);
1018
1019         rscreen->global_pool = compute_memory_pool_new(rscreen);
1020
1021         return &rscreen->screen;
1022 }