gallium: add PIPE_CAP_CONDITIONAL_RENDER
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "tgsi/tgsi_scan.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31 #include "util/u_blitter.h"
32 #include "util/u_double_list.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_transfer.h"
36 #include "util/u_surface.h"
37 #include "util/u_pack_color.h"
38 #include "util/u_memory.h"
39 #include "util/u_inlines.h"
40 #include "util/u_upload_mgr.h"
41 #include "vl/vl_decoder.h"
42 #include "vl/vl_video_buffer.h"
43 #include "os/os_time.h"
44 #include "pipebuffer/pb_buffer.h"
45 #include "r600.h"
46 #include "r600d.h"
47 #include "r600_resource.h"
48 #include "r600_shader.h"
49 #include "r600_pipe.h"
50
51 /*
52 * pipe_context
53 */
54 static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx)
55 {
56 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
57 struct r600_fence *fence = NULL;
58
59 if (!ctx->fences.bo) {
60 /* Create the shared buffer object */
61 ctx->fences.bo = r600_bo(ctx->radeon, 4096, 0, 0, 0);
62 if (!ctx->fences.bo) {
63 R600_ERR("r600: failed to create bo for fence objects\n");
64 return NULL;
65 }
66 ctx->fences.data = r600_bo_map(ctx->radeon, ctx->fences.bo, rctx->ctx.cs,
67 PIPE_TRANSFER_UNSYNCHRONIZED | PIPE_TRANSFER_WRITE);
68 }
69
70 if (!LIST_IS_EMPTY(&ctx->fences.pool)) {
71 struct r600_fence *entry;
72
73 /* Try to find a freed fence that has been signalled */
74 LIST_FOR_EACH_ENTRY(entry, &ctx->fences.pool, head) {
75 if (ctx->fences.data[entry->index] != 0) {
76 LIST_DELINIT(&entry->head);
77 fence = entry;
78 break;
79 }
80 }
81 }
82
83 if (!fence) {
84 /* Allocate a new fence */
85 struct r600_fence_block *block;
86 unsigned index;
87
88 if ((ctx->fences.next_index + 1) >= 1024) {
89 R600_ERR("r600: too many concurrent fences\n");
90 return NULL;
91 }
92
93 index = ctx->fences.next_index++;
94
95 if (!(index % FENCE_BLOCK_SIZE)) {
96 /* Allocate a new block */
97 block = CALLOC_STRUCT(r600_fence_block);
98 if (block == NULL)
99 return NULL;
100
101 LIST_ADD(&block->head, &ctx->fences.blocks);
102 } else {
103 block = LIST_ENTRY(struct r600_fence_block, ctx->fences.blocks.next, head);
104 }
105
106 fence = &block->fences[index % FENCE_BLOCK_SIZE];
107 fence->ctx = ctx;
108 fence->index = index;
109 }
110
111 pipe_reference_init(&fence->reference, 1);
112
113 ctx->fences.data[fence->index] = 0;
114 r600_context_emit_fence(&ctx->ctx, ctx->fences.bo, fence->index, 1);
115 return fence;
116 }
117
118
119 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
120 unsigned flags)
121 {
122 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
123 struct r600_fence **rfence = (struct r600_fence**)fence;
124
125 if (rfence)
126 *rfence = r600_create_fence(rctx);
127
128 r600_context_flush(&rctx->ctx, flags);
129 }
130
131 static void r600_flush_from_st(struct pipe_context *ctx,
132 struct pipe_fence_handle **fence)
133 {
134 r600_flush(ctx, fence, 0);
135 }
136
137 static void r600_flush_from_winsys(void *ctx, unsigned flags)
138 {
139 r600_flush((struct pipe_context*)ctx, NULL, flags);
140 }
141
142 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
143 {
144 pipe_mutex_lock(rscreen->mutex_num_contexts);
145 if (diff > 0) {
146 rscreen->num_contexts++;
147
148 if (rscreen->num_contexts > 1)
149 util_slab_set_thread_safety(&rscreen->pool_buffers,
150 UTIL_SLAB_MULTITHREADED);
151 } else {
152 rscreen->num_contexts--;
153
154 if (rscreen->num_contexts <= 1)
155 util_slab_set_thread_safety(&rscreen->pool_buffers,
156 UTIL_SLAB_SINGLETHREADED);
157 }
158 pipe_mutex_unlock(rscreen->mutex_num_contexts);
159 }
160
161 static void r600_destroy_context(struct pipe_context *context)
162 {
163 struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
164
165 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
166 util_unreference_framebuffer_state(&rctx->framebuffer);
167
168 r600_context_fini(&rctx->ctx);
169
170 util_blitter_destroy(rctx->blitter);
171
172 for (int i = 0; i < R600_PIPE_NSTATES; i++) {
173 free(rctx->states[i]);
174 }
175
176 u_vbuf_destroy(rctx->vbuf_mgr);
177 util_slab_destroy(&rctx->pool_transfers);
178
179 if (rctx->fences.bo) {
180 struct r600_fence_block *entry, *tmp;
181
182 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rctx->fences.blocks, head) {
183 LIST_DEL(&entry->head);
184 FREE(entry);
185 }
186
187 r600_bo_unmap(rctx->radeon, rctx->fences.bo);
188 r600_bo_reference(&rctx->fences.bo, NULL);
189 }
190
191 r600_update_num_contexts(rctx->screen, -1);
192
193 FREE(rctx);
194 }
195
196 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
197 {
198 struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
199 struct r600_screen* rscreen = (struct r600_screen *)screen;
200
201 if (rctx == NULL)
202 return NULL;
203
204 r600_update_num_contexts(rscreen, 1);
205
206 rctx->context.winsys = rscreen->screen.winsys;
207 rctx->context.screen = screen;
208 rctx->context.priv = priv;
209 rctx->context.destroy = r600_destroy_context;
210 rctx->context.flush = r600_flush_from_st;
211
212 /* Easy accessing of screen/winsys. */
213 rctx->screen = rscreen;
214 rctx->radeon = rscreen->radeon;
215 rctx->family = r600_get_family(rctx->radeon);
216 rctx->chip_class = r600_get_family_class(rctx->radeon);
217
218 rctx->fences.bo = NULL;
219 rctx->fences.data = NULL;
220 rctx->fences.next_index = 0;
221 LIST_INITHEAD(&rctx->fences.pool);
222 LIST_INITHEAD(&rctx->fences.blocks);
223
224 r600_init_blit_functions(rctx);
225 r600_init_query_functions(rctx);
226 r600_init_context_resource_functions(rctx);
227 r600_init_surface_functions(rctx);
228 rctx->context.draw_vbo = r600_draw_vbo;
229
230 rctx->context.create_video_decoder = vl_create_decoder;
231 rctx->context.create_video_buffer = vl_video_buffer_create;
232
233 switch (rctx->chip_class) {
234 case R600:
235 case R700:
236 r600_init_state_functions(rctx);
237 if (r600_context_init(&rctx->ctx, rctx->radeon)) {
238 r600_destroy_context(&rctx->context);
239 return NULL;
240 }
241 r600_init_config(rctx);
242 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
243 break;
244 case EVERGREEN:
245 case CAYMAN:
246 evergreen_init_state_functions(rctx);
247 if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
248 r600_destroy_context(&rctx->context);
249 return NULL;
250 }
251 evergreen_init_config(rctx);
252 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
253 break;
254 default:
255 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
256 r600_destroy_context(&rctx->context);
257 return NULL;
258 }
259
260 rctx->screen->ws->cs_set_flush_callback(rctx->ctx.cs, r600_flush_from_winsys, rctx);
261
262 util_slab_create(&rctx->pool_transfers,
263 sizeof(struct pipe_transfer), 64,
264 UTIL_SLAB_SINGLETHREADED);
265
266 rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256,
267 PIPE_BIND_VERTEX_BUFFER |
268 PIPE_BIND_INDEX_BUFFER |
269 PIPE_BIND_CONSTANT_BUFFER,
270 U_VERTEX_FETCH_DWORD_ALIGNED);
271 if (!rctx->vbuf_mgr) {
272 r600_destroy_context(&rctx->context);
273 return NULL;
274 }
275 rctx->vbuf_mgr->caps.format_fixed32 = 0;
276
277 rctx->blitter = util_blitter_create(&rctx->context);
278 if (rctx->blitter == NULL) {
279 r600_destroy_context(&rctx->context);
280 return NULL;
281 }
282
283 return &rctx->context;
284 }
285
286 /*
287 * pipe_screen
288 */
289 static const char* r600_get_vendor(struct pipe_screen* pscreen)
290 {
291 return "X.Org";
292 }
293
294 static const char *r600_get_family_name(enum radeon_family family)
295 {
296 switch(family) {
297 case CHIP_R600: return "AMD R600";
298 case CHIP_RV610: return "AMD RV610";
299 case CHIP_RV630: return "AMD RV630";
300 case CHIP_RV670: return "AMD RV670";
301 case CHIP_RV620: return "AMD RV620";
302 case CHIP_RV635: return "AMD RV635";
303 case CHIP_RS780: return "AMD RS780";
304 case CHIP_RS880: return "AMD RS880";
305 case CHIP_RV770: return "AMD RV770";
306 case CHIP_RV730: return "AMD RV730";
307 case CHIP_RV710: return "AMD RV710";
308 case CHIP_RV740: return "AMD RV740";
309 case CHIP_CEDAR: return "AMD CEDAR";
310 case CHIP_REDWOOD: return "AMD REDWOOD";
311 case CHIP_JUNIPER: return "AMD JUNIPER";
312 case CHIP_CYPRESS: return "AMD CYPRESS";
313 case CHIP_HEMLOCK: return "AMD HEMLOCK";
314 case CHIP_PALM: return "AMD PALM";
315 case CHIP_SUMO: return "AMD SUMO";
316 case CHIP_SUMO2: return "AMD SUMO2";
317 case CHIP_BARTS: return "AMD BARTS";
318 case CHIP_TURKS: return "AMD TURKS";
319 case CHIP_CAICOS: return "AMD CAICOS";
320 case CHIP_CAYMAN: return "AMD CAYMAN";
321 default: return "AMD unknown";
322 }
323 }
324
325 static const char* r600_get_name(struct pipe_screen* pscreen)
326 {
327 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
328 enum radeon_family family = r600_get_family(rscreen->radeon);
329
330 return r600_get_family_name(family);
331 }
332
333 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
334 {
335 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
336 enum radeon_family family = r600_get_family(rscreen->radeon);
337
338 switch (param) {
339 /* Supported features (boolean caps). */
340 case PIPE_CAP_NPOT_TEXTURES:
341 case PIPE_CAP_TWO_SIDED_STENCIL:
342 case PIPE_CAP_GLSL:
343 case PIPE_CAP_DUAL_SOURCE_BLEND:
344 case PIPE_CAP_ANISOTROPIC_FILTER:
345 case PIPE_CAP_POINT_SPRITE:
346 case PIPE_CAP_OCCLUSION_QUERY:
347 case PIPE_CAP_TEXTURE_SHADOW_MAP:
348 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
349 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
350 case PIPE_CAP_TEXTURE_SWIZZLE:
351 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
352 case PIPE_CAP_DEPTH_CLAMP:
353 case PIPE_CAP_SHADER_STENCIL_EXPORT:
354 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
355 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
356 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
357 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
358 case PIPE_CAP_SM3:
359 case PIPE_CAP_SEAMLESS_CUBE_MAP:
360 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
361 case PIPE_CAP_PRIMITIVE_RESTART:
362 case PIPE_CAP_CONDITIONAL_RENDER:
363 return 1;
364
365 /* Supported except the original R600. */
366 case PIPE_CAP_INDEP_BLEND_ENABLE:
367 case PIPE_CAP_INDEP_BLEND_FUNC:
368 /* R600 doesn't support per-MRT blends */
369 return family == CHIP_R600 ? 0 : 1;
370
371 /* Supported on Evergreen. */
372 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
373 return family >= CHIP_CEDAR ? 1 : 0;
374
375 /* Unsupported features. */
376 case PIPE_CAP_STREAM_OUTPUT:
377 case PIPE_CAP_TGSI_INSTANCEID:
378 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
379 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
380 return 0;
381
382 /* Texturing. */
383 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
384 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
385 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
386 if (family >= CHIP_CEDAR)
387 return 15;
388 else
389 return 14;
390 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
391 return rscreen->info.drm_minor >= 9 ?
392 (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
393 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
394 return 32;
395
396 /* Render targets. */
397 case PIPE_CAP_MAX_RENDER_TARGETS:
398 /* FIXME some r6xx are buggy and can only do 4 */
399 return 8;
400
401 /* Timer queries, present when the clock frequency is non zero. */
402 case PIPE_CAP_TIMER_QUERY:
403 return rscreen->info.r600_clock_crystal_freq != 0;
404
405 case PIPE_CAP_MIN_TEXEL_OFFSET:
406 return -8;
407
408 case PIPE_CAP_MAX_TEXEL_OFFSET:
409 return 7;
410
411 default:
412 R600_ERR("r600: unknown param %d\n", param);
413 return 0;
414 }
415 }
416
417 static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
418 {
419 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
420 enum radeon_family family = r600_get_family(rscreen->radeon);
421
422 switch (param) {
423 case PIPE_CAP_MAX_LINE_WIDTH:
424 case PIPE_CAP_MAX_LINE_WIDTH_AA:
425 case PIPE_CAP_MAX_POINT_WIDTH:
426 case PIPE_CAP_MAX_POINT_WIDTH_AA:
427 if (family >= CHIP_CEDAR)
428 return 16384.0f;
429 else
430 return 8192.0f;
431 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
432 return 16.0f;
433 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
434 return 16.0f;
435 default:
436 R600_ERR("r600: unsupported paramf %d\n", param);
437 return 0.0f;
438 }
439 }
440
441 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
442 {
443 switch(shader)
444 {
445 case PIPE_SHADER_FRAGMENT:
446 case PIPE_SHADER_VERTEX:
447 break;
448 case PIPE_SHADER_GEOMETRY:
449 /* TODO: support and enable geometry programs */
450 return 0;
451 default:
452 /* TODO: support tessellation on Evergreen */
453 return 0;
454 }
455
456 /* TODO: all these should be fixed, since r600 surely supports much more! */
457 switch (param) {
458 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
459 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
460 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
461 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
462 return 16384;
463 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
464 return 8; /* FIXME */
465 case PIPE_SHADER_CAP_MAX_INPUTS:
466 if(shader == PIPE_SHADER_FRAGMENT)
467 return 34;
468 else
469 return 32;
470 case PIPE_SHADER_CAP_MAX_TEMPS:
471 return 256; /* Max native temporaries. */
472 case PIPE_SHADER_CAP_MAX_ADDRS:
473 /* FIXME Isn't this equal to TEMPS? */
474 return 1; /* Max native address registers */
475 case PIPE_SHADER_CAP_MAX_CONSTS:
476 return R600_MAX_CONST_BUFFER_SIZE;
477 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
478 return R600_MAX_CONST_BUFFERS;
479 case PIPE_SHADER_CAP_MAX_PREDS:
480 return 0; /* FIXME */
481 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
482 return 1;
483 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
484 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
485 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
486 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
487 return 1;
488 case PIPE_SHADER_CAP_SUBROUTINES:
489 return 0;
490 case PIPE_SHADER_CAP_INTEGERS:
491 return 0;
492 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
493 return 16;
494 default:
495 return 0;
496 }
497 }
498
499 static int r600_get_video_param(struct pipe_screen *screen,
500 enum pipe_video_profile profile,
501 enum pipe_video_cap param)
502 {
503 switch (param) {
504 case PIPE_VIDEO_CAP_SUPPORTED:
505 return vl_profile_supported(screen, profile);
506 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
507 return 1;
508 case PIPE_VIDEO_CAP_MAX_WIDTH:
509 case PIPE_VIDEO_CAP_MAX_HEIGHT:
510 return vl_video_buffer_max_size(screen);
511 case PIPE_VIDEO_CAP_NUM_BUFFERS_DESIRED:
512 return vl_num_buffers_desired(screen, profile);
513 default:
514 return 0;
515 }
516 }
517
518 static void r600_destroy_screen(struct pipe_screen* pscreen)
519 {
520 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
521
522 if (rscreen == NULL)
523 return;
524
525 radeon_destroy(rscreen->radeon);
526 rscreen->ws->destroy(rscreen->ws);
527
528 util_slab_destroy(&rscreen->pool_buffers);
529 pipe_mutex_destroy(rscreen->mutex_num_contexts);
530 FREE(rscreen);
531 }
532
533 static void r600_fence_reference(struct pipe_screen *pscreen,
534 struct pipe_fence_handle **ptr,
535 struct pipe_fence_handle *fence)
536 {
537 struct r600_fence **oldf = (struct r600_fence**)ptr;
538 struct r600_fence *newf = (struct r600_fence*)fence;
539
540 if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
541 struct r600_pipe_context *ctx = (*oldf)->ctx;
542 LIST_ADDTAIL(&(*oldf)->head, &ctx->fences.pool);
543 }
544
545 *ptr = fence;
546 }
547
548 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
549 struct pipe_fence_handle *fence)
550 {
551 struct r600_fence *rfence = (struct r600_fence*)fence;
552 struct r600_pipe_context *ctx = rfence->ctx;
553
554 return ctx->fences.data[rfence->index];
555 }
556
557 static boolean r600_fence_finish(struct pipe_screen *pscreen,
558 struct pipe_fence_handle *fence,
559 uint64_t timeout)
560 {
561 struct r600_fence *rfence = (struct r600_fence*)fence;
562 struct r600_pipe_context *ctx = rfence->ctx;
563 int64_t start_time = 0;
564 unsigned spins = 0;
565
566 if (timeout != PIPE_TIMEOUT_INFINITE) {
567 start_time = os_time_get();
568
569 /* Convert to microseconds. */
570 timeout /= 1000;
571 }
572
573 while (ctx->fences.data[rfence->index] == 0) {
574 if (++spins % 256)
575 continue;
576 #ifdef PIPE_OS_UNIX
577 sched_yield();
578 #else
579 os_time_sleep(10);
580 #endif
581 if (timeout != PIPE_TIMEOUT_INFINITE &&
582 os_time_get() - start_time >= timeout) {
583 return FALSE;
584 }
585 }
586
587 return TRUE;
588 }
589
590 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
591 {
592 switch ((tiling_config & 0xe) >> 1) {
593 case 0:
594 rscreen->tiling_info.num_channels = 1;
595 break;
596 case 1:
597 rscreen->tiling_info.num_channels = 2;
598 break;
599 case 2:
600 rscreen->tiling_info.num_channels = 4;
601 break;
602 case 3:
603 rscreen->tiling_info.num_channels = 8;
604 break;
605 default:
606 return -EINVAL;
607 }
608
609 switch ((tiling_config & 0x30) >> 4) {
610 case 0:
611 rscreen->tiling_info.num_banks = 4;
612 break;
613 case 1:
614 rscreen->tiling_info.num_banks = 8;
615 break;
616 default:
617 return -EINVAL;
618
619 }
620 switch ((tiling_config & 0xc0) >> 6) {
621 case 0:
622 rscreen->tiling_info.group_bytes = 256;
623 break;
624 case 1:
625 rscreen->tiling_info.group_bytes = 512;
626 break;
627 default:
628 return -EINVAL;
629 }
630 return 0;
631 }
632
633 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
634 {
635 switch (tiling_config & 0xf) {
636 case 0:
637 rscreen->tiling_info.num_channels = 1;
638 break;
639 case 1:
640 rscreen->tiling_info.num_channels = 2;
641 break;
642 case 2:
643 rscreen->tiling_info.num_channels = 4;
644 break;
645 case 3:
646 rscreen->tiling_info.num_channels = 8;
647 break;
648 default:
649 return -EINVAL;
650 }
651
652 switch ((tiling_config & 0xf0) >> 4) {
653 case 0:
654 rscreen->tiling_info.num_banks = 4;
655 break;
656 case 1:
657 rscreen->tiling_info.num_banks = 8;
658 break;
659 case 2:
660 rscreen->tiling_info.num_banks = 16;
661 break;
662 default:
663 return -EINVAL;
664 }
665
666 switch ((tiling_config & 0xf00) >> 8) {
667 case 0:
668 rscreen->tiling_info.group_bytes = 256;
669 break;
670 case 1:
671 rscreen->tiling_info.group_bytes = 512;
672 break;
673 default:
674 return -EINVAL;
675 }
676 return 0;
677 }
678
679 static int r600_init_tiling(struct r600_screen *rscreen)
680 {
681 uint32_t tiling_config = rscreen->info.r600_tiling_config;
682
683 /* set default group bytes, overridden by tiling info ioctl */
684 if (r600_get_family_class(rscreen->radeon) <= R700) {
685 rscreen->tiling_info.group_bytes = 256;
686 } else {
687 rscreen->tiling_info.group_bytes = 512;
688 }
689
690 if (!tiling_config)
691 return 0;
692
693 if (r600_get_family_class(rscreen->radeon) <= R700) {
694 return r600_interpret_tiling(rscreen, tiling_config);
695 } else {
696 return evergreen_interpret_tiling(rscreen, tiling_config);
697 }
698 }
699
700 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
701 {
702 struct r600_screen *rscreen;
703 struct radeon *radeon = radeon_create(ws);
704 if (!radeon) {
705 return NULL;
706 }
707
708 rscreen = CALLOC_STRUCT(r600_screen);
709 if (rscreen == NULL) {
710 radeon_destroy(radeon);
711 return NULL;
712 }
713
714 rscreen->ws = ws;
715 rscreen->radeon = radeon;
716 ws->query_info(ws, &rscreen->info);
717
718 if (r600_init_tiling(rscreen)) {
719 radeon_destroy(radeon);
720 FREE(rscreen);
721 return NULL;
722 }
723
724 rscreen->screen.winsys = (struct pipe_winsys*)ws;
725 rscreen->screen.destroy = r600_destroy_screen;
726 rscreen->screen.get_name = r600_get_name;
727 rscreen->screen.get_vendor = r600_get_vendor;
728 rscreen->screen.get_param = r600_get_param;
729 rscreen->screen.get_shader_param = r600_get_shader_param;
730 rscreen->screen.get_paramf = r600_get_paramf;
731 rscreen->screen.get_video_param = r600_get_video_param;
732 if (r600_get_family_class(radeon) >= EVERGREEN) {
733 rscreen->screen.is_format_supported = evergreen_is_format_supported;
734 } else {
735 rscreen->screen.is_format_supported = r600_is_format_supported;
736 }
737 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
738 rscreen->screen.context_create = r600_create_context;
739 rscreen->screen.fence_reference = r600_fence_reference;
740 rscreen->screen.fence_signalled = r600_fence_signalled;
741 rscreen->screen.fence_finish = r600_fence_finish;
742 r600_init_screen_resource_functions(&rscreen->screen);
743
744 util_format_s3tc_init();
745
746 util_slab_create(&rscreen->pool_buffers,
747 sizeof(struct r600_resource), 64,
748 UTIL_SLAB_SINGLETHREADED);
749
750 pipe_mutex_init(rscreen->mutex_num_contexts);
751
752 return &rscreen->screen;
753 }