2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "tgsi/tgsi_scan.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31 #include "util/u_blitter.h"
32 #include "util/u_double_list.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_transfer.h"
36 #include "util/u_surface.h"
37 #include "util/u_pack_color.h"
38 #include "util/u_memory.h"
39 #include "util/u_inlines.h"
40 #include "util/u_upload_mgr.h"
41 #include "vl/vl_decoder.h"
42 #include "vl/vl_video_buffer.h"
43 #include "os/os_time.h"
44 #include "pipebuffer/pb_buffer.h"
47 #include "r600_resource.h"
48 #include "r600_shader.h"
49 #include "r600_pipe.h"
50 #include "r600_hw_context_priv.h"
55 static struct r600_fence
*r600_create_fence(struct r600_context
*rctx
)
57 struct r600_screen
*rscreen
= rctx
->screen
;
58 struct r600_fence
*fence
= NULL
;
60 pipe_mutex_lock(rscreen
->fences
.mutex
);
62 if (!rscreen
->fences
.bo
) {
63 /* Create the shared buffer object */
64 rscreen
->fences
.bo
= (struct r600_resource
*)
65 pipe_buffer_create(&rscreen
->screen
, PIPE_BIND_CUSTOM
,
66 PIPE_USAGE_STAGING
, 4096);
67 if (!rscreen
->fences
.bo
) {
68 R600_ERR("r600: failed to create bo for fence objects\n");
71 rscreen
->fences
.data
= rctx
->ws
->buffer_map(rscreen
->fences
.bo
->buf
,
73 PIPE_TRANSFER_READ_WRITE
);
76 if (!LIST_IS_EMPTY(&rscreen
->fences
.pool
)) {
77 struct r600_fence
*entry
;
79 /* Try to find a freed fence that has been signalled */
80 LIST_FOR_EACH_ENTRY(entry
, &rscreen
->fences
.pool
, head
) {
81 if (rscreen
->fences
.data
[entry
->index
] != 0) {
82 LIST_DELINIT(&entry
->head
);
90 /* Allocate a new fence */
91 struct r600_fence_block
*block
;
94 if ((rscreen
->fences
.next_index
+ 1) >= 1024) {
95 R600_ERR("r600: too many concurrent fences\n");
99 index
= rscreen
->fences
.next_index
++;
101 if (!(index
% FENCE_BLOCK_SIZE
)) {
102 /* Allocate a new block */
103 block
= CALLOC_STRUCT(r600_fence_block
);
107 LIST_ADD(&block
->head
, &rscreen
->fences
.blocks
);
109 block
= LIST_ENTRY(struct r600_fence_block
, rscreen
->fences
.blocks
.next
, head
);
112 fence
= &block
->fences
[index
% FENCE_BLOCK_SIZE
];
113 fence
->index
= index
;
116 pipe_reference_init(&fence
->reference
, 1);
118 rscreen
->fences
.data
[fence
->index
] = 0;
119 r600_context_emit_fence(rctx
, rscreen
->fences
.bo
, fence
->index
, 1);
121 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
122 fence
->sleep_bo
= (struct r600_resource
*)
123 pipe_buffer_create(&rctx
->screen
->screen
, PIPE_BIND_CUSTOM
,
124 PIPE_USAGE_STAGING
, 1);
125 /* Add the fence as a dummy relocation. */
126 r600_context_bo_reloc(rctx
, fence
->sleep_bo
, RADEON_USAGE_READWRITE
);
129 pipe_mutex_unlock(rscreen
->fences
.mutex
);
134 void r600_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
137 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
138 struct r600_fence
**rfence
= (struct r600_fence
**)fence
;
139 struct pipe_query
*render_cond
= NULL
;
140 unsigned render_cond_mode
= 0;
143 *rfence
= r600_create_fence(rctx
);
145 /* Disable render condition. */
146 if (rctx
->current_render_cond
) {
147 render_cond
= rctx
->current_render_cond
;
148 render_cond_mode
= rctx
->current_render_cond_mode
;
149 ctx
->render_condition(ctx
, NULL
, 0);
152 r600_context_flush(rctx
, flags
);
154 /* Re-enable render condition. */
156 ctx
->render_condition(ctx
, render_cond
, render_cond_mode
);
160 static void r600_flush_from_st(struct pipe_context
*ctx
,
161 struct pipe_fence_handle
**fence
)
163 r600_flush(ctx
, fence
, 0);
166 static void r600_flush_from_winsys(void *ctx
, unsigned flags
)
168 r600_flush((struct pipe_context
*)ctx
, NULL
, flags
);
171 static void r600_update_num_contexts(struct r600_screen
*rscreen
, int diff
)
173 pipe_mutex_lock(rscreen
->mutex_num_contexts
);
175 rscreen
->num_contexts
++;
177 if (rscreen
->num_contexts
> 1)
178 util_slab_set_thread_safety(&rscreen
->pool_buffers
,
179 UTIL_SLAB_MULTITHREADED
);
181 rscreen
->num_contexts
--;
183 if (rscreen
->num_contexts
<= 1)
184 util_slab_set_thread_safety(&rscreen
->pool_buffers
,
185 UTIL_SLAB_SINGLETHREADED
);
187 pipe_mutex_unlock(rscreen
->mutex_num_contexts
);
190 static void r600_destroy_context(struct pipe_context
*context
)
192 struct r600_context
*rctx
= (struct r600_context
*)context
;
194 if (rctx
->custom_dsa_flush
) {
195 rctx
->context
.delete_depth_stencil_alpha_state(&rctx
->context
, rctx
->custom_dsa_flush
);
197 util_unreference_framebuffer_state(&rctx
->framebuffer
);
199 r600_context_fini(rctx
);
202 util_blitter_destroy(rctx
->blitter
);
204 for (int i
= 0; i
< R600_PIPE_NSTATES
; i
++) {
205 free(rctx
->states
[i
]);
208 if (rctx
->vbuf_mgr
) {
209 u_vbuf_destroy(rctx
->vbuf_mgr
);
211 util_slab_destroy(&rctx
->pool_transfers
);
213 r600_update_num_contexts(rctx
->screen
, -1);
215 r600_release_command_buffer(&rctx
->atom_start_cs
);
218 rctx
->ws
->cs_destroy(rctx
->cs
);
225 static struct pipe_context
*r600_create_context(struct pipe_screen
*screen
, void *priv
)
227 struct r600_context
*rctx
= CALLOC_STRUCT(r600_context
);
228 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
233 util_slab_create(&rctx
->pool_transfers
,
234 sizeof(struct pipe_transfer
), 64,
235 UTIL_SLAB_SINGLETHREADED
);
237 r600_update_num_contexts(rscreen
, 1);
239 rctx
->context
.screen
= screen
;
240 rctx
->context
.priv
= priv
;
241 rctx
->context
.destroy
= r600_destroy_context
;
242 rctx
->context
.flush
= r600_flush_from_st
;
244 /* Easy accessing of screen/winsys. */
245 rctx
->screen
= rscreen
;
246 rctx
->ws
= rscreen
->ws
;
247 rctx
->family
= rscreen
->family
;
248 rctx
->chip_class
= rscreen
->chip_class
;
250 LIST_INITHEAD(&rctx
->dirty_states
);
251 LIST_INITHEAD(&rctx
->active_query_list
);
252 LIST_INITHEAD(&rctx
->dirty
);
253 LIST_INITHEAD(&rctx
->resource_dirty
);
254 LIST_INITHEAD(&rctx
->enable_list
);
256 rctx
->range
= CALLOC(NUM_RANGES
, sizeof(struct r600_range
));
260 r600_init_blit_functions(rctx
);
261 r600_init_query_functions(rctx
);
262 r600_init_context_resource_functions(rctx
);
263 r600_init_surface_functions(rctx
);
264 rctx
->context
.draw_vbo
= r600_draw_vbo
;
266 rctx
->context
.create_video_decoder
= vl_create_decoder
;
267 rctx
->context
.create_video_buffer
= vl_video_buffer_create
;
269 r600_init_common_atoms(rctx
);
271 switch (rctx
->chip_class
) {
274 r600_init_state_functions(rctx
);
275 r600_init_atom_start_cs(rctx
);
276 if (r600_context_init(rctx
))
278 rctx
->custom_dsa_flush
= r600_create_db_flush_dsa(rctx
);
282 evergreen_init_state_functions(rctx
);
283 evergreen_init_atom_start_cs(rctx
);
284 if (evergreen_context_init(rctx
))
286 rctx
->custom_dsa_flush
= evergreen_create_db_flush_dsa(rctx
);
289 R600_ERR("Unsupported chip class %d.\n", rctx
->chip_class
);
293 rctx
->cs
= rctx
->ws
->cs_create(rctx
->ws
);
294 rctx
->ws
->cs_set_flush_callback(rctx
->cs
, r600_flush_from_winsys
, rctx
);
295 r600_emit_atom(rctx
, &rctx
->atom_start_cs
.atom
);
297 rctx
->vbuf_mgr
= u_vbuf_create(&rctx
->context
, 1024 * 1024, 256,
298 PIPE_BIND_VERTEX_BUFFER
|
299 PIPE_BIND_INDEX_BUFFER
|
300 PIPE_BIND_CONSTANT_BUFFER
,
301 U_VERTEX_FETCH_DWORD_ALIGNED
);
304 rctx
->vbuf_mgr
->caps
.format_fixed32
= 0;
306 rctx
->blitter
= util_blitter_create(&rctx
->context
);
307 if (rctx
->blitter
== NULL
)
310 r600_get_backend_mask(rctx
); /* this emits commands and must be last */
312 return &rctx
->context
;
315 r600_destroy_context(&rctx
->context
);
322 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
327 static const char *r600_get_family_name(enum radeon_family family
)
330 case CHIP_R600
: return "AMD R600";
331 case CHIP_RV610
: return "AMD RV610";
332 case CHIP_RV630
: return "AMD RV630";
333 case CHIP_RV670
: return "AMD RV670";
334 case CHIP_RV620
: return "AMD RV620";
335 case CHIP_RV635
: return "AMD RV635";
336 case CHIP_RS780
: return "AMD RS780";
337 case CHIP_RS880
: return "AMD RS880";
338 case CHIP_RV770
: return "AMD RV770";
339 case CHIP_RV730
: return "AMD RV730";
340 case CHIP_RV710
: return "AMD RV710";
341 case CHIP_RV740
: return "AMD RV740";
342 case CHIP_CEDAR
: return "AMD CEDAR";
343 case CHIP_REDWOOD
: return "AMD REDWOOD";
344 case CHIP_JUNIPER
: return "AMD JUNIPER";
345 case CHIP_CYPRESS
: return "AMD CYPRESS";
346 case CHIP_HEMLOCK
: return "AMD HEMLOCK";
347 case CHIP_PALM
: return "AMD PALM";
348 case CHIP_SUMO
: return "AMD SUMO";
349 case CHIP_SUMO2
: return "AMD SUMO2";
350 case CHIP_BARTS
: return "AMD BARTS";
351 case CHIP_TURKS
: return "AMD TURKS";
352 case CHIP_CAICOS
: return "AMD CAICOS";
353 case CHIP_CAYMAN
: return "AMD CAYMAN";
354 default: return "AMD unknown";
358 static const char* r600_get_name(struct pipe_screen
* pscreen
)
360 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
362 return r600_get_family_name(rscreen
->family
);
365 static int r600_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
367 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
368 enum radeon_family family
= rscreen
->family
;
371 /* Supported features (boolean caps). */
372 case PIPE_CAP_NPOT_TEXTURES
:
373 case PIPE_CAP_TWO_SIDED_STENCIL
:
374 case PIPE_CAP_DUAL_SOURCE_BLEND
:
375 case PIPE_CAP_ANISOTROPIC_FILTER
:
376 case PIPE_CAP_POINT_SPRITE
:
377 case PIPE_CAP_OCCLUSION_QUERY
:
378 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
379 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
380 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
381 case PIPE_CAP_TEXTURE_SWIZZLE
:
382 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE
:
383 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
384 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
385 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
386 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
387 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
388 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
390 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
391 case PIPE_CAP_PRIMITIVE_RESTART
:
392 case PIPE_CAP_CONDITIONAL_RENDER
:
393 case PIPE_CAP_TEXTURE_BARRIER
:
394 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
395 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
398 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
399 return debug_get_bool_option("R600_GLSL130", FALSE
) ? 130 : 120;
401 /* Supported except the original R600. */
402 case PIPE_CAP_INDEP_BLEND_ENABLE
:
403 case PIPE_CAP_INDEP_BLEND_FUNC
:
404 /* R600 doesn't support per-MRT blends */
405 return family
== CHIP_R600
? 0 : 1;
407 /* Supported on Evergreen. */
408 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
409 return family
>= CHIP_CEDAR
? 1 : 0;
411 /* Unsupported features. */
412 case PIPE_CAP_TGSI_INSTANCEID
:
413 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
414 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
415 case PIPE_CAP_SCALED_RESOLVE
:
416 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS
:
417 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
418 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
419 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
423 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
424 return debug_get_bool_option("R600_STREAMOUT", FALSE
) ? 4 : 0;
425 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
426 return debug_get_bool_option("R600_STREAMOUT", FALSE
) ? 1 : 0;
427 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
428 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
432 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
433 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
434 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
435 if (family
>= CHIP_CEDAR
)
439 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
440 return rscreen
->info
.drm_minor
>= 9 ?
441 (family
>= CHIP_CEDAR
? 16384 : 8192) : 0;
442 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
445 /* Render targets. */
446 case PIPE_CAP_MAX_RENDER_TARGETS
:
447 /* FIXME some r6xx are buggy and can only do 4 */
450 /* Timer queries, present when the clock frequency is non zero. */
451 case PIPE_CAP_TIMER_QUERY
:
452 return rscreen
->info
.r600_clock_crystal_freq
!= 0;
454 case PIPE_CAP_MIN_TEXEL_OFFSET
:
457 case PIPE_CAP_MAX_TEXEL_OFFSET
:
463 static float r600_get_paramf(struct pipe_screen
* pscreen
,
464 enum pipe_capf param
)
466 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
467 enum radeon_family family
= rscreen
->family
;
470 case PIPE_CAPF_MAX_LINE_WIDTH
:
471 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
472 case PIPE_CAPF_MAX_POINT_WIDTH
:
473 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
474 if (family
>= CHIP_CEDAR
)
478 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
480 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
482 case PIPE_CAPF_GUARD_BAND_LEFT
:
483 case PIPE_CAPF_GUARD_BAND_TOP
:
484 case PIPE_CAPF_GUARD_BAND_RIGHT
:
485 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
491 static int r600_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
495 case PIPE_SHADER_FRAGMENT
:
496 case PIPE_SHADER_VERTEX
:
498 case PIPE_SHADER_GEOMETRY
:
499 /* TODO: support and enable geometry programs */
502 /* TODO: support tessellation on Evergreen */
506 /* TODO: all these should be fixed, since r600 surely supports much more! */
508 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
509 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
510 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
511 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
513 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
514 return 8; /* FIXME */
515 case PIPE_SHADER_CAP_MAX_INPUTS
:
516 if(shader
== PIPE_SHADER_FRAGMENT
)
520 case PIPE_SHADER_CAP_MAX_TEMPS
:
521 return 256; /* Max native temporaries. */
522 case PIPE_SHADER_CAP_MAX_ADDRS
:
523 /* FIXME Isn't this equal to TEMPS? */
524 return 1; /* Max native address registers */
525 case PIPE_SHADER_CAP_MAX_CONSTS
:
526 return R600_MAX_CONST_BUFFER_SIZE
;
527 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
528 return R600_MAX_CONST_BUFFERS
-1;
529 case PIPE_SHADER_CAP_MAX_PREDS
:
530 return 0; /* FIXME */
531 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
533 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
534 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
535 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
536 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
538 case PIPE_SHADER_CAP_SUBROUTINES
:
540 case PIPE_SHADER_CAP_INTEGERS
:
542 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
548 static int r600_get_video_param(struct pipe_screen
*screen
,
549 enum pipe_video_profile profile
,
550 enum pipe_video_cap param
)
553 case PIPE_VIDEO_CAP_SUPPORTED
:
554 return vl_profile_supported(screen
, profile
);
555 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
557 case PIPE_VIDEO_CAP_MAX_WIDTH
:
558 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
559 return vl_video_buffer_max_size(screen
);
560 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
561 return PIPE_FORMAT_NV12
;
562 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
564 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
566 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
573 static void r600_destroy_screen(struct pipe_screen
* pscreen
)
575 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
580 if (rscreen
->fences
.bo
) {
581 struct r600_fence_block
*entry
, *tmp
;
583 LIST_FOR_EACH_ENTRY_SAFE(entry
, tmp
, &rscreen
->fences
.blocks
, head
) {
584 LIST_DEL(&entry
->head
);
588 rscreen
->ws
->buffer_unmap(rscreen
->fences
.bo
->buf
);
589 pipe_resource_reference((struct pipe_resource
**)&rscreen
->fences
.bo
, NULL
);
591 pipe_mutex_destroy(rscreen
->fences
.mutex
);
593 rscreen
->ws
->destroy(rscreen
->ws
);
595 util_slab_destroy(&rscreen
->pool_buffers
);
596 pipe_mutex_destroy(rscreen
->mutex_num_contexts
);
600 static void r600_fence_reference(struct pipe_screen
*pscreen
,
601 struct pipe_fence_handle
**ptr
,
602 struct pipe_fence_handle
*fence
)
604 struct r600_fence
**oldf
= (struct r600_fence
**)ptr
;
605 struct r600_fence
*newf
= (struct r600_fence
*)fence
;
607 if (pipe_reference(&(*oldf
)->reference
, &newf
->reference
)) {
608 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
609 pipe_mutex_lock(rscreen
->fences
.mutex
);
610 pipe_resource_reference((struct pipe_resource
**)&(*oldf
)->sleep_bo
, NULL
);
611 LIST_ADDTAIL(&(*oldf
)->head
, &rscreen
->fences
.pool
);
612 pipe_mutex_unlock(rscreen
->fences
.mutex
);
618 static boolean
r600_fence_signalled(struct pipe_screen
*pscreen
,
619 struct pipe_fence_handle
*fence
)
621 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
622 struct r600_fence
*rfence
= (struct r600_fence
*)fence
;
624 return rscreen
->fences
.data
[rfence
->index
];
627 static boolean
r600_fence_finish(struct pipe_screen
*pscreen
,
628 struct pipe_fence_handle
*fence
,
631 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
632 struct r600_fence
*rfence
= (struct r600_fence
*)fence
;
633 int64_t start_time
= 0;
636 if (timeout
!= PIPE_TIMEOUT_INFINITE
) {
637 start_time
= os_time_get();
639 /* Convert to microseconds. */
643 while (rscreen
->fences
.data
[rfence
->index
] == 0) {
644 /* Special-case infinite timeout - wait for the dummy BO to become idle */
645 if (timeout
== PIPE_TIMEOUT_INFINITE
) {
646 rscreen
->ws
->buffer_wait(rfence
->sleep_bo
->buf
, RADEON_USAGE_READWRITE
);
650 /* The dummy BO will be busy until the CS including the fence has completed, or
651 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
652 if (!rscreen
->ws
->buffer_is_busy(rfence
->sleep_bo
->buf
, RADEON_USAGE_READWRITE
))
662 if (timeout
!= PIPE_TIMEOUT_INFINITE
&&
663 os_time_get() - start_time
>= timeout
) {
668 return rscreen
->fences
.data
[rfence
->index
] != 0;
671 static int r600_interpret_tiling(struct r600_screen
*rscreen
, uint32_t tiling_config
)
673 switch ((tiling_config
& 0xe) >> 1) {
675 rscreen
->tiling_info
.num_channels
= 1;
678 rscreen
->tiling_info
.num_channels
= 2;
681 rscreen
->tiling_info
.num_channels
= 4;
684 rscreen
->tiling_info
.num_channels
= 8;
690 switch ((tiling_config
& 0x30) >> 4) {
692 rscreen
->tiling_info
.num_banks
= 4;
695 rscreen
->tiling_info
.num_banks
= 8;
701 switch ((tiling_config
& 0xc0) >> 6) {
703 rscreen
->tiling_info
.group_bytes
= 256;
706 rscreen
->tiling_info
.group_bytes
= 512;
714 static int evergreen_interpret_tiling(struct r600_screen
*rscreen
, uint32_t tiling_config
)
716 switch (tiling_config
& 0xf) {
718 rscreen
->tiling_info
.num_channels
= 1;
721 rscreen
->tiling_info
.num_channels
= 2;
724 rscreen
->tiling_info
.num_channels
= 4;
727 rscreen
->tiling_info
.num_channels
= 8;
733 switch ((tiling_config
& 0xf0) >> 4) {
735 rscreen
->tiling_info
.num_banks
= 4;
738 rscreen
->tiling_info
.num_banks
= 8;
741 rscreen
->tiling_info
.num_banks
= 16;
747 switch ((tiling_config
& 0xf00) >> 8) {
749 rscreen
->tiling_info
.group_bytes
= 256;
752 rscreen
->tiling_info
.group_bytes
= 512;
760 static int r600_init_tiling(struct r600_screen
*rscreen
)
762 uint32_t tiling_config
= rscreen
->info
.r600_tiling_config
;
764 /* set default group bytes, overridden by tiling info ioctl */
765 if (rscreen
->chip_class
<= R700
) {
766 rscreen
->tiling_info
.group_bytes
= 256;
768 rscreen
->tiling_info
.group_bytes
= 512;
774 if (rscreen
->chip_class
<= R700
) {
775 return r600_interpret_tiling(rscreen
, tiling_config
);
777 return evergreen_interpret_tiling(rscreen
, tiling_config
);
781 static unsigned radeon_family_from_device(unsigned device
)
784 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
785 #include "pci_ids/r600_pci_ids.h"
792 struct pipe_screen
*r600_screen_create(struct radeon_winsys
*ws
)
794 struct r600_screen
*rscreen
= CALLOC_STRUCT(r600_screen
);
795 if (rscreen
== NULL
) {
800 ws
->query_info(ws
, &rscreen
->info
);
802 rscreen
->family
= radeon_family_from_device(rscreen
->info
.pci_id
);
803 if (rscreen
->family
== CHIP_UNKNOWN
) {
804 fprintf(stderr
, "r600: Unknown chipset 0x%04X\n", rscreen
->info
.pci_id
);
810 if (rscreen
->family
== CHIP_CAYMAN
) {
811 rscreen
->chip_class
= CAYMAN
;
812 } else if (rscreen
->family
>= CHIP_CEDAR
) {
813 rscreen
->chip_class
= EVERGREEN
;
814 } else if (rscreen
->family
>= CHIP_RV770
) {
815 rscreen
->chip_class
= R700
;
817 rscreen
->chip_class
= R600
;
820 if (r600_init_tiling(rscreen
)) {
825 rscreen
->screen
.destroy
= r600_destroy_screen
;
826 rscreen
->screen
.get_name
= r600_get_name
;
827 rscreen
->screen
.get_vendor
= r600_get_vendor
;
828 rscreen
->screen
.get_param
= r600_get_param
;
829 rscreen
->screen
.get_shader_param
= r600_get_shader_param
;
830 rscreen
->screen
.get_paramf
= r600_get_paramf
;
831 rscreen
->screen
.get_video_param
= r600_get_video_param
;
832 if (rscreen
->chip_class
>= EVERGREEN
) {
833 rscreen
->screen
.is_format_supported
= evergreen_is_format_supported
;
835 rscreen
->screen
.is_format_supported
= r600_is_format_supported
;
837 rscreen
->screen
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
838 rscreen
->screen
.context_create
= r600_create_context
;
839 rscreen
->screen
.fence_reference
= r600_fence_reference
;
840 rscreen
->screen
.fence_signalled
= r600_fence_signalled
;
841 rscreen
->screen
.fence_finish
= r600_fence_finish
;
842 r600_init_screen_resource_functions(&rscreen
->screen
);
844 util_format_s3tc_init();
846 util_slab_create(&rscreen
->pool_buffers
,
847 sizeof(struct r600_resource
), 64,
848 UTIL_SLAB_SINGLETHREADED
);
850 pipe_mutex_init(rscreen
->mutex_num_contexts
);
852 rscreen
->fences
.bo
= NULL
;
853 rscreen
->fences
.data
= NULL
;
854 rscreen
->fences
.next_index
= 0;
855 LIST_INITHEAD(&rscreen
->fences
.pool
);
856 LIST_INITHEAD(&rscreen
->fences
.blocks
);
857 pipe_mutex_init(rscreen
->fences
.mutex
);
859 return &rscreen
->screen
;